From patchwork Thu Dec 22 11:48:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 636133 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 592D0C3DA7D for ; Thu, 22 Dec 2022 11:54:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235566AbiLVLyO (ORCPT ); Thu, 22 Dec 2022 06:54:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235530AbiLVLwz (ORCPT ); Thu, 22 Dec 2022 06:52:55 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 007682934B; Thu, 22 Dec 2022 03:49:20 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 453746602CD8; Thu, 22 Dec 2022 11:49:17 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671709758; bh=X/oZl8ocJQt071EbQHuHIaXUvTU5xZlpFyUlUhGeBQk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FBt+uV3u8xFLavYUouyD4THDFwqNxoEaHEktDIVywjGjckt0EtRQhDAHPLAAUdEBZ FXxNXT6XYiEoWOOqu46VAGLb2OYaGlo9JIsdqREMitXhu4/tB0YzsIk0cyVyEh4+MV DlyWwiY6Fle3lyyQyUhvnCUNHAptdtlz3cY8KYn3jHoEFUvOmdjVfNm8sa5TVySoFk 6RZEFg7F9VzOrFl7K7yoo3+vhM0/A7ER9QjiF3k24cGAQYMzTzWN++itIqUw1kn2Yk YkD2h/lonXVHUTbBqDdOATpj1Sd6AXksbox0UJKrdvmjuJZ3kM9bCz4WGCO5rs65mj dl2bpJVT5qmXQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v1 02/25] clk: mediatek: mt8192: Propagate struct device for gate clocks Date: Thu, 22 Dec 2022 12:48:34 +0100 Message-Id: <20221222114857.120060-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> References: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert instances of mtk_clk_register_gates() to use the newer mtk_clk_register_gates_with_dev() to propagate struct device to the clk framework. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8192.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index eff66ca6c6a7..991d78a71644 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1127,7 +1127,8 @@ static int clk_mt8192_top_probe(struct platform_device *pdev) if (r) goto unregister_top_composites; - r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data); + r = mtk_clk_register_gates_with_dev(node, top_clks, ARRAY_SIZE(top_clks), + top_clk_data, &pdev->dev); if (r) goto unregister_adj_divs_composites; @@ -1167,7 +1168,8 @@ static int clk_mt8192_infra_probe(struct platform_device *pdev) if (!clk_data) return -ENOMEM; - r = mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data); + r = mtk_clk_register_gates_with_dev(node, infra_clks, ARRAY_SIZE(infra_clks), + clk_data, &pdev->dev); if (r) goto free_clk_data; @@ -1198,7 +1200,8 @@ static int clk_mt8192_peri_probe(struct platform_device *pdev) if (!clk_data) return -ENOMEM; - r = mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), clk_data); + r = mtk_clk_register_gates_with_dev(node, peri_clks, ARRAY_SIZE(peri_clks), + clk_data, &pdev->dev); if (r) goto free_clk_data; @@ -1226,7 +1229,9 @@ static int clk_mt8192_apmixed_probe(struct platform_device *pdev) return -ENOMEM; mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - r = mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); + r = mtk_clk_register_gates_with_dev(node, apmixed_clks, + ARRAY_SIZE(apmixed_clks), clk_data, + &pdev->dev); if (r) goto free_clk_data; From patchwork Thu Dec 22 11:48:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 636132 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7CE44C001B2 for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671709760; bh=xMZiAKwpe53kZFQbADFekhYR4L86oA0T01+MfIvvLHU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=N1Xbs96oIBFmKl4BZg/5lT9Y9pQXveVEX+EevdFxtYDG5Vbm9XGGlMKtZX2S98aXw 1rZkrtW8xBKNiPq1arfgpcd4OUQYrP/UwFyGnzY4XU6TNzTNVXvG5dj7W5966QmzeC fENpw+59z53RZntkuHdD0ahAZRUJv/MDtfQqYjUj6hlwviltpc0WJSi4wg3VEUIyNL eeq/v2mPQE9kNB2QXSKb5xk0pXZ5uaj49l2bsQTSfrUjb4/Yf39jcDxgBydsAAKd9m 5+6JXZidHiqakBCgJ1HU7sdsJ4yLAKEdNwJNfFw1z3A497Ghj3VnpyntyJQR93yUSs 0fCLr2h9LKECw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v1 03/25] clk: mediatek: clk-gate: Propagate struct device with mtk_clk_register_gates() Date: Thu, 22 Dec 2022 12:48:35 +0100 Message-Id: <20221222114857.120060-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> References: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Commit e4c23e19aa2a ("clk: mediatek: Register clock gate with device") introduces a helper function for the sole purpose of propagating a struct device pointer to the clk API when registering the mtk-gate clocks to take advantage of Runtime PM when/where needed and where a power domain is defined in devicetree. Function mtk_clk_register_gates() then becomes a wrapper around the new mtk_clk_register_gates_with_dev() function that will simply pass NULL as struct device: this is essential when registering drivers with CLK_OF_DECLARE instead of as a platform device, as there will be no struct device to pass... but we can as well simply have only one function that always takes such pointer as a param and pass NULL when unavoidable. This commit removes the mtk_clk_register_gates() wrapper and renames mtk_clk_register_gates_with_dev() to the former and all of the calls to either of the two functions were fixed in all drivers in order to reflect this change. Since a lot of MediaTek clock drivers are actually registering as a platform device, but were still registering the mtk-gate clocks without passing any struct device to the clock framework, they've been changed to pass a valid one now, as to make all those platforms able to use runtime power management where available. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-gate.c | 16 ++++------------ drivers/clk/mediatek/clk-gate.h | 8 ++------ drivers/clk/mediatek/clk-mt2701-aud.c | 2 +- drivers/clk/mediatek/clk-mt2701-eth.c | 2 +- drivers/clk/mediatek/clk-mt2701-g3d.c | 2 +- drivers/clk/mediatek/clk-mt2701-hif.c | 2 +- drivers/clk/mediatek/clk-mt2701-mm.c | 2 +- drivers/clk/mediatek/clk-mt2701.c | 6 +++--- drivers/clk/mediatek/clk-mt2712-mm.c | 2 +- drivers/clk/mediatek/clk-mt2712.c | 6 +++--- drivers/clk/mediatek/clk-mt6765.c | 6 +++--- drivers/clk/mediatek/clk-mt6779-mm.c | 2 +- drivers/clk/mediatek/clk-mt6779.c | 4 ++-- drivers/clk/mediatek/clk-mt6795-infracfg.c | 3 ++- drivers/clk/mediatek/clk-mt6795-mm.c | 3 ++- drivers/clk/mediatek/clk-mt6795-pericfg.c | 3 ++- drivers/clk/mediatek/clk-mt6797-mm.c | 2 +- drivers/clk/mediatek/clk-mt6797.c | 2 +- drivers/clk/mediatek/clk-mt7622-aud.c | 2 +- drivers/clk/mediatek/clk-mt7622-eth.c | 4 ++-- drivers/clk/mediatek/clk-mt7622-hif.c | 4 ++-- drivers/clk/mediatek/clk-mt7622.c | 9 +++++---- drivers/clk/mediatek/clk-mt7629-eth.c | 5 +++-- drivers/clk/mediatek/clk-mt7629-hif.c | 4 ++-- drivers/clk/mediatek/clk-mt7629.c | 6 +++--- drivers/clk/mediatek/clk-mt7986-eth.c | 6 +++--- drivers/clk/mediatek/clk-mt7986-infracfg.c | 2 +- drivers/clk/mediatek/clk-mt8135.c | 4 ++-- drivers/clk/mediatek/clk-mt8167-aud.c | 2 +- drivers/clk/mediatek/clk-mt8167-img.c | 2 +- drivers/clk/mediatek/clk-mt8167-mfgcfg.c | 2 +- drivers/clk/mediatek/clk-mt8167-mm.c | 2 +- drivers/clk/mediatek/clk-mt8167-vdec.c | 3 ++- drivers/clk/mediatek/clk-mt8167.c | 2 +- drivers/clk/mediatek/clk-mt8173-mm.c | 2 +- drivers/clk/mediatek/clk-mt8173.c | 12 ++++++------ drivers/clk/mediatek/clk-mt8183-audio.c | 2 +- drivers/clk/mediatek/clk-mt8183-mm.c | 2 +- drivers/clk/mediatek/clk-mt8183.c | 8 ++++---- drivers/clk/mediatek/clk-mt8186-mm.c | 3 ++- drivers/clk/mediatek/clk-mt8192-aud.c | 3 ++- drivers/clk/mediatek/clk-mt8192-mm.c | 3 ++- drivers/clk/mediatek/clk-mt8192.c | 12 ++++++------ drivers/clk/mediatek/clk-mt8195-apmixedsys.c | 3 ++- drivers/clk/mediatek/clk-mt8195-topckgen.c | 3 ++- drivers/clk/mediatek/clk-mt8195-vdo0.c | 3 ++- drivers/clk/mediatek/clk-mt8195-vdo1.c | 3 ++- drivers/clk/mediatek/clk-mt8365-mm.c | 5 ++--- drivers/clk/mediatek/clk-mt8365.c | 2 +- drivers/clk/mediatek/clk-mt8516-aud.c | 2 +- drivers/clk/mediatek/clk-mt8516.c | 2 +- drivers/clk/mediatek/clk-mtk.c | 4 ++-- 52 files changed, 103 insertions(+), 103 deletions(-) diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c index 0c867136e49d..80deaabfd848 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -202,10 +202,10 @@ static void mtk_clk_unregister_gate(struct clk_hw *hw) kfree(cg); } -int mtk_clk_register_gates_with_dev(struct device_node *node, - const struct mtk_gate *clks, int num, - struct clk_hw_onecell_data *clk_data, - struct device *dev) +int mtk_clk_register_gates(struct device_node *node, + const struct mtk_gate *clks, int num, + struct clk_hw_onecell_data *clk_data, + struct device *dev) { int i; struct clk_hw *hw; @@ -261,14 +261,6 @@ int mtk_clk_register_gates_with_dev(struct device_node *node, return PTR_ERR(hw); } -EXPORT_SYMBOL_GPL(mtk_clk_register_gates_with_dev); - -int mtk_clk_register_gates(struct device_node *node, - const struct mtk_gate *clks, int num, - struct clk_hw_onecell_data *clk_data) -{ - return mtk_clk_register_gates_with_dev(node, clks, num, clk_data, NULL); -} EXPORT_SYMBOL_GPL(mtk_clk_register_gates); void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num, diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h index d9897ef53528..03053c2c2fdd 100644 --- a/drivers/clk/mediatek/clk-gate.h +++ b/drivers/clk/mediatek/clk-gate.h @@ -52,12 +52,8 @@ struct mtk_gate { int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks, int num, - struct clk_hw_onecell_data *clk_data); - -int mtk_clk_register_gates_with_dev(struct device_node *node, - const struct mtk_gate *clks, int num, - struct clk_hw_onecell_data *clk_data, - struct device *dev); + struct clk_hw_onecell_data *clk_data, + struct device *dev); void mtk_clk_unregister_gates(const struct mtk_gate *clks, int num, struct clk_hw_onecell_data *clk_data); diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/clk-mt2701-aud.c index 6ba398eb7df9..ab13ab618fb5 100644 --- a/drivers/clk/mediatek/clk-mt2701-aud.c +++ b/drivers/clk/mediatek/clk-mt2701-aud.c @@ -152,7 +152,7 @@ static int clk_mt2701_aud_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_AUD_NR); mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index edf1e2ed2b59..9670e1e170f2 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -58,7 +58,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR); mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index 1458109d99d9..11391b144267 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -52,7 +52,7 @@ static int clk_mt2701_g3dsys_init(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR); mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index 434cbbe8c037..c14c0bb10f88 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -55,7 +55,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR); mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { diff --git a/drivers/clk/mediatek/clk-mt2701-mm.c b/drivers/clk/mediatek/clk-mt2701-mm.c index 9ea7abad99d2..ec5e516ca099 100644 --- a/drivers/clk/mediatek/clk-mt2701-mm.c +++ b/drivers/clk/mediatek/clk-mt2701-mm.c @@ -89,7 +89,7 @@ static int clk_mt2701_mm_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_MM_NR); mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index 9b442af37e67..dff69fabb171 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -690,7 +690,7 @@ static int mtk_topckgen_init(struct platform_device *pdev) base, &mt2701_clk_lock, clk_data); mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), - clk_data); + clk_data, &pdev->dev); return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } @@ -796,7 +796,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) } mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - infra_clk_data); + infra_clk_data, &pdev->dev); mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), infra_clk_data); @@ -919,7 +919,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_PERI_NR); mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data); + clk_data, &pdev->dev); mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base, &mt2701_clk_lock, clk_data); diff --git a/drivers/clk/mediatek/clk-mt2712-mm.c b/drivers/clk/mediatek/clk-mt2712-mm.c index 7d44b09b8a0a..6c5f26a73476 100644 --- a/drivers/clk/mediatek/clk-mt2712-mm.c +++ b/drivers/clk/mediatek/clk-mt2712-mm.c @@ -136,7 +136,7 @@ static int clk_mt2712_mm_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index 56980dd6c2ea..24ec3384c429 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1351,7 +1351,7 @@ static int clk_mt2712_top_probe(struct platform_device *pdev) mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt2712_clk_lock, top_clk_data); mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), - top_clk_data); + top_clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, top_clk_data); @@ -1371,7 +1371,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); @@ -1393,7 +1393,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); diff --git a/drivers/clk/mediatek/clk-mt6765.c b/drivers/clk/mediatek/clk-mt6765.c index e9b9e6729733..7401693ef472 100644 --- a/drivers/clk/mediatek/clk-mt6765.c +++ b/drivers/clk/mediatek/clk-mt6765.c @@ -790,7 +790,7 @@ static int clk_mt6765_apmixed_probe(struct platform_device *pdev) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); mtk_clk_register_gates(node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); + ARRAY_SIZE(apmixed_clks), clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -829,7 +829,7 @@ static int clk_mt6765_top_probe(struct platform_device *pdev) mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, &mt6765_clk_lock, clk_data); mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); @@ -863,7 +863,7 @@ static int clk_mt6765_ifr_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK); mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt6779-mm.c b/drivers/clk/mediatek/clk-mt6779-mm.c index eda8cbee3d23..101808b3e38f 100644 --- a/drivers/clk/mediatek/clk-mt6779-mm.c +++ b/drivers/clk/mediatek/clk-mt6779-mm.c @@ -94,7 +94,7 @@ static int clk_mt6779_mm_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), - clk_data); + clk_data, &pdev->dev); return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 0d0a90ee5eb2..622a2fc6c167 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -1222,7 +1222,7 @@ static int clk_mt6779_apmixed_probe(struct platform_device *pdev) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); mtk_clk_register_gates(node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); + ARRAY_SIZE(apmixed_clks), clk_data, &pdev->dev); return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } @@ -1264,7 +1264,7 @@ static int clk_mt6779_infra_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); + clk_data, &pdev->dev); return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } diff --git a/drivers/clk/mediatek/clk-mt6795-infracfg.c b/drivers/clk/mediatek/clk-mt6795-infracfg.c index df7eed6e071e..4bbd2bfe2ec4 100644 --- a/drivers/clk/mediatek/clk-mt6795-infracfg.c +++ b/drivers/clk/mediatek/clk-mt6795-infracfg.c @@ -101,7 +101,8 @@ static int clk_mt6795_infracfg_probe(struct platform_device *pdev) if (ret) goto free_clk_data; - ret = mtk_clk_register_gates(node, infra_gates, ARRAY_SIZE(infra_gates), clk_data); + ret = mtk_clk_register_gates(node, infra_gates, ARRAY_SIZE(infra_gates), + clk_data, &pdev->dev); if (ret) goto free_clk_data; diff --git a/drivers/clk/mediatek/clk-mt6795-mm.c b/drivers/clk/mediatek/clk-mt6795-mm.c index fd73f202f292..10a623b83f68 100644 --- a/drivers/clk/mediatek/clk-mt6795-mm.c +++ b/drivers/clk/mediatek/clk-mt6795-mm.c @@ -87,7 +87,8 @@ static int clk_mt6795_mm_probe(struct platform_device *pdev) if (!clk_data) return -ENOMEM; - ret = mtk_clk_register_gates(node, mm_gates, ARRAY_SIZE(mm_gates), clk_data); + ret = mtk_clk_register_gates(node, mm_gates, ARRAY_SIZE(mm_gates), + clk_data, &pdev->dev); if (ret) goto free_clk_data; diff --git a/drivers/clk/mediatek/clk-mt6795-pericfg.c b/drivers/clk/mediatek/clk-mt6795-pericfg.c index cb28d35dad59..479a8abcb80b 100644 --- a/drivers/clk/mediatek/clk-mt6795-pericfg.c +++ b/drivers/clk/mediatek/clk-mt6795-pericfg.c @@ -109,7 +109,8 @@ static int clk_mt6795_pericfg_probe(struct platform_device *pdev) if (ret) goto free_clk_data; - ret = mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), clk_data); + ret = mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), + clk_data, &pdev->dev); if (ret) goto free_clk_data; diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c b/drivers/clk/mediatek/clk-mt6797-mm.c index 0846011fc894..dd96db5f2c0d 100644 --- a/drivers/clk/mediatek/clk-mt6797-mm.c +++ b/drivers/clk/mediatek/clk-mt6797-mm.c @@ -102,7 +102,7 @@ static int clk_mt6797_mm_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_MM_NR); mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c index b89f325a4b9b..250ac8bd6a3c 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -597,7 +597,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) } mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - infra_clk_data); + infra_clk_data, &pdev->dev); mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs), infra_clk_data); diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/clk-mt7622-aud.c index 9f2e5aa7b5d9..d0379d8704af 100644 --- a/drivers/clk/mediatek/clk-mt7622-aud.c +++ b/drivers/clk/mediatek/clk-mt7622-aud.c @@ -139,7 +139,7 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index 43de0477d5d9..9b4a26ca0f44 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -82,7 +82,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -104,7 +104,7 @@ static int clk_mt7622_sgmiisys_init(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index 67e96231dd25..8cf37f75ca77 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -93,7 +93,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -115,7 +115,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index 3b55f8641fae..eab450fc824c 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -653,7 +653,7 @@ static int mtk_topckgen_init(struct platform_device *pdev) base, &mt7622_clk_lock, clk_data); mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), - clk_data); + clk_data, &pdev->dev); clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk); clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk); @@ -671,7 +671,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); + clk_data, &pdev->dev); mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), clk_data); @@ -699,7 +699,8 @@ static int mtk_apmixedsys_init(struct platform_device *pdev) clk_data); mtk_clk_register_gates(node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); + ARRAY_SIZE(apmixed_clks), clk_data, + &pdev->dev); clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk); @@ -721,7 +722,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data); + clk_data, &pdev->dev); mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, &mt7622_clk_lock, clk_data); diff --git a/drivers/clk/mediatek/clk-mt7629-eth.c b/drivers/clk/mediatek/clk-mt7629-eth.c index 282dd6559465..39aa9eb5355e 100644 --- a/drivers/clk/mediatek/clk-mt7629-eth.c +++ b/drivers/clk/mediatek/clk-mt7629-eth.c @@ -92,7 +92,8 @@ static int clk_mt7629_ethsys_init(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); - mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, clk_data); + mtk_clk_register_gates(node, eth_clks, CLK_ETH_NR_CLK, + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -115,7 +116,7 @@ static int clk_mt7629_sgmiisys_init(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); mtk_clk_register_gates(node, sgmii_clks[id++], CLK_SGMII_NR_CLK, - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index 0c8b9e139789..44fbd88b4647 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -88,7 +88,7 @@ static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -110,7 +110,7 @@ static int clk_mt7629_pciesys_init(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index e4a08c811adc..2daceeab7fc4 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -606,7 +606,7 @@ static int mtk_infrasys_init(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); + clk_data, &pdev->dev); mtk_clk_register_cpumuxes(node, infra_muxes, ARRAY_SIZE(infra_muxes), clk_data); @@ -629,7 +629,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data); + clk_data, &pdev->dev); mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, &mt7629_clk_lock, clk_data); @@ -656,7 +656,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev) clk_data); mtk_clk_register_gates(node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data); + ARRAY_SIZE(apmixed_clks), clk_data, &pdev->dev); clk_prepare_enable(clk_data->hws[CLK_APMIXED_ARMPLL]->clk); clk_prepare_enable(clk_data->hws[CLK_APMIXED_MAIN_CORE_EN]->clk); diff --git a/drivers/clk/mediatek/clk-mt7986-eth.c b/drivers/clk/mediatek/clk-mt7986-eth.c index 7868c0728e96..765df117afa6 100644 --- a/drivers/clk/mediatek/clk-mt7986-eth.c +++ b/drivers/clk/mediatek/clk-mt7986-eth.c @@ -85,7 +85,7 @@ static void __init mtk_sgmiisys_0_init(struct device_node *node) clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks)); mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks), - clk_data); + clk_data, NULL); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -103,7 +103,7 @@ static void __init mtk_sgmiisys_1_init(struct device_node *node) clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks)); mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks), - clk_data); + clk_data, NULL); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); @@ -121,7 +121,7 @@ static void __init mtk_ethsys_init(struct device_node *node) clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks)); - mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data); + mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data, NULL); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); diff --git a/drivers/clk/mediatek/clk-mt7986-infracfg.c b/drivers/clk/mediatek/clk-mt7986-infracfg.c index 49666047bf0e..24947ccdb70a 100644 --- a/drivers/clk/mediatek/clk-mt7986-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7986-infracfg.c @@ -193,7 +193,7 @@ static int clk_mt7986_infracfg_probe(struct platform_device *pdev) mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node, &mt7986_clk_lock, clk_data); mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c index b68888a034c4..7193ab38090d 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -568,7 +568,7 @@ static void __init mtk_infrasys_init(struct device_node *node) clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); + clk_data, NULL); clk_prepare_enable(clk_data->hws[CLK_INFRA_M4U]->clk); @@ -596,7 +596,7 @@ static void __init mtk_pericfg_init(struct device_node *node) clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), - clk_data); + clk_data, NULL); mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, &mt8135_clk_lock, clk_data); diff --git a/drivers/clk/mediatek/clk-mt8167-aud.c b/drivers/clk/mediatek/clk-mt8167-aud.c index ce1ae8d243c3..aa229aaf467f 100644 --- a/drivers/clk/mediatek/clk-mt8167-aud.c +++ b/drivers/clk/mediatek/clk-mt8167-aud.c @@ -55,7 +55,7 @@ static void __init mtk_audsys_init(struct device_node *node) clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK); - mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data); + mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data, NULL); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt8167-img.c b/drivers/clk/mediatek/clk-mt8167-img.c index e359e563d2b7..1e592fa46c96 100644 --- a/drivers/clk/mediatek/clk-mt8167-img.c +++ b/drivers/clk/mediatek/clk-mt8167-img.c @@ -48,7 +48,7 @@ static void __init mtk_imgsys_init(struct device_node *node) clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK); - mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), clk_data); + mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), clk_data, NULL); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); diff --git a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c index 4fd82fe87d6e..b494d04bc851 100644 --- a/drivers/clk/mediatek/clk-mt8167-mfgcfg.c +++ b/drivers/clk/mediatek/clk-mt8167-mfgcfg.c @@ -46,7 +46,7 @@ static void __init mtk_mfgcfg_init(struct device_node *node) clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK); - mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks), clk_data); + mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks), clk_data, NULL); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); diff --git a/drivers/clk/mediatek/clk-mt8167-mm.c b/drivers/clk/mediatek/clk-mt8167-mm.c index 73910060577f..5669b5eecca9 100644 --- a/drivers/clk/mediatek/clk-mt8167-mm.c +++ b/drivers/clk/mediatek/clk-mt8167-mm.c @@ -111,7 +111,7 @@ static int clk_mt8167_mm_probe(struct platform_device *pdev) data = &mt8167_mmsys_driver_data; ret = mtk_clk_register_gates(node, data->gates_clk, data->gates_num, - clk_data); + clk_data, &pdev->dev); if (ret) return ret; diff --git a/drivers/clk/mediatek/clk-mt8167-vdec.c b/drivers/clk/mediatek/clk-mt8167-vdec.c index ee4fffb6859d..fcd6fdcd2536 100644 --- a/drivers/clk/mediatek/clk-mt8167-vdec.c +++ b/drivers/clk/mediatek/clk-mt8167-vdec.c @@ -61,7 +61,8 @@ static void __init mtk_vdecsys_init(struct device_node *node) clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK); - mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), clk_data); + mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), + clk_data, NULL); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-mt8167.c index f900ac4bf7b8..b150f893a4b8 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -937,7 +937,7 @@ static void __init mtk_topckgen_init(struct device_node *node) mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data); - mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data); + mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data, NULL); mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, diff --git a/drivers/clk/mediatek/clk-mt8173-mm.c b/drivers/clk/mediatek/clk-mt8173-mm.c index 8abf42c2030c..a99583c62c3b 100644 --- a/drivers/clk/mediatek/clk-mt8173-mm.c +++ b/drivers/clk/mediatek/clk-mt8173-mm.c @@ -125,7 +125,7 @@ static int clk_mt8173_mm_probe(struct platform_device *pdev) data = &mt8173_mmsys_driver_data; ret = mtk_clk_register_gates(node, data->gates_clk, data->gates_num, - clk_data); + clk_data, &pdev->dev); if (ret) return ret; diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index b57e33cda7a5..dfb819dd1b1b 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -889,7 +889,7 @@ static void __init mtk_infrasys_init(struct device_node *node) clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); + clk_data, NULL); mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), @@ -919,7 +919,7 @@ static void __init mtk_pericfg_init(struct device_node *node) clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), - clk_data); + clk_data, NULL); mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, &mt8173_clk_lock, clk_data); @@ -1063,7 +1063,7 @@ static void __init mtk_imgsys_init(struct device_node *node) clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK); mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), - clk_data); + clk_data, NULL); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); @@ -1081,7 +1081,7 @@ static void __init mtk_vdecsys_init(struct device_node *node) clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK); mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), - clk_data); + clk_data, NULL); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -1098,7 +1098,7 @@ static void __init mtk_vencsys_init(struct device_node *node) clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK); mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks), - clk_data); + clk_data, NULL); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -1115,7 +1115,7 @@ static void __init mtk_vencltsys_init(struct device_node *node) clk_data = mtk_alloc_clk_data(CLK_VENCLT_NR_CLK); mtk_clk_register_gates(node, venclt_clks, ARRAY_SIZE(venclt_clks), - clk_data); + clk_data, NULL); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt8183-audio.c b/drivers/clk/mediatek/clk-mt8183-audio.c index b2d7746eddbe..f4c6448b6f74 100644 --- a/drivers/clk/mediatek/clk-mt8183-audio.c +++ b/drivers/clk/mediatek/clk-mt8183-audio.c @@ -76,7 +76,7 @@ static int clk_mt8183_audio_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt8183-mm.c b/drivers/clk/mediatek/clk-mt8183-mm.c index 11ecc6fb0065..f93043da26c0 100644 --- a/drivers/clk/mediatek/clk-mt8183-mm.c +++ b/drivers/clk/mediatek/clk-mt8183-mm.c @@ -91,7 +91,7 @@ static int clk_mt8183_mm_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), - clk_data); + clk_data, &pdev->dev); return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 23afc9584638..f99c092476c2 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1101,7 +1101,7 @@ static int clk_mt8183_apmixed_probe(struct platform_device *pdev) mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), - clk_data); + clk_data, &pdev->dev); return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } @@ -1176,7 +1176,7 @@ static int clk_mt8183_top_probe(struct platform_device *pdev) base, &mt8183_clk_lock, top_clk_data); mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), - top_clk_data); + top_clk_data, &pdev->dev); ret = clk_mt8183_reg_mfg_mux_notifier(&pdev->dev, top_clk_data->hws[CLK_TOP_MUX_MFG]->clk); @@ -1196,7 +1196,7 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data); + clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) { @@ -1219,7 +1219,7 @@ static int clk_mt8183_peri_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data); + clk_data, &pdev->dev); return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } diff --git a/drivers/clk/mediatek/clk-mt8186-mm.c b/drivers/clk/mediatek/clk-mt8186-mm.c index 1d33be407947..35038928eacf 100644 --- a/drivers/clk/mediatek/clk-mt8186-mm.c +++ b/drivers/clk/mediatek/clk-mt8186-mm.c @@ -69,7 +69,8 @@ static int clk_mt8186_mm_probe(struct platform_device *pdev) if (!clk_data) return -ENOMEM; - r = mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), clk_data); + r = mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), + clk_data, &pdev->dev); if (r) goto free_mm_data; diff --git a/drivers/clk/mediatek/clk-mt8192-aud.c b/drivers/clk/mediatek/clk-mt8192-aud.c index 8c989bffd8c7..3acadca2452a 100644 --- a/drivers/clk/mediatek/clk-mt8192-aud.c +++ b/drivers/clk/mediatek/clk-mt8192-aud.c @@ -87,7 +87,8 @@ static int clk_mt8192_aud_probe(struct platform_device *pdev) if (!clk_data) return -ENOMEM; - r = mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data); + r = mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), + clk_data, &pdev->dev); if (r) return r; diff --git a/drivers/clk/mediatek/clk-mt8192-mm.c b/drivers/clk/mediatek/clk-mt8192-mm.c index 1be3ff4d407d..226f6976c277 100644 --- a/drivers/clk/mediatek/clk-mt8192-mm.c +++ b/drivers/clk/mediatek/clk-mt8192-mm.c @@ -91,7 +91,8 @@ static int clk_mt8192_mm_probe(struct platform_device *pdev) if (!clk_data) return -ENOMEM; - r = mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), clk_data); + r = mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks), + clk_data, &pdev->dev); if (r) return r; diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index 991d78a71644..e1b625b86911 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1127,7 +1127,7 @@ static int clk_mt8192_top_probe(struct platform_device *pdev) if (r) goto unregister_top_composites; - r = mtk_clk_register_gates_with_dev(node, top_clks, ARRAY_SIZE(top_clks), + r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data, &pdev->dev); if (r) goto unregister_adj_divs_composites; @@ -1168,7 +1168,7 @@ static int clk_mt8192_infra_probe(struct platform_device *pdev) if (!clk_data) return -ENOMEM; - r = mtk_clk_register_gates_with_dev(node, infra_clks, ARRAY_SIZE(infra_clks), + r = mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data, &pdev->dev); if (r) goto free_clk_data; @@ -1200,7 +1200,7 @@ static int clk_mt8192_peri_probe(struct platform_device *pdev) if (!clk_data) return -ENOMEM; - r = mtk_clk_register_gates_with_dev(node, peri_clks, ARRAY_SIZE(peri_clks), + r = mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), clk_data, &pdev->dev); if (r) goto free_clk_data; @@ -1229,9 +1229,9 @@ static int clk_mt8192_apmixed_probe(struct platform_device *pdev) return -ENOMEM; mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); - r = mtk_clk_register_gates_with_dev(node, apmixed_clks, - ARRAY_SIZE(apmixed_clks), clk_data, - &pdev->dev); + r = mtk_clk_register_gates(node, apmixed_clks, + ARRAY_SIZE(apmixed_clks), clk_data, + &pdev->dev); if (r) goto free_clk_data; diff --git a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c index 0dfed6ec4d15..f967e2592dea 100644 --- a/drivers/clk/mediatek/clk-mt8195-apmixedsys.c +++ b/drivers/clk/mediatek/clk-mt8195-apmixedsys.c @@ -124,7 +124,8 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev) if (r) goto free_apmixed_data; - r = mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data); + r = mtk_clk_register_gates(node, apmixed_clks, ARRAY_SIZE(apmixed_clks), + clk_data, &pdev->dev); if (r) goto unregister_plls; diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c index 93e96419da66..ed604d39f9d5 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -1286,7 +1286,8 @@ static int clk_mt8195_topck_probe(struct platform_device *pdev) if (r) goto unregister_muxes; - r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data); + r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), + top_clk_data, &pdev->dev); if (r) goto unregister_composite_divs; diff --git a/drivers/clk/mediatek/clk-mt8195-vdo0.c b/drivers/clk/mediatek/clk-mt8195-vdo0.c index 07b46bfd5040..9ebad476e943 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo0.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo0.c @@ -104,7 +104,8 @@ static int clk_mt8195_vdo0_probe(struct platform_device *pdev) if (!clk_data) return -ENOMEM; - r = mtk_clk_register_gates(node, vdo0_clks, ARRAY_SIZE(vdo0_clks), clk_data); + r = mtk_clk_register_gates(node, vdo0_clks, ARRAY_SIZE(vdo0_clks), + clk_data, &pdev->dev); if (r) goto free_vdo0_data; diff --git a/drivers/clk/mediatek/clk-mt8195-vdo1.c b/drivers/clk/mediatek/clk-mt8195-vdo1.c index 835335b9d87b..a7a588f086c5 100644 --- a/drivers/clk/mediatek/clk-mt8195-vdo1.c +++ b/drivers/clk/mediatek/clk-mt8195-vdo1.c @@ -131,7 +131,8 @@ static int clk_mt8195_vdo1_probe(struct platform_device *pdev) if (!clk_data) return -ENOMEM; - r = mtk_clk_register_gates(node, vdo1_clks, ARRAY_SIZE(vdo1_clks), clk_data); + r = mtk_clk_register_gates(node, vdo1_clks, ARRAY_SIZE(vdo1_clks), + clk_data, &pdev->dev); if (r) goto free_vdo1_data; diff --git a/drivers/clk/mediatek/clk-mt8365-mm.c b/drivers/clk/mediatek/clk-mt8365-mm.c index 5c8bf18ab1f1..bc6bf0913452 100644 --- a/drivers/clk/mediatek/clk-mt8365-mm.c +++ b/drivers/clk/mediatek/clk-mt8365-mm.c @@ -81,9 +81,8 @@ static int clk_mt8365_mm_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK); - ret = mtk_clk_register_gates_with_dev(node, mm_clks, - ARRAY_SIZE(mm_clks), clk_data, - dev); + ret = mtk_clk_register_gates(node, mm_clks, + ARRAY_SIZE(mm_clks), clk_data, dev); if (ret) goto err_free_clk_data; diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index adfecb618f10..5a43e5aad16e 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -1020,7 +1020,7 @@ static int clk_mt8365_infra_probe(struct platform_device *pdev) return -ENOMEM; ret = mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks), - clk_data); + clk_data, &pdev->dev); if (ret) goto free_clk_data; diff --git a/drivers/clk/mediatek/clk-mt8516-aud.c b/drivers/clk/mediatek/clk-mt8516-aud.c index 90f48068a8de..e3a7b3c939f3 100644 --- a/drivers/clk/mediatek/clk-mt8516-aud.c +++ b/drivers/clk/mediatek/clk-mt8516-aud.c @@ -54,7 +54,7 @@ static void __init mtk_audsys_init(struct device_node *node) clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK); - mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data); + mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), clk_data, NULL); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index b96db88893e2..a648ee463697 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -691,7 +691,7 @@ static void __init mtk_topckgen_init(struct device_node *node) mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data); - mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data); + mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data, NULL); mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 3c1ac8d3010f..e04eef7e2b6f 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -459,8 +459,8 @@ int mtk_clk_simple_probe(struct platform_device *pdev) if (!clk_data) return -ENOMEM; - r = mtk_clk_register_gates_with_dev(node, mcd->clks, mcd->num_clks, - clk_data, &pdev->dev); + r = mtk_clk_register_gates(node, mcd->clks, mcd->num_clks, + clk_data, &pdev->dev); if (r) goto free_data; From patchwork Thu Dec 22 11:48:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 636131 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95A03C41535 for ; Thu, 22 Dec 2022 11:55:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235711AbiLVLz3 (ORCPT ); Thu, 22 Dec 2022 06:55:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235212AbiLVLx4 (ORCPT ); Thu, 22 Dec 2022 06:53:56 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92B072B62E; Thu, 22 Dec 2022 03:49:25 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 4BFC26602CD9; Thu, 22 Dec 2022 11:49:22 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671709763; bh=BJpeugsotBsLMOM6SD/PFiXg/IwoTPpVagtQf6A2tuU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Vpn7GmbwbgjZP93CspTPSA8WNma9TZ0KMGltE8hQl7cVm1/UnywjIPAfL+bcXkQkk xhkWv/Y/GPHaWJePXbtdvcWFShDxza+6dcDgvZOo4GizK/9otqCp8qrhNg02KT6m8z gSI3pIJTyowHi/kN5yxfLgpOVTRI9EMtBVOYqVs2HgOAigarRSFtiALE4AwnlxFleT MkB6aZ5gmuuOvHYJ8d4WfdE19bbhZyTHuGCG+kO4IJ7lC7qKdvgB0auSL4b/oZQrlC 6tYBckNEPnkV9JCcaz6jkiqJ6lQfQh3lPHCFU+CNNNJAhkToOHBtJJlQpuwrtovnzy i7zpg7zsKVVXw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v1 05/25] clk: mediatek: clk-mtk: Propagate struct device for composites Date: Thu, 22 Dec 2022 12:48:37 +0100 Message-Id: <20221222114857.120060-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> References: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Like done for cpumux clocks, propagate struct device for composite clocks registered through clk-mtk helpers to be able to get runtime pm support for MTK clocks. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt2701.c | 4 ++-- drivers/clk/mediatek/clk-mt2712.c | 4 ++-- drivers/clk/mediatek/clk-mt6779.c | 4 ++-- drivers/clk/mediatek/clk-mt6795-pericfg.c | 2 +- drivers/clk/mediatek/clk-mt6795-topckgen.c | 2 +- drivers/clk/mediatek/clk-mt6797.c | 2 +- drivers/clk/mediatek/clk-mt7622.c | 5 +++-- drivers/clk/mediatek/clk-mt7629.c | 4 ++-- drivers/clk/mediatek/clk-mt8135.c | 4 ++-- drivers/clk/mediatek/clk-mt8167.c | 4 ++-- drivers/clk/mediatek/clk-mt8173.c | 4 ++-- drivers/clk/mediatek/clk-mt8183.c | 6 +++--- drivers/clk/mediatek/clk-mt8186-mcu.c | 2 +- drivers/clk/mediatek/clk-mt8186-topckgen.c | 4 ++-- drivers/clk/mediatek/clk-mt8192.c | 4 ++-- drivers/clk/mediatek/clk-mt8195-topckgen.c | 2 +- drivers/clk/mediatek/clk-mt8365.c | 5 +++-- drivers/clk/mediatek/clk-mt8516.c | 4 ++-- drivers/clk/mediatek/clk-mtk.c | 9 +++++---- drivers/clk/mediatek/clk-mtk.h | 3 ++- 20 files changed, 41 insertions(+), 37 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c index dcae25778817..bd62acb5d697 100644 --- a/drivers/clk/mediatek/clk-mt2701.c +++ b/drivers/clk/mediatek/clk-mt2701.c @@ -684,7 +684,7 @@ static int mtk_topckgen_init(struct platform_device *pdev) clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), - base, &mt2701_clk_lock, clk_data); + base, &mt2701_clk_lock, clk_data, &pdev->dev); mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt2701_clk_lock, clk_data); @@ -922,7 +922,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) clk_data, &pdev->dev); mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base, - &mt2701_clk_lock, clk_data); + &mt2701_clk_lock, clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index 24ec3384c429..5cadcf6ca9b7 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1347,7 +1347,7 @@ static int clk_mt2712_top_probe(struct platform_device *pdev) top_clk_data); mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt2712_clk_lock, top_clk_data); + &mt2712_clk_lock, top_clk_data, &pdev->dev); mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt2712_clk_lock, top_clk_data); mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), @@ -1422,7 +1422,7 @@ static int clk_mt2712_mcu_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, - &mt2712_clk_lock, clk_data); + &mt2712_clk_lock, clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 622a2fc6c167..825f2f57e868 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -1248,10 +1248,10 @@ static int clk_mt6779_top_probe(struct platform_device *pdev) node, &mt6779_clk_lock, clk_data); mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes), - base, &mt6779_clk_lock, clk_data); + base, &mt6779_clk_lock, clk_data, &pdev->dev); mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), - base, &mt6779_clk_lock, clk_data); + base, &mt6779_clk_lock, clk_data, &pdev->dev); return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } diff --git a/drivers/clk/mediatek/clk-mt6795-pericfg.c b/drivers/clk/mediatek/clk-mt6795-pericfg.c index 479a8abcb80b..1fc80bc1592b 100644 --- a/drivers/clk/mediatek/clk-mt6795-pericfg.c +++ b/drivers/clk/mediatek/clk-mt6795-pericfg.c @@ -115,7 +115,7 @@ static int clk_mt6795_pericfg_probe(struct platform_device *pdev) goto free_clk_data; ret = mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, - &mt6795_peri_clk_lock, clk_data); + &mt6795_peri_clk_lock, clk_data, &pdev->dev); if (ret) goto unregister_gates; diff --git a/drivers/clk/mediatek/clk-mt6795-topckgen.c b/drivers/clk/mediatek/clk-mt6795-topckgen.c index 8b8307635a35..bb232e1726f1 100644 --- a/drivers/clk/mediatek/clk-mt6795-topckgen.c +++ b/drivers/clk/mediatek/clk-mt6795-topckgen.c @@ -558,7 +558,7 @@ static int clk_mt6795_topckgen_probe(struct platform_device *pdev) goto unregister_factors; ret = mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), base, - &mt6795_top_clk_lock, clk_data); + &mt6795_top_clk_lock, clk_data, &pdev->dev); if (ret) goto unregister_muxes; diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c index 250ac8bd6a3c..581bc7d9f66d 100644 --- a/drivers/clk/mediatek/clk-mt6797.c +++ b/drivers/clk/mediatek/clk-mt6797.c @@ -397,7 +397,7 @@ static int mtk_topckgen_init(struct platform_device *pdev) clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt6797_clk_lock, clk_data); + &mt6797_clk_lock, clk_data, &pdev->dev); return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index adf3b4535170..fb4e2552ba76 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -647,7 +647,8 @@ static int mtk_topckgen_init(struct platform_device *pdev) clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), - base, &mt7622_clk_lock, clk_data); + base, &mt7622_clk_lock, clk_data, + &pdev->dev); mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt7622_clk_lock, clk_data); @@ -725,7 +726,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) clk_data, &pdev->dev); mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, - &mt7622_clk_lock, clk_data); + &mt7622_clk_lock, clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 48bc4a6705fb..890f1944565e 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -589,7 +589,7 @@ static int mtk_topckgen_init(struct platform_device *pdev) clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), - base, &mt7629_clk_lock, clk_data); + base, &mt7629_clk_lock, clk_data, &pdev->dev); clk_prepare_enable(clk_data->hws[CLK_TOP_AXI_SEL]->clk); clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk); @@ -632,7 +632,7 @@ static int mtk_pericfg_init(struct platform_device *pdev) clk_data, &pdev->dev); mtk_clk_register_composites(peri_muxes, ARRAY_SIZE(peri_muxes), base, - &mt7629_clk_lock, clk_data); + &mt7629_clk_lock, clk_data, &pdev->dev); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c index 7193ab38090d..253fe271ee97 100644 --- a/drivers/clk/mediatek/clk-mt8135.c +++ b/drivers/clk/mediatek/clk-mt8135.c @@ -549,7 +549,7 @@ static void __init mtk_topckgen_init(struct device_node *node) mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data); mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8135_clk_lock, clk_data); + &mt8135_clk_lock, clk_data, NULL); clk_prepare_enable(clk_data->hws[CLK_TOP_CCI_SEL]->clk); @@ -598,7 +598,7 @@ static void __init mtk_pericfg_init(struct device_node *node) mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), clk_data, NULL); mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, - &mt8135_clk_lock, clk_data); + &mt8135_clk_lock, clk_data, NULL); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt8167.c b/drivers/clk/mediatek/clk-mt8167.c index b150f893a4b8..cc064e98643a 100644 --- a/drivers/clk/mediatek/clk-mt8167.c +++ b/drivers/clk/mediatek/clk-mt8167.c @@ -941,7 +941,7 @@ static void __init mtk_topckgen_init(struct device_node *node) mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8167_clk_lock, clk_data); + &mt8167_clk_lock, clk_data, NULL); mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt8167_clk_lock, clk_data); @@ -967,7 +967,7 @@ static void __init mtk_infracfg_init(struct device_node *node) clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK); mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base, - &mt8167_clk_lock, clk_data); + &mt8167_clk_lock, clk_data, NULL); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 125b01b9e2ab..617f68274004 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -870,7 +870,7 @@ static void __init mtk_topckgen_init(struct device_node *node) mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data); mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8173_clk_lock, clk_data); + &mt8173_clk_lock, clk_data, NULL); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -921,7 +921,7 @@ static void __init mtk_pericfg_init(struct device_node *node) mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), clk_data, NULL); mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, - &mt8173_clk_lock, clk_data); + &mt8173_clk_lock, clk_data, NULL); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index f99c092476c2..194906ca4b5b 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1170,10 +1170,10 @@ static int clk_mt8183_top_probe(struct platform_device *pdev) node, &mt8183_clk_lock, top_clk_data); mtk_clk_register_composites(top_aud_muxes, ARRAY_SIZE(top_aud_muxes), - base, &mt8183_clk_lock, top_clk_data); + base, &mt8183_clk_lock, top_clk_data, &pdev->dev); mtk_clk_register_composites(top_aud_divs, ARRAY_SIZE(top_aud_divs), - base, &mt8183_clk_lock, top_clk_data); + base, &mt8183_clk_lock, top_clk_data, &pdev->dev); mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data, &pdev->dev); @@ -1237,7 +1237,7 @@ static int clk_mt8183_mcu_probe(struct platform_device *pdev) clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK); mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, - &mt8183_clk_lock, clk_data); + &mt8183_clk_lock, clk_data, &pdev->dev); return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } diff --git a/drivers/clk/mediatek/clk-mt8186-mcu.c b/drivers/clk/mediatek/clk-mt8186-mcu.c index dfc305c1fc5d..c4a5557cb830 100644 --- a/drivers/clk/mediatek/clk-mt8186-mcu.c +++ b/drivers/clk/mediatek/clk-mt8186-mcu.c @@ -66,7 +66,7 @@ static int clk_mt8186_mcu_probe(struct platform_device *pdev) } r = mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base, - NULL, clk_data); + NULL, clk_data, &pdev->dev); if (r) goto free_mcu_data; diff --git a/drivers/clk/mediatek/clk-mt8186-topckgen.c b/drivers/clk/mediatek/clk-mt8186-topckgen.c index c2beda7ef976..b79954a42481 100644 --- a/drivers/clk/mediatek/clk-mt8186-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8186-topckgen.c @@ -743,12 +743,12 @@ static int clk_mt8186_topck_probe(struct platform_device *pdev) goto unregister_factors; r = mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8186_clk_lock, clk_data); + &mt8186_clk_lock, clk_data, &pdev->dev); if (r) goto unregister_muxes; r = mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, - &mt8186_clk_lock, clk_data); + &mt8186_clk_lock, clk_data, &pdev->dev); if (r) goto unregister_composite_muxes; diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index e1b625b86911..27ad629062c4 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1118,12 +1118,12 @@ static int clk_mt8192_top_probe(struct platform_device *pdev) goto unregister_factors; r = mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8192_clk_lock, top_clk_data); + &mt8192_clk_lock, top_clk_data, &pdev->dev); if (r) goto unregister_muxes; r = mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, - &mt8192_clk_lock, top_clk_data); + &mt8192_clk_lock, top_clk_data, &pdev->dev); if (r) goto unregister_top_composites; diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c index ed604d39f9d5..437c12d19b03 100644 --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c @@ -1282,7 +1282,7 @@ static int clk_mt8195_topck_probe(struct platform_device *pdev) goto unregister_muxes; r = mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, - &mt8195_clk_lock, top_clk_data); + &mt8195_clk_lock, top_clk_data, &pdev->dev); if (r) goto unregister_muxes; diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index 5a43e5aad16e..00c15f89a5f6 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -954,7 +954,7 @@ static int clk_mt8365_top_probe(struct platform_device *pdev) ret = mtk_clk_register_composites(top_misc_mux_gates, ARRAY_SIZE(top_misc_mux_gates), base, - &mt8365_clk_lock, clk_data); + &mt8365_clk_lock, clk_data, &pdev->dev); if (ret) goto unregister_muxes; @@ -1081,7 +1081,8 @@ static int clk_mt8365_mcu_probe(struct platform_device *pdev) return -ENOMEM; ret = mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), - base, &mt8365_clk_lock, clk_data); + base, &mt8365_clk_lock, clk_data, + &pdev->dev); if (ret) goto free_clk_data; diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c index a648ee463697..b50b2d1387b6 100644 --- a/drivers/clk/mediatek/clk-mt8516.c +++ b/drivers/clk/mediatek/clk-mt8516.c @@ -695,7 +695,7 @@ static void __init mtk_topckgen_init(struct device_node *node) mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8516_clk_lock, clk_data); + &mt8516_clk_lock, clk_data, NULL); mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt8516_clk_lock, clk_data); @@ -721,7 +721,7 @@ static void __init mtk_infracfg_init(struct device_node *node) clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK); mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base, - &mt8516_clk_lock, clk_data); + &mt8516_clk_lock, clk_data, NULL); r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index e04eef7e2b6f..a1ab34305b95 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -198,7 +198,7 @@ void mtk_clk_unregister_factors(const struct mtk_fixed_factor *clks, int num, EXPORT_SYMBOL_GPL(mtk_clk_unregister_factors); static struct clk_hw *mtk_clk_register_composite(const struct mtk_composite *mc, - void __iomem *base, spinlock_t *lock) + void __iomem *base, spinlock_t *lock, struct device *dev) { struct clk_hw *hw; struct clk_mux *mux = NULL; @@ -264,7 +264,7 @@ static struct clk_hw *mtk_clk_register_composite(const struct mtk_composite *mc, div_ops = &clk_divider_ops; } - hw = clk_hw_register_composite(NULL, mc->name, parent_names, num_parents, + hw = clk_hw_register_composite(dev, mc->name, parent_names, num_parents, mux_hw, mux_ops, div_hw, div_ops, gate_hw, gate_ops, @@ -310,7 +310,8 @@ static void mtk_clk_unregister_composite(struct clk_hw *hw) int mtk_clk_register_composites(const struct mtk_composite *mcs, int num, void __iomem *base, spinlock_t *lock, - struct clk_hw_onecell_data *clk_data) + struct clk_hw_onecell_data *clk_data, + struct device *dev) { struct clk_hw *hw; int i; @@ -327,7 +328,7 @@ int mtk_clk_register_composites(const struct mtk_composite *mcs, int num, continue; } - hw = mtk_clk_register_composite(mc, base, lock); + hw = mtk_clk_register_composite(mc, base, lock, dev); if (IS_ERR(hw)) { pr_err("Failed to register clk %s: %pe\n", mc->name, diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index f2db6b57d5b5..15122504c02d 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -156,7 +156,8 @@ struct mtk_composite { int mtk_clk_register_composites(const struct mtk_composite *mcs, int num, void __iomem *base, spinlock_t *lock, - struct clk_hw_onecell_data *clk_data); + struct clk_hw_onecell_data *clk_data, + struct device *dev); void mtk_clk_unregister_composites(const struct mtk_composite *mcs, int num, struct clk_hw_onecell_data *clk_data); From patchwork Thu Dec 22 11:48:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 636130 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4CA35C4167B for ; Thu, 22 Dec 2022 11:55:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235490AbiLVLzk (ORCPT ); Thu, 22 Dec 2022 06:55:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53092 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235515AbiLVLyH (ORCPT ); Thu, 22 Dec 2022 06:54:07 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F3D72CC83; Thu, 22 Dec 2022 03:49:28 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9AFD16602C6F; Thu, 22 Dec 2022 11:49:25 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671709767; bh=a4f9kigYCsZYqWWZJsSkeZo+Ou8NCxgHVWscF4M2s84=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SHeL4PnBwaV3Ch3A+mvCCMyj9Rf8F0hAYX7VcZyNBFW9gbs19AlFzV0JCeknJKiIO ZfAelaSBcM5KxUBNXvPjzs+E/WsABTAz7eBuK2wVDVfgmHSSAbqXoXvsrBN3D5XXH8 6ph+w49t4zutr8onZDlmOneUmg3DF4rzm5PURj8jPjWyoQEeyYl7AVtdEEOrm/hSST E+0tXRVXMhioBYpVYdhbOnyawLc8gua/yixawrxuhm+zM/M6/GpvUyeXP89nxuZ0yp 8aciiE2LIqCWSzmw4BhKGwYFutxJkmQvC4bIWjzdLXi8+tplM81jZA9jZB6f1kQeFq 7UQvZIiKpB5Tw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v1 07/25] clk: mediatek: clk-mtk: Add dummy clock ops Date: Thu, 22 Dec 2022 12:48:39 +0100 Message-Id: <20221222114857.120060-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> References: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In order to migrate some (few) old clock drivers to the common mtk_clk_simple_probe() function, add dummy clock ops to be able to insert a dummy clock with ID 0 at the beginning of the list. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mtk.c | 15 +++++++++++++++ drivers/clk/mediatek/clk-mtk.h | 17 +++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index a1ab34305b95..d05364e17e95 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -18,6 +18,21 @@ #include "clk-mtk.h" #include "clk-gate.h" +const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 }; + +static int mtk_clk_dummy_enable(struct clk_hw *hw) +{ + return 0; +} + +static void mtk_clk_dummy_disable(struct clk_hw *hw) { } + +const struct clk_ops mtk_clk_dummy_ops = { + .enable = mtk_clk_dummy_enable, + .disable = mtk_clk_dummy_disable, +}; +EXPORT_SYMBOL_GPL(mtk_clk_dummy_ops); + static void mtk_init_clk_data(struct clk_hw_onecell_data *clk_data, unsigned int clk_num) { diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index 15122504c02d..b72e88c0179f 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -22,6 +22,23 @@ struct platform_device; +/* + * We need the clock IDs to start from zero but to maintain devicetree + * backwards compatibility we can't change bindings to start from zero. + * Only a few platforms are affected, so we solve issues given by the + * commonized MTK clocks probe function(s) by adding a dummy clock at + * the beginning where needed. + */ +extern const struct clk_ops mtk_clk_dummy_ops; +extern const struct mtk_gate_regs cg_regs_dummy; + +#define GATE_DUMMY(_id, _name) { \ + .id = _id, \ + .name = _name, \ + .regs = &cg_regs_dummy, \ + .ops = &mtk_clk_dummy_ops, \ + } + struct mtk_fixed_clk { int id; const char *name; From patchwork Thu Dec 22 11:48:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 636129 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2B30C4332F for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671709770; bh=Q79Cdsx41x4f+YPxKYF83Ryep4djnWlEAq5arTZPmB4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gVi1iw7bersSZD4Qkou3Brdk+OZOQUb0refYKwGDTpxcrhobQ9LwNs1WR8ZCi7wyr eGLsosrmZFdiTsYNiT0vryL4SuSBm2ZbIJnaL7gvXLt0xUJzl9O5buvZmuY40k4yXD NQ5rcVjxm/1Zf1oOQYWAKt7xhhE0ZTqDB8ygPN4THWD9JoVCVWWANOEA360/g7Tf9r h6AHOFQK4jGvw0blMP/e70Sb8yReUtE6+EyMeB+F5gDAZIntF4INF21GgDRYmgFy5M fd1ysbws86vEn4YxLMyVkCaQqT9ohPl63KoUPvqOt7kHAYqKoiD4c9D742FHSKUZNj e8qb2+yypeyGA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v1 09/25] clk: mediatek: mt8173: Migrate to platform driver and common probe Date: Thu, 22 Dec 2022 12:48:41 +0100 Message-Id: <20221222114857.120060-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> References: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This driver is using CLK_OF_DECLARE() for all clocks: while this definitely works, it's not preferred as this makes it impossible to compile non boot critical clock drivers as modules and to take advantage of clock controller Runtime PM. As a preparation for a larger cleanup, migrate all of the clock controller drivers for MT8173 to platform_driver and use the common mtk_clk_simple_probe() where possible. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8173.c | 478 +++++++++++++++++------------- 1 file changed, 273 insertions(+), 205 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c index 617f68274004..70cdc0719658 100644 --- a/drivers/clk/mediatek/clk-mt8173.c +++ b/drivers/clk/mediatek/clk-mt8173.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include "clk-cpumux.h" #include "clk-gate.h" @@ -15,6 +17,9 @@ #include +#define REGOFF_REF2USB 0x8 +#define REGOFF_HDMI_REF 0x40 + /* * For some clocks, we don't care what their actual rates are. And these * clocks may change their rate on different products or different scenarios. @@ -24,7 +29,7 @@ static DEFINE_SPINLOCK(mt8173_clk_lock); -static const struct mtk_fixed_clk fixed_clks[] __initconst = { +static const struct mtk_fixed_clk fixed_clks[] = { FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", DUMMY_RATE), FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ), FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", DUMMY_RATE), @@ -33,7 +38,7 @@ static const struct mtk_fixed_clk fixed_clks[] __initconst = { FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", DUMMY_RATE), }; -static const struct mtk_fixed_factor top_divs[] __initconst = { +static const struct mtk_fixed_factor top_divs[] = { FACTOR(CLK_TOP_ARMCA7PLL_754M, "armca7pll_754m", "armca7pll", 1, 2), FACTOR(CLK_TOP_ARMCA7PLL_502M, "armca7pll_502m", "armca7pll", 1, 3), @@ -129,7 +134,7 @@ static const struct mtk_fixed_factor top_divs[] __initconst = { FACTOR(CLK_TOP_VENCPLL_D4, "vencpll_d4", "vencpll", 1, 4), }; -static const char * const axi_parents[] __initconst = { +static const char * const axi_parents[] = { "clk26m", "syspll1_d2", "syspll_d5", @@ -140,17 +145,17 @@ static const char * const axi_parents[] __initconst = { "dmpll_d4" }; -static const char * const mem_parents[] __initconst = { +static const char * const mem_parents[] = { "clk26m", "dmpll_ck" }; -static const char * const ddrphycfg_parents[] __initconst = { +static const char * const ddrphycfg_parents[] = { "clk26m", "syspll1_d8" }; -static const char * const mm_parents[] __initconst = { +static const char * const mm_parents[] = { "clk26m", "vencpll_d2", "main_h364m", @@ -162,14 +167,14 @@ static const char * const mm_parents[] __initconst = { "dmpll_d2" }; -static const char * const pwm_parents[] __initconst = { +static const char * const pwm_parents[] = { "clk26m", "univpll2_d4", "univpll3_d2", "univpll1_d4" }; -static const char * const vdec_parents[] __initconst = { +static const char * const vdec_parents[] = { "clk26m", "vcodecpll_ck", "tvdpll_445p5m", @@ -182,7 +187,7 @@ static const char * const vdec_parents[] __initconst = { "dmpll_d4" }; -static const char * const venc_parents[] __initconst = { +static const char * const venc_parents[] = { "clk26m", "vcodecpll_ck", "tvdpll_445p5m", @@ -195,7 +200,7 @@ static const char * const venc_parents[] __initconst = { "dmpll_d4" }; -static const char * const mfg_parents[] __initconst = { +static const char * const mfg_parents[] = { "clk26m", "mmpll_ck", "dmpll_ck", @@ -214,7 +219,7 @@ static const char * const mfg_parents[] __initconst = { "univpll2_d2" }; -static const char * const camtg_parents[] __initconst = { +static const char * const camtg_parents[] = { "clk26m", "univpll_d26", "univpll2_d2", @@ -223,12 +228,12 @@ static const char * const camtg_parents[] __initconst = { "univpll1_d4" }; -static const char * const uart_parents[] __initconst = { +static const char * const uart_parents[] = { "clk26m", "univpll2_d8" }; -static const char * const spi_parents[] __initconst = { +static const char * const spi_parents[] = { "clk26m", "syspll3_d2", "syspll1_d4", @@ -238,20 +243,20 @@ static const char * const spi_parents[] __initconst = { "univpll1_d8" }; -static const char * const usb20_parents[] __initconst = { +static const char * const usb20_parents[] = { "clk26m", "univpll1_d8", "univpll3_d4" }; -static const char * const usb30_parents[] __initconst = { +static const char * const usb30_parents[] = { "clk26m", "univpll3_d2", "usb_syspll_125m", "univpll2_d4" }; -static const char * const msdc50_0_h_parents[] __initconst = { +static const char * const msdc50_0_h_parents[] = { "clk26m", "syspll1_d2", "syspll2_d2", @@ -260,7 +265,7 @@ static const char * const msdc50_0_h_parents[] __initconst = { "univpll1_d4" }; -static const char * const msdc50_0_parents[] __initconst = { +static const char * const msdc50_0_parents[] = { "clk26m", "msdcpll_ck", "msdcpll_d2", @@ -278,7 +283,7 @@ static const char * const msdc50_0_parents[] __initconst = { "msdcpll2_d4" }; -static const char * const msdc30_1_parents[] __initconst = { +static const char * const msdc30_1_parents[] = { "clk26m", "univpll2_d2", "msdcpll_d4", @@ -289,7 +294,7 @@ static const char * const msdc30_1_parents[] __initconst = { "vencpll_d4" }; -static const char * const msdc30_2_parents[] __initconst = { +static const char * const msdc30_2_parents[] = { "clk26m", "univpll2_d2", "msdcpll_d4", @@ -300,7 +305,7 @@ static const char * const msdc30_2_parents[] __initconst = { "vencpll_d2" }; -static const char * const msdc30_3_parents[] __initconst = { +static const char * const msdc30_3_parents[] = { "clk26m", "msdcpll2_ck", "msdcpll2_d2", @@ -317,14 +322,14 @@ static const char * const msdc30_3_parents[] __initconst = { "msdcpll_d4" }; -static const char * const audio_parents[] __initconst = { +static const char * const audio_parents[] = { "clk26m", "syspll3_d4", "syspll4_d4", "syspll1_d16" }; -static const char * const aud_intbus_parents[] __initconst = { +static const char * const aud_intbus_parents[] = { "clk26m", "syspll1_d4", "syspll4_d2", @@ -334,7 +339,7 @@ static const char * const aud_intbus_parents[] __initconst = { "dmpll_d8" }; -static const char * const pmicspi_parents[] __initconst = { +static const char * const pmicspi_parents[] = { "clk26m", "syspll1_d8", "syspll3_d4", @@ -345,7 +350,7 @@ static const char * const pmicspi_parents[] __initconst = { "dmpll_d16" }; -static const char * const scp_parents[] __initconst = { +static const char * const scp_parents[] = { "clk26m", "syspll1_d2", "univpll_d5", @@ -354,14 +359,14 @@ static const char * const scp_parents[] __initconst = { "dmpll_d4" }; -static const char * const atb_parents[] __initconst = { +static const char * const atb_parents[] = { "clk26m", "syspll1_d2", "univpll_d5", "dmpll_d2" }; -static const char * const venc_lt_parents[] __initconst = { +static const char * const venc_lt_parents[] = { "clk26m", "univpll_d3", "vcodecpll_ck", @@ -376,7 +381,7 @@ static const char * const venc_lt_parents[] __initconst = { "dmpll_ck" }; -static const char * const dpi0_parents[] __initconst = { +static const char * const dpi0_parents[] = { "clk26m", "tvdpll_d2", "tvdpll_d4", @@ -386,13 +391,13 @@ static const char * const dpi0_parents[] __initconst = { "tvdpll_d16" }; -static const char * const irda_parents[] __initconst = { +static const char * const irda_parents[] = { "clk26m", "univpll2_d4", "syspll2_d4" }; -static const char * const cci400_parents[] __initconst = { +static const char * const cci400_parents[] = { "clk26m", "vencpll_ck", "armca7pll_754m", @@ -403,41 +408,41 @@ static const char * const cci400_parents[] __initconst = { "dmpll_ck" }; -static const char * const aud_1_parents[] __initconst = { +static const char * const aud_1_parents[] = { "clk26m", "apll1_ck", "univpll2_d4", "univpll2_d8" }; -static const char * const aud_2_parents[] __initconst = { +static const char * const aud_2_parents[] = { "clk26m", "apll2_ck", "univpll2_d4", "univpll2_d8" }; -static const char * const mem_mfg_in_parents[] __initconst = { +static const char * const mem_mfg_in_parents[] = { "clk26m", "mmpll_ck", "dmpll_ck", "clk26m" }; -static const char * const axi_mfg_in_parents[] __initconst = { +static const char * const axi_mfg_in_parents[] = { "clk26m", "axi_sel", "dmpll_d2" }; -static const char * const scam_parents[] __initconst = { +static const char * const scam_parents[] = { "clk26m", "syspll3_d2", "univpll2_d4", "dmpll_d4" }; -static const char * const spinfi_ifr_parents[] __initconst = { +static const char * const spinfi_ifr_parents[] = { "clk26m", "univpll2_d8", "univpll3_d4", @@ -448,14 +453,14 @@ static const char * const spinfi_ifr_parents[] __initconst = { "univpll1_d4" }; -static const char * const hdmi_parents[] __initconst = { +static const char * const hdmi_parents[] = { "clk26m", "hdmitx_dig_cts", "hdmitxpll_d2", "hdmitxpll_d3" }; -static const char * const dpilvds_parents[] __initconst = { +static const char * const dpilvds_parents[] = { "clk26m", "lvdspll", "lvdspll_d2", @@ -464,7 +469,7 @@ static const char * const dpilvds_parents[] __initconst = { "fpc_ck" }; -static const char * const msdc50_2_h_parents[] __initconst = { +static const char * const msdc50_2_h_parents[] = { "clk26m", "syspll1_d2", "syspll2_d2", @@ -473,72 +478,72 @@ static const char * const msdc50_2_h_parents[] __initconst = { "univpll1_d4" }; -static const char * const hdcp_parents[] __initconst = { +static const char * const hdcp_parents[] = { "clk26m", "syspll4_d2", "syspll3_d4", "univpll2_d4" }; -static const char * const hdcp_24m_parents[] __initconst = { +static const char * const hdcp_24m_parents[] = { "clk26m", "univpll_d26", "univpll_d52", "univpll2_d8" }; -static const char * const rtc_parents[] __initconst = { +static const char * const rtc_parents[] = { "clkrtc_int", "clkrtc_ext", "clk26m", "univpll3_d8" }; -static const char * const i2s0_m_ck_parents[] __initconst = { +static const char * const i2s0_m_ck_parents[] = { "apll1_div1", "apll2_div1" }; -static const char * const i2s1_m_ck_parents[] __initconst = { +static const char * const i2s1_m_ck_parents[] = { "apll1_div2", "apll2_div2" }; -static const char * const i2s2_m_ck_parents[] __initconst = { +static const char * const i2s2_m_ck_parents[] = { "apll1_div3", "apll2_div3" }; -static const char * const i2s3_m_ck_parents[] __initconst = { +static const char * const i2s3_m_ck_parents[] = { "apll1_div4", "apll2_div4" }; -static const char * const i2s3_b_ck_parents[] __initconst = { +static const char * const i2s3_b_ck_parents[] = { "apll1_div5", "apll2_div5" }; -static const char * const ca53_parents[] __initconst = { +static const char * const ca53_parents[] = { "clk26m", "armca7pll", "mainpll", "univpll" }; -static const char * const ca72_parents[] __initconst = { +static const char * const ca72_parents[] = { "clk26m", "armca15pll", "mainpll", "univpll" }; -static const struct mtk_composite cpu_muxes[] __initconst = { +static const struct mtk_composite cpu_muxes[] = { MUX(CLK_INFRA_CA53SEL, "infra_ca53_sel", ca53_parents, 0x0000, 0, 2), MUX(CLK_INFRA_CA72SEL, "infra_ca72_sel", ca72_parents, 0x0000, 2, 2), }; -static const struct mtk_composite top_muxes[] __initconst = { +static const struct mtk_composite top_muxes[] = { /* CLK_CFG_0 */ MUX(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x0040, 0, 3), MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1), @@ -614,7 +619,7 @@ static const struct mtk_composite top_muxes[] __initconst = { MUX(CLK_TOP_I2S3_B_SEL, "i2s3_b_ck_sel", i2s3_b_ck_parents, 0x120, 8, 1), }; -static const struct mtk_gate_regs infra_cg_regs __initconst = { +static const struct mtk_gate_regs infra_cg_regs = { .set_ofs = 0x0040, .clr_ofs = 0x0044, .sta_ofs = 0x0048, @@ -629,7 +634,7 @@ static const struct mtk_gate_regs infra_cg_regs __initconst = { .ops = &mtk_clk_gate_ops_setclr, \ } -static const struct mtk_gate infra_clks[] __initconst = { +static const struct mtk_gate infra_clks[] = { GATE_ICG(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0), GATE_ICG(CLK_INFRA_SMI, "infra_smi", "mm_sel", 1), GATE_ICG(CLK_INFRA_AUDIO, "infra_audio", "aud_intbus_sel", 5), @@ -643,17 +648,17 @@ static const struct mtk_gate infra_clks[] __initconst = { GATE_ICG(CLK_INFRA_PMICWRAP, "infra_pmicwrap", "axi_sel", 23), }; -static const struct mtk_fixed_factor infra_divs[] __initconst = { +static const struct mtk_fixed_factor infra_early_divs[] = { FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2), }; -static const struct mtk_gate_regs peri0_cg_regs __initconst = { +static const struct mtk_gate_regs peri0_cg_regs = { .set_ofs = 0x0008, .clr_ofs = 0x0010, .sta_ofs = 0x0018, }; -static const struct mtk_gate_regs peri1_cg_regs __initconst = { +static const struct mtk_gate_regs peri1_cg_regs = { .set_ofs = 0x000c, .clr_ofs = 0x0014, .sta_ofs = 0x001c, @@ -677,7 +682,7 @@ static const struct mtk_gate_regs peri1_cg_regs __initconst = { .ops = &mtk_clk_gate_ops_setclr, \ } -static const struct mtk_gate peri_gates[] __initconst = { +static const struct mtk_gate peri_gates[] = { /* PERI0 */ GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0), GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1), @@ -717,19 +722,19 @@ static const struct mtk_gate peri_gates[] __initconst = { GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2), }; -static const char * const uart_ck_sel_parents[] __initconst = { +static const char * const uart_ck_sel_parents[] = { "clk26m", "uart_sel", }; -static const struct mtk_composite peri_clks[] __initconst = { +static const struct mtk_composite peri_clks[] = { MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1), MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1), MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1), MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1), }; -static const struct mtk_gate_regs cg_regs_4_8_0 __initconst = { +static const struct mtk_gate_regs cg_regs_4_8_0 = { .set_ofs = 0x0004, .clr_ofs = 0x0008, .sta_ofs = 0x0000, @@ -744,7 +749,8 @@ static const struct mtk_gate_regs cg_regs_4_8_0 __initconst = { .ops = &mtk_clk_gate_ops_setclr, \ } -static const struct mtk_gate img_clks[] __initconst = { +static const struct mtk_gate img_clks[] = { + GATE_DUMMY(CLK_DUMMY, "img_dummy"), GATE_IMG(CLK_IMG_LARB2_SMI, "img_larb2_smi", "mm_sel", 0), GATE_IMG(CLK_IMG_CAM_SMI, "img_cam_smi", "mm_sel", 5), GATE_IMG(CLK_IMG_CAM_CAM, "img_cam_cam", "mm_sel", 6), @@ -754,13 +760,13 @@ static const struct mtk_gate img_clks[] __initconst = { GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11), }; -static const struct mtk_gate_regs vdec0_cg_regs __initconst = { +static const struct mtk_gate_regs vdec0_cg_regs = { .set_ofs = 0x0000, .clr_ofs = 0x0004, .sta_ofs = 0x0000, }; -static const struct mtk_gate_regs vdec1_cg_regs __initconst = { +static const struct mtk_gate_regs vdec1_cg_regs = { .set_ofs = 0x0008, .clr_ofs = 0x000c, .sta_ofs = 0x0008, @@ -784,7 +790,8 @@ static const struct mtk_gate_regs vdec1_cg_regs __initconst = { .ops = &mtk_clk_gate_ops_setclr_inv, \ } -static const struct mtk_gate vdec_clks[] __initconst = { +static const struct mtk_gate vdec_clks[] = { + GATE_DUMMY(CLK_DUMMY, "vdec_dummy"), GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0), GATE_VDEC1(CLK_VDEC_LARB_CKEN, "vdec_larb_cken", "mm_sel", 0), }; @@ -798,7 +805,8 @@ static const struct mtk_gate vdec_clks[] __initconst = { .ops = &mtk_clk_gate_ops_setclr_inv, \ } -static const struct mtk_gate venc_clks[] __initconst = { +static const struct mtk_gate venc_clks[] = { + GATE_DUMMY(CLK_DUMMY, "venc_dummy"), GATE_VENC(CLK_VENC_CKE0, "venc_cke0", "mm_sel", 0), GATE_VENC(CLK_VENC_CKE1, "venc_cke1", "venc_sel", 4), GATE_VENC(CLK_VENC_CKE2, "venc_cke2", "venc_sel", 8), @@ -814,7 +822,8 @@ static const struct mtk_gate venc_clks[] __initconst = { .ops = &mtk_clk_gate_ops_setclr_inv, \ } -static const struct mtk_gate venclt_clks[] __initconst = { +static const struct mtk_gate venclt_clks[] = { + GATE_DUMMY(CLK_DUMMY, "venclt_dummy"), GATE_VENCLT(CLK_VENCLT_CKE0, "venclt_cke0", "mm_sel", 0), GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4), }; @@ -837,10 +846,11 @@ static const struct mtk_clk_rst_desc clk_rst_desc[] = { } }; -static struct clk_hw_onecell_data *mt8173_top_clk_data __initdata; -static struct clk_hw_onecell_data *mt8173_pll_clk_data __initdata; +static struct clk_hw_onecell_data *mt8173_top_clk_data; +static struct clk_hw_onecell_data *mt8173_pll_clk_data; +static struct clk_hw_onecell_data *infra_clk_data; -static void __init mtk_clk_enable_critical(void) +static void mtk_clk_enable_critical(void) { if (!mt8173_top_clk_data || !mt8173_pll_clk_data) return; @@ -853,102 +863,149 @@ static void __init mtk_clk_enable_critical(void) clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_RTC_SEL]->clk); } -static void __init mtk_topckgen_init(struct device_node *node) +static int clk_mt8173_topck_probe(struct platform_device *pdev) { + struct device_node *node = pdev->dev.of_node; struct clk_hw_onecell_data *clk_data; void __iomem *base; int r; - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); mt8173_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); + if (IS_ERR_OR_NULL(clk_data)) + return -ENOMEM; - mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data); - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8173_clk_lock, clk_data, NULL); + r = mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data); + if (r) + goto free_clk_data; + + r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); + if (r) + goto unregister_fixed_clks; + + r = mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, + &mt8173_clk_lock, clk_data, &pdev->dev); + if (r) + goto unregister_factors; r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); + goto unregister_composites; mtk_clk_enable_critical(); + return 0; + +unregister_composites: + mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), clk_data); +unregister_factors: + mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); +unregister_fixed_clks: + mtk_clk_unregister_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + return r; } -CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init); -static void __init mtk_infrasys_init(struct device_node *node) +static void clk_mt8173_infra_init_early(struct device_node *node) { - struct clk_hw_onecell_data *clk_data; + int i; + + infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); + if (!infra_clk_data) + return; + + for (i = 0; i < CLK_INFRA_NR_CLK; i++) + infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); + + mtk_clk_register_factors(infra_early_divs, ARRAY_SIZE(infra_early_divs), infra_clk_data); + + of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data); +} +CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg", + clk_mt8173_infra_init_early); + +static int clk_mt8173_infra_probe(struct platform_device *pdev) +{ + struct device_node *node = pdev->dev.of_node; int r; - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); + r = mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), + infra_clk_data, &pdev->dev); + if (r) + return r; - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, NULL); - mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data); + r = mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), + infra_clk_data, &pdev->dev); + if (r) + goto unregister_gates; - mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), - clk_data, NULL); + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, infra_clk_data); + if (r) + goto unregister_cpumuxes; - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r = mtk_register_reset_controller(node, &clk_rst_desc[0]); if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); + goto unregister_clk_hw; + + return 0; - mtk_register_reset_controller(node, &clk_rst_desc[0]); +unregister_clk_hw: + of_clk_del_provider(node); +unregister_cpumuxes: + mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), infra_clk_data); +unregister_gates: + mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), infra_clk_data); + return r; } -CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init); -static void __init mtk_pericfg_init(struct device_node *node) +static int clk_mt8173_peri_probe(struct platform_device *pdev) { + struct device_node *node = pdev->dev.of_node; struct clk_hw_onecell_data *clk_data; int r; void __iomem *base; - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); + if (IS_ERR_OR_NULL(clk_data)) + return -ENOMEM; - mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), - clk_data, NULL); - mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, - &mt8173_clk_lock, clk_data, NULL); + r = mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates), + clk_data, &pdev->dev); + if (r) + goto free_clk_data; + + r = mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base, + &mt8173_clk_lock, clk_data, &pdev->dev); + if (r) + goto unregister_gates; r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); + goto unregister_composites; - mtk_register_reset_controller(node, &clk_rst_desc[1]); + r = mtk_register_reset_controller(node, &clk_rst_desc[1]); + if (r) + goto unregister_clk_hw; + + return 0; + +unregister_clk_hw: + of_clk_del_provider(node); +unregister_composites: + mtk_clk_unregister_composites(peri_clks, ARRAY_SIZE(peri_clks), clk_data); +unregister_gates: + mtk_clk_unregister_gates(peri_gates, ARRAY_SIZE(peri_gates), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + return r; } -CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init); - -struct mtk_clk_usb { - int id; - const char *name; - const char *parent; - u32 reg_ofs; -}; - -#define APMIXED_USB(_id, _name, _parent, _reg_ofs) { \ - .id = _id, \ - .name = _name, \ - .parent = _parent, \ - .reg_ofs = _reg_ofs, \ - } - -static const struct mtk_clk_usb apmixed_usb[] __initconst = { - APMIXED_USB(CLK_APMIXED_REF2USB_TX, "ref2usb_tx", "clk26m", 0x8), -}; #define MT8173_PLL_FMAX (3000UL * MHZ) @@ -1007,119 +1064,130 @@ static const struct mtk_pll_data plls[] = { PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x2f0, 0x2fc, 0, 0, 21, 0x2f0, 4, 0x0, 0x2f4, 0), }; -static void __init mtk_apmixedsys_init(struct device_node *node) +static int clk_mt8173_apmixed_probe(struct platform_device *pdev) { + struct device_node *node = pdev->dev.of_node; struct clk_hw_onecell_data *clk_data; void __iomem *base; struct clk_hw *hw; - int r, i; + int r; base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return; - } + if (!base) + return PTR_ERR(base); mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK); - if (!clk_data) { - iounmap(base); - return; - } - - mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (IS_ERR_OR_NULL(clk_data)) + return -ENOMEM; - for (i = 0; i < ARRAY_SIZE(apmixed_usb); i++) { - const struct mtk_clk_usb *cku = &apmixed_usb[i]; - - hw = mtk_clk_register_ref2usb_tx(cku->name, cku->parent, base + cku->reg_ofs); - if (IS_ERR(hw)) { - pr_err("Failed to register clk %s: %ld\n", cku->name, PTR_ERR(hw)); - continue; - } + r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data); + if (r) + goto free_clk_data; - clk_data->hws[cku->id] = hw; + hw = mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REGOFF_REF2USB); + if (IS_ERR(hw)) { + r = PTR_ERR(hw); + dev_err(&pdev->dev, "Failed to register ref2usb_tx: %d\n", r); + goto unregister_plls; } + clk_data->hws[CLK_APMIXED_REF2USB_TX] = hw; - hw = clk_hw_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0, - base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO, - NULL); + hw = devm_clk_hw_register_divider(&pdev->dev, "hdmi_ref", "tvdpll_594m", 0, + base + REGOFF_HDMI_REF, 16, 3, + CLK_DIVIDER_POWER_OF_TWO, NULL); clk_data->hws[CLK_APMIXED_HDMI_REF] = hw; r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); + goto unregister_ref2usb; mtk_clk_enable_critical(); + return 0; + +unregister_ref2usb: + mtk_clk_unregister_ref2usb_tx(clk_data->hws[CLK_APMIXED_REF2USB_TX]); +unregister_plls: + mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data); +free_clk_data: + mtk_free_clk_data(clk_data); + return r; } -CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys", - mtk_apmixedsys_init); - -static void __init mtk_imgsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; - - clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK); - mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks), - clk_data, NULL); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); +static const struct mtk_clk_desc img_desc = { + .clks = img_clks, + .num_clks = ARRAY_SIZE(img_clks), +}; - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8173-imgsys", mtk_imgsys_init); +static const struct mtk_clk_desc vdec_desc = { + .clks = vdec_clks, + .num_clks = ARRAY_SIZE(vdec_clks), +}; -static void __init mtk_vdecsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; +static const struct mtk_clk_desc venc_desc = { + .clks = venc_clks, + .num_clks = ARRAY_SIZE(venc_clks), +}; - clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK); +static const struct mtk_clk_desc venc_lt_desc = { + .clks = venclt_clks, + .num_clks = ARRAY_SIZE(venclt_clks), +}; - mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks), - clk_data, NULL); +static const struct of_device_id of_match_clk_mt8173_simple[] = { + { .compatible = "mediatek,mt8173-imgsys", .data = &img_desc }, + { .compatible = "mediatek,mt8173-vdecsys", .data = &vdec_desc }, + { .compatible = "mediatek,mt8173-vencsys", .data = &venc_desc }, + { .compatible = "mediatek,mt8173-vencltsys", .data = &venc_lt_desc }, + { /* sentinel */ } +}; - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); -} -CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8173-vdecsys", mtk_vdecsys_init); +static struct platform_driver clk_mt8173_simple_drv = { + .driver = { + .name = "clk-mt8173-simple", + .of_match_table = of_match_clk_mt8173_simple, + }, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, +}; -static void __init mtk_vencsys_init(struct device_node *node) +static int clk_mt8173_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; + int (*clk_probe)(struct platform_device *pdev); int r; - clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK); + clk_probe = of_device_get_match_data(&pdev->dev); + if (!clk_probe) + return -EINVAL; - mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks), - clk_data, NULL); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r = clk_probe(pdev); if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); + dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); + + return r; } -CLK_OF_DECLARE(mtk_vencsys, "mediatek,mt8173-vencsys", mtk_vencsys_init); -static void __init mtk_vencltsys_init(struct device_node *node) -{ - struct clk_hw_onecell_data *clk_data; - int r; +static const struct of_device_id of_match_clk_mt8173[] = { + { .compatible = "mediatek,mt8173-apmixedsys", .data = clk_mt8173_apmixed_probe }, + { .compatible = "mediatek,mt8173-infracfg", .data = clk_mt8173_infra_probe }, + { .compatible = "mediatek,mt8173-topckgen", .data = clk_mt8173_topck_probe }, + { .compatible = "mediatek,mt8173-pericfg", .data = clk_mt8173_peri_probe }, + { /* sentinel */ } +}; - clk_data = mtk_alloc_clk_data(CLK_VENCLT_NR_CLK); +static struct platform_driver clk_mt8173_drv = { + .probe = clk_mt8173_probe, + .driver = { + .name = "clk-mt8173", + .of_match_table = of_match_clk_mt8173, + }, +}; - mtk_clk_register_gates(node, venclt_clks, ARRAY_SIZE(venclt_clks), - clk_data, NULL); +static int __init clk_mt8173_init(void) +{ + int ret = platform_driver_register(&clk_mt8173_drv); - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); + if (ret) + return ret; + return platform_driver_register(&clk_mt8173_simple_drv); } -CLK_OF_DECLARE(mtk_vencltsys, "mediatek,mt8173-vencltsys", mtk_vencltsys_init); +arch_initcall(clk_mt8173_init); From patchwork Thu Dec 22 11:48:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 636128 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F137FC4167B for ; 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c=relaxed/simple; d=collabora.com; s=mail; t=1671709775; bh=Tr/46hNNOpqiOPa/o4lwiU65I35XnBdfwH4jCPa5+O8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XkvZjgkK5shQMRzCcdGGltXudtsDvdURUWGjYcJTBAXYZPzM7FfHwOfzn3Wrx5UtU bioxR2SRpIqJ6SmRehVzitgBgg/+RFltcUtMqpaBXy6Ct4YnpLVakKNoF9tC1m4nXG dIA20SB/YDTwdbU3zYfcMcxyiKXFGErxLiBUGYAkQ6AXeJy+JHoKdDr1YAyrDOEjE/ QZgX/7PV/SzOT7C2vae5zGZQwaZNFTJJBJuAn7xJgBGyLhGA794rpKjl5ropAJ9aon HuGag79PsKpMLd6qdcf+Y3LC+y87JX6zKrhb70p7qnSg75NdWr8/4AdJDmWuSIPjQ9 eWEeyp7OPIGEA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v1 12/25] dt-bindings: clock: mt2701/mt6779: Add dummy clock with ID 0 Date: Thu, 22 Dec 2022 12:48:44 +0100 Message-Id: <20221222114857.120060-13-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> References: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As done for MT8173 and as a preparation for clock controller drivers cleanups, add a dummy clock with ID 0, allowing us to simplify driver probe. Signed-off-by: AngeloGioacchino Del Regno --- include/dt-bindings/clock/mt2701-clk.h | 3 +++ include/dt-bindings/clock/mt6779-clk.h | 3 +++ 2 files changed, 6 insertions(+) diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h index 6d531d5ae065..0ec2c81453b0 100644 --- a/include/dt-bindings/clock/mt2701-clk.h +++ b/include/dt-bindings/clock/mt2701-clk.h @@ -7,6 +7,9 @@ #ifndef _DT_BINDINGS_CLK_MT2701_H #define _DT_BINDINGS_CLK_MT2701_H +/* Dummy clock for backwards compatibility */ +#define CLK_DUMMY 0 + /* TOPCKGEN */ #define CLK_TOP_SYSPLL 1 #define CLK_TOP_SYSPLL_D2 2 diff --git a/include/dt-bindings/clock/mt6779-clk.h b/include/dt-bindings/clock/mt6779-clk.h index b083139afbd2..478d4af33b2a 100644 --- a/include/dt-bindings/clock/mt6779-clk.h +++ b/include/dt-bindings/clock/mt6779-clk.h @@ -7,6 +7,9 @@ #ifndef _DT_BINDINGS_CLK_MT6779_H #define _DT_BINDINGS_CLK_MT6779_H +/* Dummy clock for backwards compatibility */ +#define CLK_DUMMY 0 + /* TOPCKGEN */ #define CLK_TOP_AXI 1 #define CLK_TOP_MM 2 From patchwork Thu Dec 22 11:48:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 636126 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68211C41535 for ; Thu, 22 Dec 2022 11:56:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235778AbiLVL4c (ORCPT ); Thu, 22 Dec 2022 06:56:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235522AbiLVLzD (ORCPT ); Thu, 22 Dec 2022 06:55:03 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5EC102CC9C; Thu, 22 Dec 2022 03:49:38 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 9E8D46602CDF; Thu, 22 Dec 2022 11:49:35 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671709777; bh=9AMGeEobxZAlGGSxOjtTru9sFdkLsAzlzcePTMEUc+U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nduLXxZxZaVgkBjNh4b3WeQbTbVnXkrZlUE8lYvsovTcpxvXJsXHkNeIXkSBeIk44 2Rty2NW3+eYLWKPCzq3K7jsqH/hjiPsVnYoD7H6UOcCBHzteG9qzXAiwspuB1rBIYC y2livRTy82nG5HFWvVct/wkSdbJGJfLXOkaH4N6qFRP6xOZbrFLzeQHyyJDAcHGwTw l2MC2X3gjTTnkGsaaBjD3EnivZLXye0X2yJ38PjD7hx52g8bHKJZoih8QmB6ffXEUV mUN63BkZctQi+0VEhK/Qn/bAVjVCXjqgCwrtwVAMOccZiHg18bx2A3F6DauoJvYrm5 +OBXnR1VFkipQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v1 13/25] clk: mediatek: Switch to mtk_clk_simple_probe() where possible Date: Thu, 22 Dec 2022 12:48:45 +0100 Message-Id: <20221222114857.120060-14-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> References: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org mtk_clk_simple_probe() is a function that registers mtk gate clocks and, if reset data is present, a reset controller and across all of the MTK clock drivers, such a function is duplicated many times: switch to the common mtk_clk_simple_probe() function for all of the clock drivers that are registering as platform drivers. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt2701-aud.c | 26 +++---- drivers/clk/mediatek/clk-mt2701-eth.c | 34 +++------ drivers/clk/mediatek/clk-mt2701-g3d.c | 56 +++----------- drivers/clk/mediatek/clk-mt2701-hif.c | 36 +++------ drivers/clk/mediatek/clk-mt2712.c | 83 ++++++++------------- drivers/clk/mediatek/clk-mt6779.c | 42 ++++++----- drivers/clk/mediatek/clk-mt7622-aud.c | 49 +++---------- drivers/clk/mediatek/clk-mt7622-eth.c | 82 ++++----------------- drivers/clk/mediatek/clk-mt7622-hif.c | 85 ++++----------------- drivers/clk/mediatek/clk-mt7629-hif.c | 85 ++++----------------- drivers/clk/mediatek/clk-mt8183-audio.c | 19 +++-- drivers/clk/mediatek/clk-mt8183.c | 75 ++++++++----------- drivers/clk/mediatek/clk-mt8192-aud.c | 25 +++---- drivers/clk/mediatek/clk-mt8192.c | 98 ++++++++----------------- 14 files changed, 236 insertions(+), 559 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c b/drivers/clk/mediatek/clk-mt2701-aud.c index ab13ab618fb5..1fd6d96b34dc 100644 --- a/drivers/clk/mediatek/clk-mt2701-aud.c +++ b/drivers/clk/mediatek/clk-mt2701-aud.c @@ -76,6 +76,7 @@ static const struct mtk_gate_regs audio3_cg_regs = { }; static const struct mtk_gate audio_clks[] = { + GATE_DUMMY(CLK_DUMMY, "aud_dummy"), /* AUDIO0 */ GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2), GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20), @@ -138,29 +139,26 @@ static const struct mtk_gate audio_clks[] = { GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), }; +static const struct mtk_clk_desc audio_desc = { + .clks = audio_clks, + .num_clks = ARRAY_SIZE(audio_clks), +}; + static const struct of_device_id of_match_clk_mt2701_aud[] = { - { .compatible = "mediatek,mt2701-audsys", }, - {} + { .compatible = "mediatek,mt2701-audsys", .data = &audio_desc }, + { /* sentinel */ } }; static int clk_mt2701_aud_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; int r; - clk_data = mtk_alloc_clk_data(CLK_AUD_NR); - - mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r = mtk_clk_simple_probe(pdev); if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); - - goto err_clk_provider; + return r; } r = devm_of_platform_populate(&pdev->dev); @@ -170,13 +168,13 @@ static int clk_mt2701_aud_probe(struct platform_device *pdev) return 0; err_plat_populate: - of_clk_del_provider(node); -err_clk_provider: + mtk_clk_simple_remove(pdev); return r; } static struct platform_driver clk_mt2701_aud_drv = { .probe = clk_mt2701_aud_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt2701-aud", .of_match_table = of_match_clk_mt2701_aud, diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c index 9670e1e170f2..bd3fddf53ce1 100644 --- a/drivers/clk/mediatek/clk-mt2701-eth.c +++ b/drivers/clk/mediatek/clk-mt2701-eth.c @@ -26,6 +26,7 @@ static const struct mtk_gate_regs eth_cg_regs = { } static const struct mtk_gate eth_clks[] = { + GATE_DUMMY(CLK_DUMMY, "eth_dummy"), GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5), GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6), GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7), @@ -44,35 +45,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; +static const struct mtk_clk_desc eth_desc = { + .clks = eth_clks, + .num_clks = ARRAY_SIZE(eth_clks), + .rst_desc = &clk_rst_desc, +}; + static const struct of_device_id of_match_clk_mt2701_eth[] = { - { .compatible = "mediatek,mt2701-ethsys", }, + { .compatible = "mediatek,mt2701-ethsys", .data = ð_desc }, {} }; -static int clk_mt2701_eth_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR); - - mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - static struct platform_driver clk_mt2701_eth_drv = { - .probe = clk_mt2701_eth_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt2701-eth", .of_match_table = of_match_clk_mt2701_eth, diff --git a/drivers/clk/mediatek/clk-mt2701-g3d.c b/drivers/clk/mediatek/clk-mt2701-g3d.c index 11391b144267..499a170ba5f9 100644 --- a/drivers/clk/mediatek/clk-mt2701-g3d.c +++ b/drivers/clk/mediatek/clk-mt2701-g3d.c @@ -32,6 +32,7 @@ static const struct mtk_gate_regs g3d_cg_regs = { }; static const struct mtk_gate g3d_clks[] = { + GATE_DUMMY(CLK_DUMMY, "g3d_dummy"), GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0), }; @@ -43,57 +44,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; -static int clk_mt2701_g3dsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR); - - mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} +static const struct mtk_clk_desc g3d_desc = { + .clks = g3d_clks, + .num_clks = ARRAY_SIZE(g3d_clks), + .rst_desc = &clk_rst_desc, +}; static const struct of_device_id of_match_clk_mt2701_g3d[] = { - { - .compatible = "mediatek,mt2701-g3dsys", - .data = clk_mt2701_g3dsys_init, - }, { - /* sentinel */ - } + { .compatible = "mediatek,mt2701-g3dsys", .data = &g3d_desc }, + { /* sentinel */ } }; -static int clk_mt2701_g3d_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init = of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r = clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt2701_g3d_drv = { - .probe = clk_mt2701_g3d_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt2701-g3d", .of_match_table = of_match_clk_mt2701_g3d, diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c index c14c0bb10f88..5d113838b3e4 100644 --- a/drivers/clk/mediatek/clk-mt2701-hif.c +++ b/drivers/clk/mediatek/clk-mt2701-hif.c @@ -26,6 +26,7 @@ static const struct mtk_gate_regs hif_cg_regs = { } static const struct mtk_gate hif_clks[] = { + GATE_DUMMY(CLK_DUMMY, "hif_dummy"), GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21), GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22), GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24), @@ -41,37 +42,20 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; +static const struct mtk_clk_desc hif_desc = { + .clks = hif_clks, + .num_clks = ARRAY_SIZE(hif_clks), + .rst_desc = &clk_rst_desc, +}; + static const struct of_device_id of_match_clk_mt2701_hif[] = { - { .compatible = "mediatek,mt2701-hifsys", }, + { .compatible = "mediatek,mt2701-hifsys", .data = &hif_desc }, {} }; -static int clk_mt2701_hif_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR); - - mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - return r; - } - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return 0; -} - static struct platform_driver clk_mt2701_hif_drv = { - .probe = clk_mt2701_hif_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt2701-hif", .of_match_table = of_match_clk_mt2701_hif, diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c index 5cadcf6ca9b7..c4bee791f570 100644 --- a/drivers/clk/mediatek/clk-mt2712.c +++ b/drivers/clk/mediatek/clk-mt2712.c @@ -1362,50 +1362,6 @@ static int clk_mt2712_top_probe(struct platform_device *pdev) return r; } -static int clk_mt2712_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r != 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]); - - return r; -} - -static int clk_mt2712_peri_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - int r; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); - - mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r != 0) - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]); - - return r; -} - static int clk_mt2712_mcu_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; @@ -1440,12 +1396,6 @@ static const struct of_device_id of_match_clk_mt2712[] = { }, { .compatible = "mediatek,mt2712-topckgen", .data = clk_mt2712_top_probe, - }, { - .compatible = "mediatek,mt2712-infracfg", - .data = clk_mt2712_infra_probe, - }, { - .compatible = "mediatek,mt2712-pericfg", - .data = clk_mt2712_peri_probe, }, { .compatible = "mediatek,mt2712-mcucfg", .data = clk_mt2712_mcu_probe, @@ -1472,6 +1422,33 @@ static int clk_mt2712_probe(struct platform_device *pdev) return r; } +static const struct mtk_clk_desc infra_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), + .rst_desc = &clk_rst_desc[0], +}; + +static const struct mtk_clk_desc peri_desc = { + .clks = peri_clks, + .num_clks = ARRAY_SIZE(peri_clks), + .rst_desc = &clk_rst_desc[1], +}; + +static const struct of_device_id of_match_clk_mt2712_simple[] = { + { .compatible = "mediatek,mt2712-infracfg", .data = &infra_desc }, + { .compatible = "mediatek,mt2712-pericfg", .data = &peri_desc, }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt2712_simple_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt2712-simple", + .of_match_table = of_match_clk_mt2712_simple, + }, +}; + static struct platform_driver clk_mt2712_drv = { .probe = clk_mt2712_probe, .driver = { @@ -1482,7 +1459,11 @@ static struct platform_driver clk_mt2712_drv = { static int __init clk_mt2712_init(void) { - return platform_driver_register(&clk_mt2712_drv); + int ret = platform_driver_register(&clk_mt2712_drv); + + if (ret) + return ret; + return platform_driver_register(&clk_mt2712_simple_drv); } arch_initcall(clk_mt2712_init); diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c index 6d1fb19be77b..479fb38766ea 100644 --- a/drivers/clk/mediatek/clk-mt6779.c +++ b/drivers/clk/mediatek/clk-mt6779.c @@ -880,6 +880,7 @@ static const struct mtk_gate_regs infra3_cg_regs = { &mtk_clk_gate_ops_setclr) static const struct mtk_gate infra_clks[] = { + GATE_DUMMY(CLK_DUMMY, "ifa_dummy"), /* INFRA0 */ GATE_INFRA0(CLK_INFRA_PMIC_TMR, "infra_pmic_tmr", "axi_sel", 0), @@ -1256,19 +1257,6 @@ static int clk_mt6779_top_probe(struct platform_device *pdev) return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); } -static int clk_mt6779_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, &pdev->dev); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - static const struct of_device_id of_match_clk_mt6779[] = { { .compatible = "mediatek,mt6779-apmixed", @@ -1276,9 +1264,6 @@ static const struct of_device_id of_match_clk_mt6779[] = { }, { .compatible = "mediatek,mt6779-topckgen", .data = clk_mt6779_top_probe, - }, { - .compatible = "mediatek,mt6779-infracfg_ao", - .data = clk_mt6779_infra_probe, }, { /* sentinel */ } @@ -1302,6 +1287,25 @@ static int clk_mt6779_probe(struct platform_device *pdev) return r; } +static const struct mtk_clk_desc infra_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), +}; + +static const struct of_device_id of_match_clk_mt6779_infra[] = { + { .compatible = "mediatek,mt6779-infracfg_ao", .data = &infra_desc }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt6779_infra_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt6779-infra", + .of_match_table = of_match_clk_mt6779_infra, + }, +}; + static struct platform_driver clk_mt6779_drv = { .probe = clk_mt6779_probe, .driver = { @@ -1312,7 +1316,11 @@ static struct platform_driver clk_mt6779_drv = { static int __init clk_mt6779_init(void) { - return platform_driver_register(&clk_mt6779_drv); + int ret = platform_driver_register(&clk_mt6779_drv); + + if (ret) + return ret; + return platform_driver_register(&clk_mt6779_infra_drv); } arch_initcall(clk_mt6779_init); diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/clk-mt7622-aud.c index d0379d8704af..86464cc750e2 100644 --- a/drivers/clk/mediatek/clk-mt7622-aud.c +++ b/drivers/clk/mediatek/clk-mt7622-aud.c @@ -130,24 +130,21 @@ static const struct mtk_gate audio_clks[] = { GATE_AUDIO3(CLK_AUDIO_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14), }; -static int clk_mt7622_audiosys_init(struct platform_device *pdev) +static const struct mtk_clk_desc audio_desc = { + .clks = audio_clks, + .num_clks = ARRAY_SIZE(audio_clks), +}; + +static int clk_mt7622_aud_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; int r; - clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); - - mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r = mtk_clk_simple_probe(pdev); if (r) { dev_err(&pdev->dev, "could not register clock provider: %s: %d\n", pdev->name, r); - - goto err_clk_provider; + return r; } r = devm_of_platform_populate(&pdev->dev); @@ -157,40 +154,18 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev) return 0; err_plat_populate: - of_clk_del_provider(node); -err_clk_provider: + mtk_clk_simple_remove(pdev); return r; } static const struct of_device_id of_match_clk_mt7622_aud[] = { - { - .compatible = "mediatek,mt7622-audsys", - .data = clk_mt7622_audiosys_init, - }, { - /* sentinel */ - } + { .compatible = "mediatek,mt7622-audsys", .data = &audio_desc }, + { /* sentinel */ } }; -static int clk_mt7622_aud_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init = of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r = clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt7622_aud_drv = { .probe = clk_mt7622_aud_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt7622-aud", .of_match_table = of_match_clk_mt7622_aud, diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c index 9b4a26ca0f44..7dd0cec802f7 100644 --- a/drivers/clk/mediatek/clk-mt7622-eth.c +++ b/drivers/clk/mediatek/clk-mt7622-eth.c @@ -73,80 +73,26 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; -static int clk_mt7622_ethsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK); - - mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - -static int clk_mt7622_sgmiisys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK); - - mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); +static const struct mtk_clk_desc eth_desc = { + .clks = eth_clks, + .num_clks = ARRAY_SIZE(eth_clks), + .rst_desc = &clk_rst_desc, +}; - return r; -} +static const struct mtk_clk_desc sgmii_desc = { + .clks = eth_clks, + .num_clks = ARRAY_SIZE(sgmii_clks), +}; static const struct of_device_id of_match_clk_mt7622_eth[] = { - { - .compatible = "mediatek,mt7622-ethsys", - .data = clk_mt7622_ethsys_init, - }, { - .compatible = "mediatek,mt7622-sgmiisys", - .data = clk_mt7622_sgmiisys_init, - }, { - /* sentinel */ - } + { .compatible = "mediatek,mt7622-ethsys", .data = ð_desc }, + { .compatible = "mediatek,mt7622-sgmiisys", .data = &sgmii_desc }, + { /* sentinel */ } }; -static int clk_mt7622_eth_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init = of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r = clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt7622_eth_drv = { - .probe = clk_mt7622_eth_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt7622-eth", .of_match_table = of_match_clk_mt7622_eth, diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c index 8cf37f75ca77..ab5cad0c2b1c 100644 --- a/drivers/clk/mediatek/clk-mt7622-hif.c +++ b/drivers/clk/mediatek/clk-mt7622-hif.c @@ -84,82 +84,27 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; -static int clk_mt7622_ssusbsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); - - mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - -static int clk_mt7622_pciesys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); - - mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); +static const struct mtk_clk_desc ssusb_desc = { + .clks = ssusb_clks, + .num_clks = ARRAY_SIZE(ssusb_clks), + .rst_desc = &clk_rst_desc, +}; - return r; -} +static const struct mtk_clk_desc pcie_desc = { + .clks = pcie_clks, + .num_clks = ARRAY_SIZE(pcie_clks), + .rst_desc = &clk_rst_desc, +}; static const struct of_device_id of_match_clk_mt7622_hif[] = { - { - .compatible = "mediatek,mt7622-pciesys", - .data = clk_mt7622_pciesys_init, - }, { - .compatible = "mediatek,mt7622-ssusbsys", - .data = clk_mt7622_ssusbsys_init, - }, { - /* sentinel */ - } + { .compatible = "mediatek,mt7622-pciesys", .data = &pcie_desc }, + { .compatible = "mediatek,mt7622-ssusbsys", .data = &ssusb_desc }, + { /* sentinel */ } }; -static int clk_mt7622_hif_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init = of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r = clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt7622_hif_drv = { - .probe = clk_mt7622_hif_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt7622-hif", .of_match_table = of_match_clk_mt7622_hif, diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index 44fbd88b4647..c3eb09ea6036 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -79,82 +79,27 @@ static const struct mtk_clk_rst_desc clk_rst_desc = { .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; -static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK); - - mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - -static int clk_mt7629_pciesys_init(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK); - - mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); +static const struct mtk_clk_desc ssusb_desc = { + .clks = ssusb_clks, + .num_clks = ARRAY_SIZE(ssusb_clks), + .rst_desc = &clk_rst_desc, +}; - return r; -} +static const struct mtk_clk_desc pcie_desc = { + .clks = pcie_clks, + .num_clks = ARRAY_SIZE(pcie_clks), + .rst_desc = &clk_rst_desc, +}; static const struct of_device_id of_match_clk_mt7629_hif[] = { - { - .compatible = "mediatek,mt7629-pciesys", - .data = clk_mt7629_pciesys_init, - }, { - .compatible = "mediatek,mt7629-ssusbsys", - .data = clk_mt7629_ssusbsys_init, - }, { - /* sentinel */ - } + { .compatible = "mediatek,mt7629-pciesys", .data = &pcie_desc }, + { .compatible = "mediatek,mt7629-ssusbsys", .data = &ssusb_desc }, + { /* sentinel */ } }; -static int clk_mt7629_hif_probe(struct platform_device *pdev) -{ - int (*clk_init)(struct platform_device *); - int r; - - clk_init = of_device_get_match_data(&pdev->dev); - if (!clk_init) - return -EINVAL; - - r = clk_init(pdev); - if (r) - dev_err(&pdev->dev, - "could not register clock provider: %s: %d\n", - pdev->name, r); - - return r; -} - static struct platform_driver clk_mt7629_hif_drv = { - .probe = clk_mt7629_hif_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt7629-hif", .of_match_table = of_match_clk_mt7629_hif, diff --git a/drivers/clk/mediatek/clk-mt8183-audio.c b/drivers/clk/mediatek/clk-mt8183-audio.c index f4c6448b6f74..f5600450b4d1 100644 --- a/drivers/clk/mediatek/clk-mt8183-audio.c +++ b/drivers/clk/mediatek/clk-mt8183-audio.c @@ -67,35 +67,34 @@ static const struct mtk_gate audio_clks[] = { 20), }; +static const struct mtk_clk_desc audio_desc = { + .clks = audio_clks, + .num_clks = ARRAY_SIZE(audio_clks), +}; + static int clk_mt8183_audio_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; int r; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK); - - mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks), - clk_data, &pdev->dev); - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r = mtk_clk_simple_probe(pdev); if (r) return r; r = devm_of_platform_populate(&pdev->dev); if (r) - of_clk_del_provider(node); + mtk_clk_simple_remove(pdev); return r; } static const struct of_device_id of_match_clk_mt8183_audio[] = { - { .compatible = "mediatek,mt8183-audiosys", }, + { .compatible = "mediatek,mt8183-audiosys", .data = &audio_desc }, {} }; static struct platform_driver clk_mt8183_audio_drv = { .probe = clk_mt8183_audio_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8183-audio", .of_match_table = of_match_clk_mt8183_audio, diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c index 10a82b542376..f1d84c0730d5 100644 --- a/drivers/clk/mediatek/clk-mt8183.c +++ b/drivers/clk/mediatek/clk-mt8183.c @@ -1187,43 +1187,6 @@ static int clk_mt8183_top_probe(struct platform_device *pdev) top_clk_data); } -static int clk_mt8183_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - - mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) { - dev_err(&pdev->dev, - "%s(): could not register clock provider: %d\n", - __func__, r); - return r; - } - - mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - - return r; -} - -static int clk_mt8183_peri_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - - clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); - - mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data, &pdev->dev); - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); -} - static int clk_mt8183_mcu_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; @@ -1249,12 +1212,6 @@ static const struct of_device_id of_match_clk_mt8183[] = { }, { .compatible = "mediatek,mt8183-topckgen", .data = clk_mt8183_top_probe, - }, { - .compatible = "mediatek,mt8183-infracfg", - .data = clk_mt8183_infra_probe, - }, { - .compatible = "mediatek,mt8183-pericfg", - .data = clk_mt8183_peri_probe, }, { .compatible = "mediatek,mt8183-mcucfg", .data = clk_mt8183_mcu_probe, @@ -1281,6 +1238,32 @@ static int clk_mt8183_probe(struct platform_device *pdev) return r; } +static const struct mtk_clk_desc infra_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), + .rst_desc = &clk_rst_desc, +}; + +static const struct mtk_clk_desc peri_desc = { + .clks = peri_clks, + .num_clks = ARRAY_SIZE(peri_clks), +}; + +static const struct of_device_id of_match_clk_mt8183_simple[] = { + { .compatible = "mediatek,mt8183-infracfg", .data = &infra_desc }, + { .compatible = "mediatek,mt8183-pericfg", .data = &peri_desc, }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8183_simple_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8183-simple", + .of_match_table = of_match_clk_mt8183_simple, + }, +}; + static struct platform_driver clk_mt8183_drv = { .probe = clk_mt8183_probe, .driver = { @@ -1291,7 +1274,11 @@ static struct platform_driver clk_mt8183_drv = { static int __init clk_mt8183_init(void) { - return platform_driver_register(&clk_mt8183_drv); + int ret = platform_driver_register(&clk_mt8183_drv); + + if (ret) + return ret; + return platform_driver_register(&clk_mt8183_simple_drv); } arch_initcall(clk_mt8183_init); diff --git a/drivers/clk/mediatek/clk-mt8192-aud.c b/drivers/clk/mediatek/clk-mt8192-aud.c index 3acadca2452a..d52f671e20ce 100644 --- a/drivers/clk/mediatek/clk-mt8192-aud.c +++ b/drivers/clk/mediatek/clk-mt8192-aud.c @@ -77,39 +77,34 @@ static const struct mtk_gate aud_clks[] = { GATE_AUD2(CLK_AUD_I2S9_B, "aud_i2s9_b", "audio_sel", 4), }; +static const struct mtk_clk_desc aud_desc = { + .clks = aud_clks, + .num_clks = ARRAY_SIZE(aud_clks), +}; + static int clk_mt8192_aud_probe(struct platform_device *pdev) { - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; int r; - clk_data = mtk_alloc_clk_data(CLK_AUD_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r = mtk_clk_register_gates(node, aud_clks, ARRAY_SIZE(aud_clks), - clk_data, &pdev->dev); - if (r) - return r; - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); + r = mtk_clk_simple_probe(pdev); if (r) return r; r = devm_of_platform_populate(&pdev->dev); if (r) - of_clk_del_provider(node); + mtk_clk_simple_remove(pdev); return r; } static const struct of_device_id of_match_clk_mt8192_aud[] = { - { .compatible = "mediatek,mt8192-audsys", }, - {} + { .compatible = "mediatek,mt8192-audsys", .data = &aud_desc }, + { /* sentinel */ } }; static struct platform_driver clk_mt8192_aud_drv = { .probe = clk_mt8192_aud_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8192-aud", .of_match_table = of_match_clk_mt8192_aud, diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index 3ca068a4c552..9a9d51bfb84d 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1158,66 +1158,6 @@ static int clk_mt8192_top_probe(struct platform_device *pdev) return r; } -static int clk_mt8192_infra_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r = mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), - clk_data, &pdev->dev); - if (r) - goto free_clk_data; - - r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc); - if (r) - goto unregister_gates; - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - return r; - -unregister_gates: - mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8192_peri_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - - clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK); - if (!clk_data) - return -ENOMEM; - - r = mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks), - clk_data, &pdev->dev); - if (r) - goto free_clk_data; - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_gates; - - return r; - -unregister_gates: - mtk_clk_unregister_gates(peri_clks, ARRAY_SIZE(peri_clks), clk_data); -free_clk_data: - mtk_free_clk_data(clk_data); - return r; -} - static int clk_mt8192_apmixed_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; @@ -1255,12 +1195,6 @@ static const struct of_device_id of_match_clk_mt8192[] = { }, { .compatible = "mediatek,mt8192-topckgen", .data = clk_mt8192_top_probe, - }, { - .compatible = "mediatek,mt8192-infracfg", - .data = clk_mt8192_infra_probe, - }, { - .compatible = "mediatek,mt8192-pericfg", - .data = clk_mt8192_peri_probe, }, { /* sentinel */ } @@ -1282,6 +1216,32 @@ static int clk_mt8192_probe(struct platform_device *pdev) return r; } +static const struct mtk_clk_desc infra_desc = { + .clks = infra_clks, + .num_clks = ARRAY_SIZE(infra_clks), + .rst_desc = &clk_rst_desc, +}; + +static const struct mtk_clk_desc peri_desc = { + .clks = peri_clks, + .num_clks = ARRAY_SIZE(peri_clks), +}; + +static const struct of_device_id of_match_clk_mt8192_simple[] = { + { .compatible = "mediatek,mt8192-infracfg", .data = &infra_desc }, + { .compatible = "mediatek,mt8192-pericfg", .data = &peri_desc }, + { /* sentinel */ } +}; + +static struct platform_driver clk_mt8192_simple_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8192-simple", + .of_match_table = of_match_clk_mt8192_simple, + }, +}; + static struct platform_driver clk_mt8192_drv = { .probe = clk_mt8192_probe, .driver = { @@ -1292,7 +1252,11 @@ static struct platform_driver clk_mt8192_drv = { static int __init clk_mt8192_init(void) { - return platform_driver_register(&clk_mt8192_drv); + int ret = platform_driver_register(&clk_mt8192_drv); + + if (ret) + return ret; + return platform_driver_register(&clk_mt8192_simple_drv); } arch_initcall(clk_mt8192_init); From patchwork Thu Dec 22 11:48:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 636127 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B204FC001B2 for ; Thu, 22 Dec 2022 11:56:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235703AbiLVL4a (ORCPT ); Thu, 22 Dec 2022 06:56:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232013AbiLVLzC (ORCPT ); Thu, 22 Dec 2022 06:55:02 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FC232CCA2; Thu, 22 Dec 2022 03:49:39 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 50B056602CDD; Thu, 22 Dec 2022 11:49:37 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671709778; bh=NDY+uaez18W4BwgRtO+4UNCg4HcrE/+PE351Z4/8UD4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=W3ihDvn7i4u8tMdWj7Uc3gsunWqWWAwtIVhcTp5HWxztgaEwSMcSwqW/DoQsqovgX ojfXa5hhw6eovdyz4V6ECAq5IBic6NTbc4KWqtw81BwmJo7/N2i8hdvycxXXW5ijZx 8nU9r3aGDXoKO6ZC17R5qWh51NvI2YZwSX5m9rmpQNt1lXtX9Jr4E8OW3a+vL2QkGT 1iryIl/8NX9MXowMZw+l/hhXhWIgC+5DpBXJvavTTpKLNRwlKukU4hpYiq85RiivEt AElWJke+tI7QCKRLTnCFcNCn1dgyN9INZCt8NCKQ89LesROW3lmTxktsNnTmBTjuK2 YfGgOGGO5PElA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v1 14/25] clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe() Date: Thu, 22 Dec 2022 12:48:46 +0100 Message-Id: <20221222114857.120060-15-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> References: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As a preparation to increase probe functions commonization across various MediaTek SoC clock controller drivers, extend function mtk_clk_simple_probe() to be able to register not only gates, but also fixed clocks, factors, muxes and composites. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mtk.c | 101 ++++++++++++++++++++++++++++++--- drivers/clk/mediatek/clk-mtk.h | 10 ++++ 2 files changed, 103 insertions(+), 8 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index d05364e17e95..b0a6225cd7b2 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -11,12 +11,14 @@ #include #include #include +#include #include #include #include #include "clk-mtk.h" #include "clk-gate.h" +#include "clk-mux.h" const struct mtk_gate_regs cg_regs_dummy = { 0, 0, 0 }; @@ -465,20 +467,71 @@ int mtk_clk_simple_probe(struct platform_device *pdev) const struct mtk_clk_desc *mcd; struct clk_hw_onecell_data *clk_data; struct device_node *node = pdev->dev.of_node; - int r; + void __iomem *base; + int num_clks, r; mcd = of_device_get_match_data(&pdev->dev); if (!mcd) return -EINVAL; - clk_data = mtk_alloc_clk_data(mcd->num_clks); + /* Composite clocks needs us to pass iomem pointer */ + if (mcd->composite_clks) { + if (!mcd->shared_io) + base = devm_platform_ioremap_resource(pdev, 0); + else + base = of_iomap(node, 0); + + if (IS_ERR_OR_NULL(base)) + return IS_ERR(base) ? PTR_ERR(base) : -ENOMEM; + } + + /* Calculate how many clk_hw_onecell_data entries to allocate */ + num_clks = mcd->num_clks + mcd->num_composite_clks; + num_clks += mcd->num_fixed_clks + mcd->num_factor_clks; + num_clks += mcd->num_mux_clks; + + clk_data = mtk_alloc_clk_data(num_clks); if (!clk_data) return -ENOMEM; - r = mtk_clk_register_gates(node, mcd->clks, mcd->num_clks, - clk_data, &pdev->dev); - if (r) - goto free_data; + if (mcd->fixed_clks) { + r = mtk_clk_register_fixed_clks(mcd->fixed_clks, + mcd->num_fixed_clks, clk_data); + if (r) + goto free_data; + } + + if (mcd->factor_clks) { + r = mtk_clk_register_factors(mcd->factor_clks, + mcd->num_factor_clks, clk_data); + if (r) + goto unregister_fixed_clks; + } + + if (mcd->mux_clks) { + r = mtk_clk_register_muxes(mcd->mux_clks, mcd->num_mux_clks, + node, mcd->clk_lock, clk_data, + &pdev->dev); + if (r) + goto unregister_factors; + }; + + if (mcd->composite_clks) { + /* We don't check composite_lock because it's optional */ + r = mtk_clk_register_composites(mcd->composite_clks, + mcd->num_composite_clks, + base, mcd->clk_lock, + clk_data, &pdev->dev); + if (r) + goto unregister_muxes; + } + + if (mcd->clks) { + r = mtk_clk_register_gates(node, mcd->clks, mcd->num_clks, + clk_data, &pdev->dev); + if (r) + goto unregister_composites; + } r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) @@ -496,9 +549,28 @@ int mtk_clk_simple_probe(struct platform_device *pdev) return r; unregister_clks: - mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); + if (mcd->clks) + mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); +unregister_composites: + if (mcd->composite_clks) + mtk_clk_unregister_composites(mcd->composite_clks, + mcd->num_composite_clks, clk_data); +unregister_muxes: + if (mcd->mux_clks) + mtk_clk_unregister_muxes(mcd->mux_clks, + mcd->num_mux_clks, clk_data); +unregister_factors: + if (mcd->factor_clks) + mtk_clk_unregister_factors(mcd->factor_clks, + mcd->num_factor_clks, clk_data); +unregister_fixed_clks: + if (mcd->fixed_clks) + mtk_clk_unregister_fixed_clks(mcd->fixed_clks, + mcd->num_fixed_clks, clk_data); free_data: mtk_free_clk_data(clk_data); + if (mcd->shared_io && base) + iounmap(base); return r; } EXPORT_SYMBOL_GPL(mtk_clk_simple_probe); @@ -510,7 +582,20 @@ int mtk_clk_simple_remove(struct platform_device *pdev) struct device_node *node = pdev->dev.of_node; of_clk_del_provider(node); - mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); + if (mcd->clks) + mtk_clk_unregister_gates(mcd->clks, mcd->num_clks, clk_data); + if (mcd->composite_clks) + mtk_clk_unregister_composites(mcd->composite_clks, + mcd->num_composite_clks, clk_data); + if (mcd->mux_clks) + mtk_clk_unregister_muxes(mcd->mux_clks, + mcd->num_mux_clks, clk_data); + if (mcd->factor_clks) + mtk_clk_unregister_factors(mcd->factor_clks, + mcd->num_factor_clks, clk_data); + if (mcd->fixed_clks) + mtk_clk_unregister_fixed_clks(mcd->fixed_clks, + mcd->num_fixed_clks, clk_data); mtk_free_clk_data(clk_data); return 0; diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index b72e88c0179f..f49aea3fb4bd 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -218,7 +218,17 @@ void mtk_clk_unregister_ref2usb_tx(struct clk_hw *hw); struct mtk_clk_desc { const struct mtk_gate *clks; size_t num_clks; + const struct mtk_composite *composite_clks; + size_t num_composite_clks; + const struct mtk_fixed_clk *fixed_clks; + size_t num_fixed_clks; + const struct mtk_fixed_factor *factor_clks; + size_t num_factor_clks; + const struct mtk_mux *mux_clks; + size_t num_mux_clks; const struct mtk_clk_rst_desc *rst_desc; + spinlock_t *clk_lock; + bool shared_io; }; int mtk_clk_simple_probe(struct platform_device *pdev); From patchwork Thu Dec 22 11:48:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 636125 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D34DCC4332F for ; Thu, 22 Dec 2022 11:56:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235630AbiLVL4h (ORCPT ); Thu, 22 Dec 2022 06:56:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235637AbiLVLzJ (ORCPT ); Thu, 22 Dec 2022 06:55:09 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 076BA2CCB8; Thu, 22 Dec 2022 03:49:45 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 8A3A76602D06; Thu, 22 Dec 2022 11:49:42 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671709784; bh=p4HuxSnc6rYIjz4n4YZOsHO8uVPvIY0fR52pGIHTaV4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gbP/ly7JKiBIW4uKo5D7fUJv2akHh+vniPP8hKkXDl1Uj4J463fdO8zKB4Ch6jfVa DtQd7nsrAkZbvgRY18+/u74sAyjKdZMNP3TpcrNoKTrHiXcFDsyvOCOJFCzpVJCCPb WqTdql2eb0HFsqOeHxK9k8cw5O5cU2+kFrcIUm4a5vVmcSbhdmXjbVeqMTJ9wiQkFV 0eOBNaFeRHSJxXDA0PoPNf+QVkOubUd8xLknnZudnSkBoNhQEq2+uqYA/KwxXQk4ZL ZVDDVAz7ZCQE5BEshotByCmn6XH/gvlMrrEMsTnjKi3PNGQVuNKyl3Lx9BFUGboRq3 syfLUhNenEjCQ== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v1 17/25] clk: mediatek: mt8192: Join top_adj_divs and top_muxes Date: Thu, 22 Dec 2022 12:48:49 +0100 Message-Id: <20221222114857.120060-18-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> References: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org These two are both mtk_composite arrays, one dependent on another, but that's something that the clock framework is supposed to sort out and anyway registering them separately isn't going to ease the framework's job in checking dependencies. Put the contents of top_adj_divs in top_muxes to join them together and register them in one shot. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8192.c | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index ec9dc7fe848e..702770326286 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -698,9 +698,7 @@ static struct mtk_composite top_muxes[] = { MUX(CLK_TOP_APLL_I2S7_M_SEL, "apll_i2s7_m_sel", apll_i2s_m_parents, 0x320, 23, 1), MUX(CLK_TOP_APLL_I2S8_M_SEL, "apll_i2s8_m_sel", apll_i2s_m_parents, 0x320, 24, 1), MUX(CLK_TOP_APLL_I2S9_M_SEL, "apll_i2s9_m_sel", apll_i2s_m_parents, 0x320, 25, 1), -}; - -static const struct mtk_composite top_adj_divs[] = { + /* APLL_DIV */ DIV_GATE(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll_i2s0_m_sel", 0x320, 0, 0x328, 8, 0), DIV_GATE(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll_i2s1_m_sel", 0x320, 1, 0x328, 8, 8), DIV_GATE(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll_i2s2_m_sel", 0x320, 2, 0x328, 8, 16), @@ -1099,15 +1097,10 @@ static int clk_mt8192_top_probe(struct platform_device *pdev) if (r) goto unregister_muxes; - r = mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, - &mt8192_clk_lock, top_clk_data, &pdev->dev); - if (r) - goto unregister_top_composites; - r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data, &pdev->dev); if (r) - goto unregister_adj_divs_composites; + goto unregister_top_composites; r = clk_mt8192_reg_mfg_mux_notifier(&pdev->dev, top_clk_data->hws[CLK_TOP_MFG_PLL_SEL]->clk); @@ -1119,8 +1112,6 @@ static int clk_mt8192_top_probe(struct platform_device *pdev) unregister_gates: mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data); -unregister_adj_divs_composites: - mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data); unregister_top_composites: mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), top_clk_data); unregister_muxes: From patchwork Thu Dec 22 11:48:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 636124 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6891C4167B for ; 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a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671709789; bh=BelWIyFvzZ+ppaBjnTg51Px56ewLTSYDYBP45U3epbg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d8NH4b2qx3jDGD9TmRBBAkZplqwp/uvBLCiDUxxmZ6cuBdAlWbEwmzvDr/lM4Mlul JAlRXq6d8GQ0EHfkeGygbIpIeggqQb7E7OCqCB7bOBMJZHTYB0fGSFitwVjds2vLW8 O8DcPggjiW8kZvvjNQNpZ3IJe0LrZZRekhlqXeK4vbBrfbyWfgzcFzj6gYVAtodBvt 9MYeSwDdRmsTHUriG+uMvPN1ZjATKHbUWGcg0M8turkTwPIuELF6EIKGw/0akAO15Z 8/PL144AOMXaaMn30EiWf7CrdZ5Tb+Vu7ueWl2bst20PEckkXjIBKtOM0xMg5wgWqx mM8PBBnV6MkqA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v1 20/25] clk: mediatek: clk-mtk: Register MFG notifier in mtk_clk_simple_probe() Date: Thu, 22 Dec 2022 12:48:52 +0100 Message-Id: <20221222114857.120060-21-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> References: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In preparation for commonizing topckgen probe on various MediaTek SoCs clock drivers, add the ability to register the MFG MUX notifier in mtk_clk_simple_probe() by passing a custom notifier register function pointer, as this function will be slightly different across different SoCs. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mtk.c | 8 ++++++++ drivers/clk/mediatek/clk-mtk.h | 3 +++ 2 files changed, 11 insertions(+) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index b0a6225cd7b2..df6281492fb6 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -533,6 +533,14 @@ int mtk_clk_simple_probe(struct platform_device *pdev) goto unregister_composites; } + if (mcd->clk_notifier_func) { + struct clk *mfg_mux = clk_data->hws[mcd->mfg_clk_idx]->clk; + + r = mcd->clk_notifier_func(&pdev->dev, mfg_mux); + if (r) + goto unregister_clks; + } + r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); if (r) goto unregister_clks; diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h index f49aea3fb4bd..aa4d469134d8 100644 --- a/drivers/clk/mediatek/clk-mtk.h +++ b/drivers/clk/mediatek/clk-mtk.h @@ -229,6 +229,9 @@ struct mtk_clk_desc { const struct mtk_clk_rst_desc *rst_desc; spinlock_t *clk_lock; bool shared_io; + + int (*clk_notifier_func)(struct device *dev, struct clk *clk); + unsigned int mfg_clk_idx; }; int mtk_clk_simple_probe(struct platform_device *pdev); From patchwork Thu Dec 22 11:48:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 636123 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 961A2C3DA7A for ; Thu, 22 Dec 2022 11:57:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235172AbiLVL5I (ORCPT ); Thu, 22 Dec 2022 06:57:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235723AbiLVLzh (ORCPT ); Thu, 22 Dec 2022 06:55:37 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27DE42EF81; Thu, 22 Dec 2022 03:49:51 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 40C1D6602CF8; Thu, 22 Dec 2022 11:49:49 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671709790; bh=v4bpRy6DKVod2vAuX1EyO2724COnQa/afh1pvd8ocYY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FrsQLoJofTCMYgIJrQfyPkRSDYicPjNPBtaKkJa/r8n75WbEuah3G+kP+KIMamQ4D cvQ5Znz8ycsOGwOKR04Prl57jgCHjQaHzy6Au5ixDG25y2Xt3416psh7SZ7y/auuWg 7WP8dT7jrRao8oP5+P5BQWoqk3XmIXq+pExfMGV7XiZwcehPQBVosjhlltQm+Y6bLP mOkkKTkC7iZ5IcUzEVbYKHJoc9wo6uxFUMq51iT0dDT6ZM7zKfIwl4AixgVfFerjz1 pmQjEEPGgHmg6bPwLYuuu0kNGSGYE+viCJ9guutyy7Q+Nu9V4bkKibkvry8gFoE1L9 48Y3kqNMpIMcg== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v1 21/25] clk: mediatek: clk-mt8192: Migrate topckgen to mtk_clk_simple_probe() Date: Thu, 22 Dec 2022 12:48:53 +0100 Message-Id: <20221222114857.120060-22-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> References: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since the common simple probe function for MediaTek clock drivers can now register the MFG MUX notifier, it's possible to migrate MT8192's topckgen to that, allowing for some code size reduction. Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8192.c | 80 +++++++------------------------ 1 file changed, 17 insertions(+), 63 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c index 702770326286..adde457e6277 100644 --- a/drivers/clk/mediatek/clk-mt8192.c +++ b/drivers/clk/mediatek/clk-mt8192.c @@ -1064,66 +1064,6 @@ static int clk_mt8192_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); } -static int clk_mt8192_top_probe(struct platform_device *pdev) -{ - struct device_node *node = pdev->dev.of_node; - struct clk_hw_onecell_data *top_clk_data; - int r; - void __iomem *base; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); - if (!top_clk_data) - return; - - r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data); - if (r) - return r; - - r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); - if (r) - goto unregister_fixed_clks; - - r = mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node, - &mt8192_clk_lock, top_clk_data, &pdev->dev); - if (r) - goto unregister_factors; - - r = mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8192_clk_lock, top_clk_data, &pdev->dev); - if (r) - goto unregister_muxes; - - r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), - top_clk_data, &pdev->dev); - if (r) - goto unregister_top_composites; - - r = clk_mt8192_reg_mfg_mux_notifier(&pdev->dev, - top_clk_data->hws[CLK_TOP_MFG_PLL_SEL]->clk); - if (r) - goto unregister_gates; - - return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, - top_clk_data); - -unregister_gates: - mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data); -unregister_top_composites: - mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), top_clk_data); -unregister_muxes: - mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data); -unregister_factors: - mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data); -unregister_fixed_clks: - mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - top_clk_data); - return r; -} - static int clk_mt8192_apmixed_probe(struct platform_device *pdev) { struct clk_hw_onecell_data *clk_data; @@ -1158,9 +1098,6 @@ static const struct of_device_id of_match_clk_mt8192[] = { { .compatible = "mediatek,mt8192-apmixedsys", .data = clk_mt8192_apmixed_probe, - }, { - .compatible = "mediatek,mt8192-topckgen", - .data = clk_mt8192_top_probe, }, { /* sentinel */ } @@ -1193,9 +1130,26 @@ static const struct mtk_clk_desc peri_desc = { .num_clks = ARRAY_SIZE(peri_clks), }; +static const struct mtk_clk_desc topck_desc = { + .fixed_clks = top_fixed_clks, + .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), + .factor_clks = top_divs, + .num_factor_clks = ARRAY_SIZE(top_divs), + .mux_clks = top_mtk_muxes, + .num_mux_clks = ARRAY_SIZE(top_mtk_muxes), + .composite_clks = top_muxes, + .num_composite_clks = ARRAY_SIZE(top_muxes), + .clks = top_clks, + .num_clks = ARRAY_SIZE(top_clks), + .clk_lock = &mt8192_clk_lock, + .clk_notifier_func = clk_mt8192_reg_mfg_mux_notifier, + .mfg_clk_idx = CLK_TOP_MFG_PLL_SEL, +}; + static const struct of_device_id of_match_clk_mt8192_simple[] = { { .compatible = "mediatek,mt8192-infracfg", .data = &infra_desc }, { .compatible = "mediatek,mt8192-pericfg", .data = &peri_desc }, + { .compatible = "mediatek,mt8192-topckgen", .data = &topck_desc }, { /* sentinel */ } }; From patchwork Thu Dec 22 11:48:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 636121 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5626DC4167B for ; Thu, 22 Dec 2022 11:57:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235603AbiLVL5N (ORCPT ); Thu, 22 Dec 2022 06:57:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235730AbiLVLzl (ORCPT ); Thu, 22 Dec 2022 06:55:41 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87D2A2CCBB; Thu, 22 Dec 2022 03:49:53 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E05C56602CF9; Thu, 22 Dec 2022 11:49:50 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671709792; bh=pTPLqgfggQOJQKnrG05/EFzS5SPhf9tzN93cDLVUrqk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WgdBWw6KNXZj4C0KGInjFeutYEtcSTyJn04K4LfbXMqPd7WKGon9pw7CurJdxSKRt NFxPmnqXchewQYY1tubw48ehVEDa3aGSm9r6F6vzYghk4HT/EZGnWaOsWILdO42txx iY8ZuMufo+WHd/POAeLJTmbaTEzvT5sbn6SyOc4AkMAUdq7KY9mUNehtOMOeuRkEbs dECokdz+ptJJ/7aash4kiNibuQPQElBxoCmfyF7aPWLFqCJqnIPA5xNv3P5nZsdliA QklTOXzqfNKaD5hLcVJEwe4chzmYTle1bX3aav3h7LmVvosn1egDfHEV8Iko9lu/gE UcI9l0Sx9wZVA== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v1 22/25] clk: mediatek: clk-mt8186-topckgen: Migrate to mtk_clk_simple_probe() Date: Thu, 22 Dec 2022 12:48:54 +0100 Message-Id: <20221222114857.120060-23-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> References: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As done with MT8192, migrate MT8186 topckgen away from a custom probe function and use mtk_clk_simple_{probe, remove}(). Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt8186-topckgen.c | 101 ++++----------------- 1 file changed, 19 insertions(+), 82 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt8186-topckgen.c b/drivers/clk/mediatek/clk-mt8186-topckgen.c index 63befb1f492d..0fba88adf9fa 100644 --- a/drivers/clk/mediatek/clk-mt8186-topckgen.c +++ b/drivers/clk/mediatek/clk-mt8186-topckgen.c @@ -681,11 +681,6 @@ static struct mtk_composite top_muxes[] = { 0x0320, 4, 0x0334, 8, 0), }; -static const struct of_device_id of_match_clk_mt8186_topck[] = { - { .compatible = "mediatek,mt8186-topckgen", }, - {} -}; - /* Register mux notifier for MFG mux */ static int clk_mt8186_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) { @@ -708,86 +703,28 @@ static int clk_mt8186_reg_mfg_mux_notifier(struct device *dev, struct clk *clk) return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb); } -static int clk_mt8186_topck_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - - clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK); - if (!clk_data) - return -ENOMEM; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) { - r = PTR_ERR(base); - goto free_top_data; - } - - r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - clk_data); - if (r) - goto free_top_data; - - r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - if (r) - goto unregister_fixed_clks; - - r = mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node, - &mt8186_clk_lock, clk_data, &pdev->dev); - if (r) - goto unregister_factors; - - r = mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, - &mt8186_clk_lock, clk_data, &pdev->dev); - if (r) - goto unregister_muxes; - - r = clk_mt8186_reg_mfg_mux_notifier(&pdev->dev, - clk_data->hws[CLK_TOP_MFG]->clk); - if (r) - goto unregister_composite_muxes; - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - if (r) - goto unregister_composite_muxes; - - platform_set_drvdata(pdev, clk_data); - - return r; - -unregister_composite_muxes: - mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), clk_data); -unregister_muxes: - mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), clk_data); -unregister_factors: - mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); -unregister_fixed_clks: - mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), clk_data); -free_top_data: - mtk_free_clk_data(clk_data); - return r; -} - -static int clk_mt8186_topck_remove(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev); - struct device_node *node = pdev->dev.of_node; - - of_clk_del_provider(node); - mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), clk_data); - mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), clk_data); - mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), clk_data); - mtk_free_clk_data(clk_data); +static const struct mtk_clk_desc topck_desc = { + .fixed_clks = top_fixed_clks, + .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), + .factor_clks = top_divs, + .num_factor_clks = ARRAY_SIZE(top_divs), + .mux_clks = top_mtk_muxes, + .num_mux_clks = ARRAY_SIZE(top_mtk_muxes), + .composite_clks = top_muxes, + .num_composite_clks = ARRAY_SIZE(top_muxes), + .clk_lock = &mt8186_clk_lock, + .clk_notifier_func = clk_mt8186_reg_mfg_mux_notifier, + .mfg_clk_idx = CLK_TOP_MFG, +}; - return 0; -} +static const struct of_device_id of_match_clk_mt8186_topck[] = { + { .compatible = "mediatek,mt8186-topckgen", .data = &topck_desc }, + {} +}; static struct platform_driver clk_mt8186_topck_drv = { - .probe = clk_mt8186_topck_probe, - .remove = clk_mt8186_topck_remove, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt8186-topck", .of_match_table = of_match_clk_mt8186_topck, From patchwork Thu Dec 22 11:48:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 636122 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 181D9C46467 for ; Thu, 22 Dec 2022 11:57:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235529AbiLVL5K (ORCPT ); Thu, 22 Dec 2022 06:57:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235538AbiLVLzv (ORCPT ); Thu, 22 Dec 2022 06:55:51 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F3292CCAF; Thu, 22 Dec 2022 03:49:58 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E4D816602D1D; Thu, 22 Dec 2022 11:49:55 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1671709797; bh=PXg/FppXIPAwQaA1oQS+Wf5hDsh7ZOHb0BNVjLOTW5Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=f9W6n2Y+3XLDFPStXfD7nv1eW8u2Cq6hou75Mr0KBNGbXgRhbFUvBDL0gRaXjmkg7 UMOAtHy9RpleUcKMqypwUm+7FAP+7WV94SPPDS+iflSM0R/3B0aYQ+zVzsCrD1kbCN GLQRSRhrcBvuMao4KMZkkxqhvQDXv5uRUpuNxj/JtHPg+K9qzLfeMANU/PKqlwK/IW jWq29M4zs7VdJhfxxuCcltCFciWJYoREentf1WHh1zoMt7+ZBmdnEzDUFeSiN8AEmd crxVtp/VRrYmXTljITVZtiquORGQRHUQmrruNQeeitOGEvtUI2kb2G0cp9sMJ1mkVR u8wQ8i1Fqflcw== From: AngeloGioacchino Del Regno To: mturquette@baylibre.com Cc: sboyd@kernel.org, matthias.bgg@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, wenst@chromium.org, johnson.wang@mediatek.com, miles.chen@mediatek.com, fparent@baylibre.com, chun-jie.chen@mediatek.com, sam.shih@mediatek.com, y.oudjana@protonmail.com, nfraprado@collabora.com, rex-bc.chen@mediatek.com, ryder.lee@kernel.org, daniel@makrotopia.org, jose.exposito89@gmail.com, yangyingliang@huawei.com, pablo.sun@mediatek.com, msp@baylibre.com, weiyi.lu@mediatek.com, ikjn@chromium.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com Subject: [PATCH v1 25/25] clk: mediatek: clk-mt7986-topckgen: Migrate to mtk_clk_simple_probe() Date: Thu, 22 Dec 2022 12:48:57 +0100 Message-Id: <20221222114857.120060-26-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> References: <20221222114857.120060-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There are no more non-common calls in clk_mt7986_topckgen_probe(): migrate this driver to mtk_clk_simple_probe(). Signed-off-by: AngeloGioacchino Del Regno --- drivers/clk/mediatek/clk-mt7986-topckgen.c | 52 +++++----------------- 1 file changed, 12 insertions(+), 40 deletions(-) diff --git a/drivers/clk/mediatek/clk-mt7986-topckgen.c b/drivers/clk/mediatek/clk-mt7986-topckgen.c index bf3088e6d9e3..286418aa00a0 100644 --- a/drivers/clk/mediatek/clk-mt7986-topckgen.c +++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c @@ -290,52 +290,24 @@ static const struct mtk_mux top_muxes[] = { 0x1C4, 5), }; -static int clk_mt7986_topckgen_probe(struct platform_device *pdev) -{ - struct clk_hw_onecell_data *clk_data; - struct device_node *node = pdev->dev.of_node; - int r; - void __iomem *base; - int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) + - ARRAY_SIZE(top_muxes); - - base = of_iomap(node, 0); - if (!base) { - pr_err("%s(): ioremap failed\n", __func__); - return -ENOMEM; - } - - clk_data = mtk_alloc_clk_data(nr); - if (!clk_data) - return -ENOMEM; - - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), - clk_data); - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data); - mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node, - &mt7986_clk_lock, clk_data, &pdev->dev); - - r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data); - - if (r) { - pr_err("%s(): could not register clock provider: %d\n", - __func__, r); - goto free_topckgen_data; - } - return r; - -free_topckgen_data: - mtk_free_clk_data(clk_data); - return r; -} +static const struct mtk_clk_desc topck_desc = { + .fixed_clks = top_fixed_clks, + .num_fixed_clks = ARRAY_SIZE(top_fixed_clks), + .factor_clks = top_divs, + .num_factor_clks = ARRAY_SIZE(top_divs), + .mux_clks = top_muxes, + .num_mux_clks = ARRAY_SIZE(top_muxes), + .clk_lock = &mt7986_clk_lock, +}; static const struct of_device_id of_match_clk_mt7986_topckgen[] = { - { .compatible = "mediatek,mt7986-topckgen", }, + { .compatible = "mediatek,mt7986-topckgen", .data = &topck_desc }, {} }; static struct platform_driver clk_mt7986_topckgen_drv = { - .probe = clk_mt7986_topckgen_probe, + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, .driver = { .name = "clk-mt7986-topckgen", .of_match_table = of_match_clk_mt7986_topckgen,