From patchwork Thu Dec 22 13:16:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 636035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83D30C4167B for ; Thu, 22 Dec 2022 13:17:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235527AbiLVNRt (ORCPT ); Thu, 22 Dec 2022 08:17:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235494AbiLVNRg (ORCPT ); Thu, 22 Dec 2022 08:17:36 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2176D2B25B for ; Thu, 22 Dec 2022 05:17:35 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id gt4so1895334pjb.1 for ; Thu, 22 Dec 2022 05:17:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=USFa3vv6r3M6at72+GYbrAEuQqTIcmw3cLL2W4/Vhuk=; b=n7aSVFF/XLTOv6FrKLmFAXkYEpQlwu5xvBMfaF/KeAVsnD9B8sRvW9jIGMlI4kpfRZ 29+RZt6RYVECcvyqzdWeS73J0pFr2puJUtokcq7CF/XJ69QKKTNErmZGJQzvpJTJ6mqb Or8YsDrbocMGp1YqlXneOKPUvl6U+gm52uBmOgqGsWrbf5SiQ3GQt37FYDlgdm3Rr8ti CWODXN45P21Bz27lpM4J28cV/oZwZTii4DfUqC6VWkM6ZREGXiGBYAaKuSusRxcU2o9z xzQnWFnf9mHmiMEFyQWnBxVJj8AX6axnfsKJDtpMWTlRngoszvw/uSNiLa+LghTniuiA L1Zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=USFa3vv6r3M6at72+GYbrAEuQqTIcmw3cLL2W4/Vhuk=; b=rAZ/bVY8NiQrC+vRJbW4A70j3YPh+TFIAFg7SKG7BWFhgqrj1PAJ11QZVHmpU4OjqL LvVVq1cL8WJx1yj34XlKuVaiCHq2iWkPSAYQX88tKXimKbPYf3iMk7YKdgvginPugBP/ Y1TBlw7PO0TGgqdTY56Q0HWjBJNlWD1PdhxXUNsCyl/fAROXi6J1sUKv+i5lAbRX3s9L qzxHc8DMQddMzEn0ZZbKKz3ovKklFIZ8Nnz0QN1UhagUXHVYrca87RERhP43DuHiQ/a8 fviiW87m3m+GMMdHwbnSDwIEBztVHVDhCjWDUFGn+BxXU1QcQnU2g526suBqhOZWJ0o6 MEYQ== X-Gm-Message-State: AFqh2komop5/Svfr9gCNR2P3D9NyvM+iHO+/8eLvWZumGwcD5uvQ2Tvc 1mSGczq2UjTumR74r/hV6PsR X-Google-Smtp-Source: AMrXdXuQ+EqK/3gOMscN/wnCEi/fM+XH7w5vmRz7TDRzrianSyLuaXhMJIDGmfkpZ0U2BhNZdDDBgw== X-Received: by 2002:a05:6a20:a6a8:b0:9d:efd3:66bf with SMTP id ba40-20020a056a20a6a800b0009defd366bfmr7065991pzb.6.1671715054802; Thu, 22 Dec 2022 05:17:34 -0800 (PST) Received: from localhost.localdomain ([117.217.177.99]) by smtp.gmail.com with ESMTPSA id g12-20020a170902fe0c00b001896040022asm491570plj.190.2022.12.22.05.17.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 05:17:33 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam , Krzysztof Kozlowski Subject: [PATCH v4 01/16] dt-bindings: arm: msm: Update the maintainers for LLCC Date: Thu, 22 Dec 2022 18:46:41 +0530 Message-Id: <20221222131656.49584-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> References: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rishabh Bhatnagar has left Qualcomm, and there is no evidence of him maintaining with a new identity. So his entry needs to be removed. Also, Sai Prakash Ranjan's email address should be updated to use quicinc domain. Cc: Sai Prakash Ranjan Acked-by: Sai Prakash Ranjan Acked-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 38efcad56dbd..d1df49ffcc1b 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Last Level Cache Controller maintainers: - - Rishabh Bhatnagar - - Sai Prakash Ranjan + - Sai Prakash Ranjan description: | LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, From patchwork Thu Dec 22 13:16:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 636395 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E096AC001B2 for ; Thu, 22 Dec 2022 13:18:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235650AbiLVNSP (ORCPT ); Thu, 22 Dec 2022 08:18:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235552AbiLVNRv (ORCPT ); Thu, 22 Dec 2022 08:17:51 -0500 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE16F2B602 for ; Thu, 22 Dec 2022 05:17:42 -0800 (PST) Received: by mail-pj1-x1030.google.com with SMTP id o1-20020a17090a678100b00219cf69e5f0so5686251pjj.2 for ; Thu, 22 Dec 2022 05:17:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Bp5/r4pBB7Qfe42Kb/SOy1gZ4/1fvqqZd0eC3Bvgy/g=; b=d9BHDr+PPsP+TSxNM0CJCIKo120fJMIwSZS2m3BjHORr7CsHkePASymtvGUYq1l26s e2NehLvgfNB2lCBjW2Cp3xzQqtqN5EgUPxl3oz3bBZQayLBdX9W6TDBvkEy6myiFB8Xb o5b2OzN5eIGZCA6Z85W7H8uvFBNNRNfbjJiBUMyN0fTXNVx0+8TRLcvgsq0HXosY0meT gHvTlOsPZIA3Xkt4gmBlmcPyOk0HLziwmQggcZTCtYYbdroLxyULzVnZzsAoN4Si7s/K tdXvty4i4Zt8tWrce/NkQkCRxgxgXYXRJ1tlOpJ79I7q8TegUQ2fgUslis3r5MSGNuA0 nrQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Bp5/r4pBB7Qfe42Kb/SOy1gZ4/1fvqqZd0eC3Bvgy/g=; b=rKs8wYSov29t8icypyIM2j11shmR+ZBc6WwszkhN9+lt9fk3rzJn1A/7tNMSOl6MpU ThXG4FAEBDcAFKrwkvekYoyfxlh+yYuuSqp98YSzJ0iCMM2bH6f6m0N0fAqUgxyJNRtY 8fB0Gw97ijtKamgcdPlcb3gH1HVk+NnU1i9ScrzArLKnA6EWFPPCX7iMg1K4wM4elE6j 0z7Tbl1Xz8txh9CHI+JttUs+1MHhlbMdGL6zaaOoevYAf21iYAkHNg7WTBuyHU07+UhG XJY5xVCj2Xhiqe1JLB1eCBiwM1aFKB1aj/YoP5Vv3dMh3xGfFGfp4TnTkMbwzpDVpGF5 s6mg== X-Gm-Message-State: AFqh2kpjTEICpQRCvR3/2wC8wiFvT7fu7iDppQuMBdQ15CxKGSUP/MDJ b2ueajW5uZLnPs7HTcYP7JP+ X-Google-Smtp-Source: AMrXdXsQhOnQuBfMe9o2xBz7j7/zdg6xem8ycEmxGz9ThgatyoZwCGcCPjtTrgEvSDBztznOKlPJQw== X-Received: by 2002:a17:903:2444:b0:190:f82f:c937 with SMTP id l4-20020a170903244400b00190f82fc937mr8523352pls.42.1671715062372; Thu, 22 Dec 2022 05:17:42 -0800 (PST) Received: from localhost.localdomain ([117.217.177.99]) by smtp.gmail.com with ESMTPSA id g12-20020a170902fe0c00b001896040022asm491570plj.190.2022.12.22.05.17.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 05:17:41 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v4 02/16] dt-bindings: arm: msm: Fix register regions used for LLCC banks Date: Thu, 22 Dec 2022 18:46:42 +0530 Message-Id: <20221222131656.49584-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> References: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register regions of the LLCC banks are located at different addresses. Currently, the binding just lists the LLCC0 base address and tries to cover all the banks using a single size. This is entirely wrong as there are other register regions that happen to lie inside the size covered by the binding such as the memory controller and holes. So this needs to be fixed by specifying the base address of individual LLCC banks. This approach will break the existing users of this binding as the register regions are splitted and the drivers now cannot use LLCC0 register region for accessing rest of the banks (which is wrong anyway). But considering the fact that the binding was wrong from the day one and also the device drivers going wrong by the binding, this breakage is acceptable. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski --- .../bindings/arm/msm/qcom,llcc.yaml | 125 ++++++++++++++++-- 1 file changed, 114 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index d1df49ffcc1b..050e21d4a03e 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -33,14 +33,12 @@ properties: - qcom,sm8550-llcc reg: - items: - - description: LLCC base register region - - description: LLCC broadcast base register region + minItems: 2 + maxItems: 9 reg-names: - items: - - const: llcc_base - - const: llcc_broadcast_base + minItems: 2 + maxItems: 9 interrupts: maxItems: 1 @@ -50,15 +48,120 @@ required: - reg - reg-names +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-llcc + - qcom,sm6350-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC6 base register region + - description: LLCC7 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc4_base + - const: llcc5_base + - const: llcc6_base + - const: llcc7_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-llcc + - qcom,sm8150-llcc + - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc_broadcast_base + additionalProperties: false examples: - | #include - system-cache-controller@1100000 { - compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; + soc { + #address-cells = <2>; + #size-cells = <2>; + + system-cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; + interrupts = ; + }; }; From patchwork Thu Dec 22 13:16:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 636034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BAC5C4167B for ; Thu, 22 Dec 2022 13:18:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235456AbiLVNSc (ORCPT ); Thu, 22 Dec 2022 08:18:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235519AbiLVNSF (ORCPT ); Thu, 22 Dec 2022 08:18:05 -0500 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 596522B252 for ; Thu, 22 Dec 2022 05:17:50 -0800 (PST) Received: by mail-pj1-x1032.google.com with SMTP id hd14-20020a17090b458e00b0021909875bccso5619986pjb.1 for ; Thu, 22 Dec 2022 05:17:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ny8LRDxtkCbzVPxZcMEK/2xCa3Cj3hxgheO6Po9c4/Y=; b=dhMQGBmR06G9CatEmwe+v1F0+trf5UQoHfDvkucAjtc26GNdGjq0Mmqd3P8/l8e2lK j786FeOg6gLzai89na4eEqUrq5EPxCmKugelr6TGJ4doyO0njRznbdKs31Jc1oVwXTRb A1rZaEsO9STSnQ6vC6bpfPiDtyKFXi+Amq7vxoqvJNgEBx9agHOu3jd2Vt66p10rFzXL 816uQsS0YIusOOBr1wkkbgCudts0SFCyXkBtNRn0J/bRIoqRw4ocVVUOrii7XrWZF+EV ZAWISg78ZvUvnApxbF+wnyadkb8QLFGVE7v7tScsnKYkBnUVUhrE3S7t2oUpLJFbEa9+ AYJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ny8LRDxtkCbzVPxZcMEK/2xCa3Cj3hxgheO6Po9c4/Y=; b=PPkVKB1FGcdTIjY72rGNiYqaXMHrLUnALbGibJPQupEiyU4CF1Q0Ads6tq/4jAmR6J 1G/2u2eT4HgsUnyM0xrKl77BIKEFSsag08ZJTeCMvozoCdx9zczSENFr3nn25HdlDoB7 asVRz59TzokyobF9t7A7cXsiuFybuwuevZGDeJfCh4wycD5REy5SbnPw2Hpxb6mU23GQ DpDrOxfT4cL1yb8T1q5KGaV8ztfJ2G11kF/+9jr3c8HqF60s5K7wRwZJGqEYYIgxVygl Q14bwVqavW7bzJBYyw+6OEqTj4aDkcawBebX7AcAR5YKAXljVojeck6p6t+tFv/Nz4Oi MYGA== X-Gm-Message-State: AFqh2koBKjqe7bMfC8Dqq3kABmbWFPOsPEy/ee5WjYTo58icMiJiPBjx pWx+IQ0p7RgxtfN3movEybZj X-Google-Smtp-Source: AMrXdXtdlLhBbT/Lo06+N7ABRxG2EOW4Dg+4lppus3WpcowYBMBT8zKC6wfC2dxBDs+Sr7SmovSWNQ== X-Received: by 2002:a17:903:10c:b0:192:5838:afaa with SMTP id y12-20020a170903010c00b001925838afaamr621172plc.25.1671715069820; Thu, 22 Dec 2022 05:17:49 -0800 (PST) Received: from localhost.localdomain ([117.217.177.99]) by smtp.gmail.com with ESMTPSA id g12-20020a170902fe0c00b001896040022asm491570plj.190.2022.12.22.05.17.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 05:17:48 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v4 03/16] arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks Date: Thu, 22 Dec 2022 18:46:43 +0530 Message-Id: <20221222131656.49584-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> References: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 65032b94b46d..e1c0d9faf46e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2132,8 +2132,11 @@ uart15: serial@a9c000 { llcc: system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; - reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Thu Dec 22 13:16:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 636394 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14AF0C4332F for ; Thu, 22 Dec 2022 13:18:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235512AbiLVNSn (ORCPT ); Thu, 22 Dec 2022 08:18:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235616AbiLVNSJ (ORCPT ); Thu, 22 Dec 2022 08:18:09 -0500 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7E8982B635 for ; Thu, 22 Dec 2022 05:17:57 -0800 (PST) Received: by mail-pl1-x62b.google.com with SMTP id jn22so1955069plb.13 for ; Thu, 22 Dec 2022 05:17:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4GFA6I79C1YmmOYQX1BIX7MOGuUjMMgmSjlJ7uhFCjc=; b=KyqAKH9suEnSST6nGHfrF6tiq5gOyxJrohsSocczxR2yYtSwc4itB7Rwfc7SH8NQLf BOPZJAR/M5OHetigMOlkHgsIEqWFC+GZdcpTBQGve1FYMPv1J3bDllxaG/kYFe48R3kZ rkszrwUINRgXb7Td2fzluU97ArKf/8mB1NDMjLIUKHoEEbIeT8GPsj8E4Ny3qEZBPheS uYLvV3c5hS6z+vjOmzfvNLSasQIo7ZLkLBKmN+fyEWCGfW90yyMw9m4HJgs6DIfQhYWn JzXWbNAb3RUKYta7ThAlAjFkiNAyQDrz5AndikCMq+Mdx+pYaM3bf4ikeORkaz/Rfb+k eOUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4GFA6I79C1YmmOYQX1BIX7MOGuUjMMgmSjlJ7uhFCjc=; b=4PDPb9E2qtIwlSDvrHGZldgyu6DQKiMpfpk0hrjE2ces4WqNbue8vEohnzQq8x26wc nZLP8yjgncLCoeD9AwuVHglq3zbhFz4KKUQj/fNEC4FOpoEemL7qwHtyWR6SJKt4vy0I h2Zj56a+4eyv49mP+DL3dIU8PzcTO1PzuiMimSAFoWwsxjS5u6iV4QJczSb3JcxRlZHw whaYZ4iTb6hq9/OvghdqQlAPtsm8P8BnEIZnlHiGY+OMyqtMO2nX8DiAVD+OZrN1ASsu PNbVC9Xu0jwaDGrPGFoERRjYbV32dApVtXARhylJvfEAkj9BJKwZNDozETozQBhnw3Qi Ah1w== X-Gm-Message-State: AFqh2kpEVUmua8UezU5jv9SnZ98mkuFWqUgjYzIwMK6ihCvkyeaQgBln JFCJnyUcych/fFzTGlI2w/u6 X-Google-Smtp-Source: AMrXdXsatbDMtdO3R2ucECYmD9QW413oKPw0txMOMDN+VIJ/fone11nOH6I7fduVKUAJ3Wo/Y3UYXg== X-Received: by 2002:a17:903:228a:b0:191:217f:b2ea with SMTP id b10-20020a170903228a00b00191217fb2eamr8592642plh.40.1671715077246; Thu, 22 Dec 2022 05:17:57 -0800 (PST) Received: from localhost.localdomain ([117.217.177.99]) by smtp.gmail.com with ESMTPSA id g12-20020a170902fe0c00b001896040022asm491570plj.190.2022.12.22.05.17.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 05:17:56 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v4 04/16] arm64: dts: qcom: sc7180: Fix the base addresses of LLCC banks Date: Thu, 22 Dec 2022 18:46:44 +0530 Message-Id: <20221222131656.49584-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> References: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SC7180, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index f71cf21a8dd8..f861f692c9b1 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2759,7 +2759,7 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible = "qcom,sc7180-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg-names = "llcc0_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Thu Dec 22 13:16:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 636033 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5D4BC4167B for ; Thu, 22 Dec 2022 13:18:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235519AbiLVNSs (ORCPT ); Thu, 22 Dec 2022 08:18:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235633AbiLVNSP (ORCPT ); Thu, 22 Dec 2022 08:18:15 -0500 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A75C2B265 for ; Thu, 22 Dec 2022 05:18:05 -0800 (PST) Received: by mail-pj1-x1031.google.com with SMTP id z8-20020a17090abd8800b00219ed30ce47so5669732pjr.3 for ; Thu, 22 Dec 2022 05:18:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u3b0H9FlwI0cHeu/QvvhJdFruV0iaHa3piiWtATy1Lw=; b=gnByMWDrv/Lg6BTxLAdidhvjUtHGpWOlSVTpQZb/yNKi+IGyo2ix5/CLp/zvC2ezgX rLHDsvBolhEvXSgcaskguoAus95ifGJXB5dvp0tClVHYI1SwNTh6csg8ZGj/AgDBDfnD GV9jil3DlgWv8YzUfXAqtFLYxwRyQAuaYTOe0iyvbrxqiw1IFa5qbluv1NBOanOZpjlW JH4YTwUoUBAI/OEVyu9NAGYXEYPiDIxk2HhbOS07yrD1Jt5PdR7LnvOi1XAIychU4jTD ZHcmcfxg13p3exaHU/ek4vNSsAVLnbNc+lLw/UnxcnnXKst8AQQaSQwR6Do6ACZdgSQ7 h9cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u3b0H9FlwI0cHeu/QvvhJdFruV0iaHa3piiWtATy1Lw=; b=cvAOt3XRb+3QzVMLuINjlTnuZQ+hLKauFs+rT6amazFLxkPd9VgVQbPWvnuodW5nLb hE0e5DdOWlgw5dIgiAhMFwGCVL3WhCVOeFOPNy84iZ9wuNW96kWhRWo0UCT1QdQMIAID u+wtBWG+d/IrzFr1ezZytOWEvSw5AleNYlbvzAJ32v/PXoRPjC6ZUvsOAMIRs2t7BWex oZYaMn13/hspcOF0jn66B8lPSRLWJ8nOo89BENT8Pis6D+ZPxDuKqZIyDJDHNffFchpt Z0/pcXXTUsJKWB6LbpqN6oTGxUfgXOxAgish21AHJ0CZ8McAmzLAfArh0bYR/OUJjhjZ NmEA== X-Gm-Message-State: AFqh2krsuovONoS8MwgvzOyMU7/TWmp35vWEHxkOJouoPjfM5sSqSrTf iPIQj3Hx2cSWmWoM8kcH7Vj0 X-Google-Smtp-Source: AMrXdXt1JcCCvNMmg+NUKFmQ0qTatt0gElq/BF6S/H778bnu/MoF9dptpCELzd8BTBoKEofmZwedjQ== X-Received: by 2002:a17:902:f68a:b0:192:49f4:fe67 with SMTP id l10-20020a170902f68a00b0019249f4fe67mr7323465plg.57.1671715084787; Thu, 22 Dec 2022 05:18:04 -0800 (PST) Received: from localhost.localdomain ([117.217.177.99]) by smtp.gmail.com with ESMTPSA id g12-20020a170902fe0c00b001896040022asm491570plj.190.2022.12.22.05.17.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 05:18:03 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v4 05/16] arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks Date: Thu, 22 Dec 2022 18:46:45 +0530 Message-Id: <20221222131656.49584-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> References: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. While at it, let's also fix the size of the llcc_broadcast_base to cover the whole region. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0adf13399e64..6c6eb6f4f650 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3579,8 +3579,9 @@ gem_noc: interconnect@9100000 { system-cache-controller@9200000 { compatible = "qcom,sc7280-llcc"; - reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Thu Dec 22 13:16:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 636031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68637C10F1D for ; Thu, 22 Dec 2022 13:19:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234764AbiLVNS7 (ORCPT ); Thu, 22 Dec 2022 08:18:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48256 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235564AbiLVNSP (ORCPT ); Thu, 22 Dec 2022 08:18:15 -0500 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1CF72A53F for ; Thu, 22 Dec 2022 05:18:12 -0800 (PST) Received: by mail-pj1-x1033.google.com with SMTP id gv5-20020a17090b11c500b00223f01c73c3so5449458pjb.0 for ; Thu, 22 Dec 2022 05:18:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TVKI7LzAkCeTNtN2kaZFbBM4yejfzWbEhk9TFnMYwYw=; b=P/a+54AgWuWXtmXW0Z8O+Z4jquZ6bjEQJYCos8CoZuhMjjTvnXhIYgjxuOmTDy32+0 Kcr+bf3cXzVpz9f0cNhNz/XK2mJRqFhb1uSe9ZDqO/Z3IVIFE9RvTyqCTE0nHnin1tdz a8mBSs5XShG3YBkdgOSM7by4y/YzeqUpy5K0woYBdRb4acljtFdA9F74/EcYgA/MWG+l aJNv0vt9pbz9yv+E40Z+1sk6Asiw1AtA/rjyJEIC0IDakCNR6RHh/T1mJvjN3o4rl858 F7SBp6WCIfiB74jDKsSSwH0bAyQbK7VRJ/cv+1f7WQP2u8IkfsvgrYjIpAgkl+oGA0fo x64Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TVKI7LzAkCeTNtN2kaZFbBM4yejfzWbEhk9TFnMYwYw=; b=SfI7BmQ9LcUvL0zmUuHG3Wc9xqqsbbkM/v/gNf8LbB4N973aKjaDsk72+D1Nv7zSVo X94CS0SMeJXo9UF/W1DUGDfuY4+xg0b48IYE3LUKyU6YzMCn7a5z9XRHYGui4VJlQD83 xMxQlWR+4SM1VPLALlMpcslqttRnoplJ+k5BqagJv7Oo12W6Y+LDliHhgkJ3Vl9sVE2r tyoGS23FF9YCqNJg2gbYU8G1DQjVG0B5s2+pf2E3r6aMqJVzDGDlJNzH821/mWx5Pcc2 wr2rxOGlQoKdB83rDR+vTWMNHdxR/LM4UY7jZrZx+Uw3ko5KQiff/xG5LeIKm9pEsVgh Gg+Q== X-Gm-Message-State: AFqh2kpKIcJb84LBcVqSyasGF/QVtiHH8YbP/21Wl4r8Md51XSmDvwbK puMLvAjP4reTXxDLppzWy/ZU X-Google-Smtp-Source: AMrXdXs6GKa04tnmCrRCU9GMOUViTkmcx9NG4nUPCgprwzoRazOPtkyIpmoTMBILt/ItUkBQxGc6zw== X-Received: by 2002:a17:903:210b:b0:18f:aca1:b0c9 with SMTP id o11-20020a170903210b00b0018faca1b0c9mr5058479ple.53.1671715092349; Thu, 22 Dec 2022 05:18:12 -0800 (PST) Received: from localhost.localdomain ([117.217.177.99]) by smtp.gmail.com with ESMTPSA id g12-20020a170902fe0c00b001896040022asm491570plj.190.2022.12.22.05.18.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 05:18:11 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v4 06/16] arm64: dts: qcom: sc8280xp: Fix the base addresses of LLCC banks Date: Thu, 22 Dec 2022 18:46:46 +0530 Message-Id: <20221222131656.49584-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> References: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 109c9d2b684d..0510a5d510e7 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -1856,8 +1856,14 @@ opp-6 { system-cache-controller@9200000 { compatible = "qcom,sc8280xp-llcc"; - reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, + <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc4_base", "llcc5_base", + "llcc6_base", "llcc7_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Thu Dec 22 13:16:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 636392 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43C9EC3DA7C for ; Thu, 22 Dec 2022 13:19:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235432AbiLVNS6 (ORCPT ); Thu, 22 Dec 2022 08:18:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48510 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235558AbiLVNSU (ORCPT ); Thu, 22 Dec 2022 08:18:20 -0500 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8A302B279 for ; Thu, 22 Dec 2022 05:18:19 -0800 (PST) Received: by mail-pj1-x1031.google.com with SMTP id z8-20020a17090abd8800b00219ed30ce47so5670395pjr.3 for ; Thu, 22 Dec 2022 05:18:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7WUljA05hxjrMgWInu+aANTEuP2TXhzChwqlFzG2wks=; b=C6UEEu2cv9HWmh2bzqVBHeQNYzwhh1L9U41oaFA6os6JZIvt0qOms7EsWan5cEV7G8 qsqXREDB3CHZbzOCiJBLqi+fXZTtfzBsk4cLkQLICCPN5ELJM2O4eZQdxJnKWrWekIrG Cdl+6PhS6yrwZoCPgec0sAfNU/Lz4Z9OaL1GXz+MgxOIgxkIL5pIC2dRDIATEQyzfuq3 +D9Ep3r9hv4cZKTwNmtK+WPgoD6mU32mkblcraTyNqu1woMe80CkJJt95f0Gdt2fFgvO qHQHrtlUG1k8WwTDlZWoj8h16PiKr9rqRyymr04KacTDb2OIZuTjTbLumfQvjQ/wuJOU slPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7WUljA05hxjrMgWInu+aANTEuP2TXhzChwqlFzG2wks=; b=6bKqmc94M50TYrt31Xa3miCV6x+P2QCtoJtgFdeLj7utymz0AyMCWk57Vl6oIOZMUE m2N/v3mms2oPkW9IjbT//U3IrKxP0ELl6Q5UzTzoQhcQWXYmiL6jDEbLXofxCXieTbQU WwabOi2KQKSG6VD/gOb2xw4Nwfn9AtDkqqAaaaXWDCqO9n+ZGo3Nsonj8DfR2cZtNr3v 3CoxnCgQCM0k2FMwpp19JU08kDRgLmIzo7NtPwlukUuIrL3Ea3bWD6za8t4vpCTvz7of XeONk/bNxZWtkywE/FlCfPOKBoudz+My5viEBRd4ybn5szomV72UXirk1l0uB1Qoi638 Xc2Q== X-Gm-Message-State: AFqh2krs0CM4IQzudndzJr2Msh7QWCJfTfZ+KZQauG2mZsvQ8X44YRP9 LE+s39ogR2wYz4RU9eMtNAeq X-Google-Smtp-Source: AMrXdXsCzWm9VWW8TILq8RHEyV9mJ8/MU3x52JiKXifwS6CTKL1XVbjr8B9n0QsLNCyD0eS8wukUMQ== X-Received: by 2002:a17:902:c612:b0:192:511e:b9ab with SMTP id r18-20020a170902c61200b00192511eb9abmr3162310plr.21.1671715099601; Thu, 22 Dec 2022 05:18:19 -0800 (PST) Received: from localhost.localdomain ([117.217.177.99]) by smtp.gmail.com with ESMTPSA id g12-20020a170902fe0c00b001896040022asm491570plj.190.2022.12.22.05.18.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 05:18:18 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v4 07/16] arm64: dts: qcom: sm8150: Fix the base addresses of LLCC banks Date: Thu, 22 Dec 2022 18:46:47 +0530 Message-Id: <20221222131656.49584-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> References: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a0c57fb798d3..7fd2291b2638 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1762,8 +1762,11 @@ mmss_noc: interconnect@1740000 { system-cache-controller@9200000 { compatible = "qcom,sm8150-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Thu Dec 22 13:16:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 636032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46294C10F1D for ; Thu, 22 Dec 2022 13:18:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235371AbiLVNSz (ORCPT ); Thu, 22 Dec 2022 08:18:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235397AbiLVNS2 (ORCPT ); Thu, 22 Dec 2022 08:18:28 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D1E12B603 for ; Thu, 22 Dec 2022 05:18:27 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id x3so1875144pjv.4 for ; Thu, 22 Dec 2022 05:18:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WYoJy3okzdnngL6TcLmeGykcAQcBXE1fb+mKXu1bB1c=; b=ZtQ5aYt6JszkNCc6c+71vylemy82zpImGkRGBLjyDIYf900tOPtXU155alWvES6I1M iN33nGCpROLkAWz2iuohHqj0WGMRtqHS9xDzku9mG2s9eEQkt4khJBVbQ3qq3b4HOA6l R3OiuzxM8jBtFr4UDlvK6L1wOV6uTgeCQlEU6XYG7D0VC2AmlsmzQuN+5VwkKXZ0CLoF K95z38wHmzOT7Vbkjk4Z6BmrLHVQnNZCMcX0kdRG0L5JmGdSFrmd2YFdwz0FVzttv0/l 4LLt67WOyGy9V4XDggSgZXyDOflfPKYJR/YGUYQ9EeVBtidNSLZOUhCuupf7w9zw3Q60 VOwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WYoJy3okzdnngL6TcLmeGykcAQcBXE1fb+mKXu1bB1c=; b=kkQHGa3+zhQyuTuJUF0CGnr5m657JKag/M2dKgJh0HKMlFbeAgsB/1OrvHuTnfKifv CjrtPYo+q/7z3ggnNnUGFx0PQG+0A+rnANm8AAIYJovkagZ3WIIW6ydri404XfyWmGeg A1O2clKBdCxJLTpFLGy3LOZL1laoclyTJ2Tlpv7qqVDPbYyR/ycTT2z3JT22YwMQLdxE Xey+YtxprSoUAreK8tnXJp4q5YaJ4lNmRSLD9J0kvKYv9AY4n/vGfZGNIKucipgPr07Z 7GLth1NU04n8ACpzZ1R8V8th6RFfPBKwFtrrSBnlNWZIHiqbOtOPnTe38xhPwEyQxACD 4xrA== X-Gm-Message-State: AFqh2koMlv4f+e6flovSJGT5Tp6NQhbzN7Hz5WaQAbyHueH16kvIu/YP 1a6s2M4QHH4pXu17X4MRYlrY X-Google-Smtp-Source: AMrXdXuQk5bFXwNnUxnhWo5QLTtJciBLJW9VKkXjO0jzujbPw/eVGhVOUzd7gxx0E69pxZ8/u3ZH1A== X-Received: by 2002:a17:902:edc3:b0:189:5ef4:6ae9 with SMTP id q3-20020a170902edc300b001895ef46ae9mr5194255plk.45.1671715106651; Thu, 22 Dec 2022 05:18:26 -0800 (PST) Received: from localhost.localdomain ([117.217.177.99]) by smtp.gmail.com with ESMTPSA id g12-20020a170902fe0c00b001896040022asm491570plj.190.2022.12.22.05.18.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 05:18:25 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v4 08/16] arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banks Date: Thu, 22 Dec 2022 18:46:48 +0530 Message-Id: <20221222131656.49584-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> References: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index dab5579946f3..d1b65fb3f3f3 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3545,8 +3545,11 @@ usb_1_dwc3: usb@a600000 { system-cache-controller@9200000 { compatible = "qcom,sm8250-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; usb_2: usb@a8f8800 { From patchwork Thu Dec 22 13:16:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 636393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 461EAC4332F for ; Thu, 22 Dec 2022 13:18:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235212AbiLVNSz (ORCPT ); Thu, 22 Dec 2022 08:18:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235494AbiLVNSi (ORCPT ); Thu, 22 Dec 2022 08:18:38 -0500 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AABCB2B24E for ; Thu, 22 Dec 2022 05:18:34 -0800 (PST) Received: by mail-pj1-x1036.google.com with SMTP id n65-20020a17090a2cc700b0021bc5ef7a14so1870622pjd.0 for ; Thu, 22 Dec 2022 05:18:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sMev9I+ZdryrTBjzJ8tiTgJp1UwzDLK7UbgCFoQvzyA=; b=VBdAGtoyo4j2LV+Tuat5GuV++N4ZltEQvbVJe/poeH/NKjLl8sIWRKaOEc0HxyfGjN UccwIuH5LaAQZeB/Hg1/z7ge75Rjtqf9bB9xPhz5X2Wvg3XpryO5sLq/SyYjDGGGI1v4 xNnQrbrnvGj8aku4FvL2Rp+CTFHcygeeiEYNG+FdqxxEak8M5JLLQAHJYYwMi5OHqu1Y kXVHR5fqO4ID2ul360A76+i81odlQh/l5Wl7HSVBCW04bgaRRZhABkoQiLbnNIwAyGUT IMFojxCV4ih5FFAeWNZZ461ke5qd3NAp4l/qjaaJWJb5BXAHAx+5GYEM6wkHC6e8657J Pr5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sMev9I+ZdryrTBjzJ8tiTgJp1UwzDLK7UbgCFoQvzyA=; b=qc8C/5Ha9O4ieb/BEhCzlgSSpfG+NYmCj6r5GfQqLdYuDdEMH1E3BFisN4GX++LWjw rGLZiu2ZayPK9ujrMGTBN/lI+wX3Q6iHOMbapGvSZb+poiABsfCoi3pwWWYs8NkzX5eO RwnrBNmaHPh1U1rQdzvxJynv0nCFx7ShOkfmLKoQRhCuZvYQB8HRWkxbybAdQ5zLSsUa Of3n5I8o7/qbo0XLbjospRtkLq52djMuVvLP/og1lg6EgDhrnUXUuIsVIdIrXjiV0RiX W/zF3WIt8MsQXqV0XmqN0nx7iAntcOVhDBAcG/SLh7I3SsbF1XlaLABiSWkcFPR4IrBJ 8pow== X-Gm-Message-State: AFqh2kr6PUZfXrz+6iIxVEY5/9IrFVwH3juNKCaVc1SmHmZde94dL61q qEgRVvxQLRU1BYHBGu+Awgn9y6OgZ9EVs+E= X-Google-Smtp-Source: AMrXdXu1dtDcszvkCZLB22zWl7tN5MHyoiGrt+aug72V2pxhYmajpVvfW98nW284frJHcPzzW0ASag== X-Received: by 2002:a17:902:8c90:b0:189:9fb2:255a with SMTP id t16-20020a1709028c9000b001899fb2255amr21318128plo.19.1671715114125; Thu, 22 Dec 2022 05:18:34 -0800 (PST) Received: from localhost.localdomain ([117.217.177.99]) by smtp.gmail.com with ESMTPSA id g12-20020a170902fe0c00b001896040022asm491570plj.190.2022.12.22.05.18.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 05:18:33 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v4 09/16] arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks Date: Thu, 22 Dec 2022 18:46:49 +0530 Message-Id: <20221222131656.49584-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> References: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 245dce24ec59..836732d16635 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2513,8 +2513,11 @@ gem_noc: interconnect@9100000 { system-cache-controller@9200000 { compatible = "qcom,sm8350-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; usb_1: usb@a6f8800 { From patchwork Thu Dec 22 13:16:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 636391 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8198AC4332F for ; Thu, 22 Dec 2022 13:19:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229962AbiLVNTD (ORCPT ); Thu, 22 Dec 2022 08:19:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235516AbiLVNSo (ORCPT ); Thu, 22 Dec 2022 08:18:44 -0500 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 213772B260 for ; Thu, 22 Dec 2022 05:18:42 -0800 (PST) Received: by mail-pj1-x1030.google.com with SMTP id o31-20020a17090a0a2200b00223fedffb30so1827741pjo.3 for ; Thu, 22 Dec 2022 05:18:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u6zR8ugZMMSbsUYzZxGLGG2mvpL7z7iHt3BZjr/IYFc=; b=fHwgLHipJ6VLjwey2U5iYiltJ/dLHCb4PBtuCTxZb/HtMgeam3PQsSSXurVr5NCoPr CnHT1sEm0hmoKvTrpHTb8UZM78a2rPe29dNvsfcRdX+9eugWKu0FJmO96O2AA1K/yxNz LdVLZRPcWdk3DS7UAj/PQRJbPHsdQvj8BUU9uA7gXujhKjixdRwaQV0PLOY+2c+fgndR cQSJQ16C5PuHmhhD0r5RESt7CL6pkThxaOQUlEe7IURqgl3IgFLwjSzW9EPIrrw24NjY oxzyZfqhQ+GrF3N2LChLB/N5dE4nAPsJ3BgmbHOPsqCMHXkryL1713vr0GEAK+QQdUPO 3hUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u6zR8ugZMMSbsUYzZxGLGG2mvpL7z7iHt3BZjr/IYFc=; b=XBYCePZ7U9V4EXF1j7WOxSkPNPyC/3cKtSvTYcqauOf0ZF1H4gMRjeMdYou3yT5TAZ UUfIjSjUocDd1RNVFSIDEnnzEWahVKckdyiwPESUiCYAJ/LrCWmk77LBxQQipXbvWmI3 FAryw+wPPgczJlWi8yv6ME5wYgFKmW2PAileGLQSwtv/WGPy+DBD12PHvpHrDhaVHed1 njtrjuUfOHcG0CZxHAvAksMDabfrUmJrAC2aDvlRPiCUc4wHlqrUvEpAfxKH1E3epe46 hlyDxt9XohSi7Y/I66YsusNYWDjjJi9USkpe71e9JX2uKWgVWgtTAxABTvtag2DSNXh+ IePg== X-Gm-Message-State: AFqh2koyDmVeIx3DqYLb3VBH9TWAJWIu53hK63lsqelWxoNkgdiqpBoj /JNL0oMhuifAC+rhsiEec9Yg X-Google-Smtp-Source: AMrXdXty/zW+OP48FtSBFLMwFJcA5jtnA64QMT/URaoC+T6Jjl/h9QSTM+RuT3a6uZXE9enr+BDCFw== X-Received: by 2002:a17:902:8f86:b0:191:282:5d6c with SMTP id z6-20020a1709028f8600b0019102825d6cmr6452823plo.61.1671715121561; Thu, 22 Dec 2022 05:18:41 -0800 (PST) Received: from localhost.localdomain ([117.217.177.99]) by smtp.gmail.com with ESMTPSA id g12-20020a170902fe0c00b001896040022asm491570plj.190.2022.12.22.05.18.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 05:18:40 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v4 10/16] arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks Date: Thu, 22 Dec 2022 18:46:50 +0530 Message-Id: <20221222131656.49584-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> References: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 570475040d95..12549a2912c6 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3640,8 +3640,11 @@ gem_noc: interconnect@19100000 { system-cache-controller@19200000 { compatible = "qcom,sm8450-llcc"; - reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, + <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, + <0 0x19a00000 0 0x80000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Thu Dec 22 13:16:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 636030 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34DA8C4332F for ; Thu, 22 Dec 2022 13:19:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235692AbiLVNTS (ORCPT ); Thu, 22 Dec 2022 08:19:18 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235535AbiLVNSx (ORCPT ); Thu, 22 Dec 2022 08:18:53 -0500 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98B532B264 for ; Thu, 22 Dec 2022 05:18:49 -0800 (PST) Received: by mail-pl1-x62f.google.com with SMTP id d15so1990761pls.6 for ; Thu, 22 Dec 2022 05:18:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=znASgBClq0rwhBOl4/Fw1c5T/s1foKbyxf4XPqRiKDI=; b=VXe+Xf10elUr+UnSO49j92OhvgPpDswCeSmg+CP9iS6mREZbL8qbFc661pe6BPRjfQ S3oNVU7zYqI9S1bS7I58nmbbA8es6jmQ8pwyAbsbtAM9JJNu3C53jeDKRxU7zvt1xzSS ZFR7zig5z3K+G8wse0/DQhpC6YKUPAVB4WSwfAxXcprqqx7YKa4ShdLkmbLNPILPPFYj pS0zS4x976uQd/9EIjjzzwX5G9bm8b7a91lqP78l2dYEd86dCFaIDGRFs+0TZ00WTUC3 RgkVd4NehMkFcgHCza83ksV8+nHNj/ZIlImHcPegVB9YmotZURTeMSUfuO0CHz9Ezn0L Dz/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=znASgBClq0rwhBOl4/Fw1c5T/s1foKbyxf4XPqRiKDI=; b=ZxMpsjgPp0+5UJVtq9aMGHG+lcbivSlwB8h8TdL87NpVFfSKvwQHFNG9Ok184RDmUY B7ZSZUEGiBhxh8UzC3481jRJpoW9fcaUbWGlveq0UDWPOnHf6byyMjsuNuN3qVPNQOHH 2YeoKqJ6WJZHGI4si4ZcJ9jjVVUbesqvMgPN88FmwIhVLsLDr93dqYdcWSa1LWyVfSzT tL352zwm+lDXQ+2NXrR7kspHl8ZqQMILNy9HR1KrQ5qXokfJxX25ZfN/a+ad4EYQe1mh 8fdYFcXdMBQiirtAy1rd3JHrDHdJGZJYoM7a+gFOrki8HTMpZSceiB8wbgBWw3SqtTwi cF4A== X-Gm-Message-State: AFqh2kpVVgnDY8LLG1ZwKEdkPY3o7/F2aYOb27RgnlLGGbEa2gaO7IiX Z3NkpXq4WJfVwRhFvmLJGxaV60QI8Vxu/5k= X-Google-Smtp-Source: AMrXdXtjtf4dX/X47BtcJcA5+3mMzsRKeuSSmtjKeWq+FivoGU2p4egWef1dD/S8nEDd112vlehkAg== X-Received: by 2002:a17:902:c382:b0:189:e3d0:2682 with SMTP id g2-20020a170902c38200b00189e3d02682mr6521113plg.30.1671715129086; Thu, 22 Dec 2022 05:18:49 -0800 (PST) Received: from localhost.localdomain ([117.217.177.99]) by smtp.gmail.com with ESMTPSA id g12-20020a170902fe0c00b001896040022asm491570plj.190.2022.12.22.05.18.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 05:18:48 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v4 11/16] arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks Date: Thu, 22 Dec 2022 18:46:51 +0530 Message-Id: <20221222131656.49584-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> References: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SM6350, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by: Parikshit Pareek Tested-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 43324bf291c3..c7701f5e4af6 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1174,7 +1174,7 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible = "qcom,sm6350-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg-names = "llcc0_base", "llcc_broadcast_base"; }; gem_noc: interconnect@9680000 { From patchwork Thu Dec 22 13:16:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 636390 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01418C001B2 for ; Thu, 22 Dec 2022 13:19:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235708AbiLVNTf (ORCPT ); Thu, 22 Dec 2022 08:19:35 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235379AbiLVNS5 (ORCPT ); Thu, 22 Dec 2022 08:18:57 -0500 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 519532B24A for ; Thu, 22 Dec 2022 05:18:57 -0800 (PST) Received: by mail-pj1-x1035.google.com with SMTP id t11-20020a17090a024b00b0021932afece4so5661293pje.5 for ; Thu, 22 Dec 2022 05:18:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d0mC3YHxzlEQlwMPao/Y7ASve0hKwhscYa/RkKUoFYA=; b=idwOGGO1DQQ/Drnnb+7kYYOP6u1VjrOPSkhZO0g4Ex4/Q2zJDFJWn+qCdkaQqyNcqD f+N8QoRylsLnXhjcH1klfJYfhRRRLMYjvMmoBSa9PNyonHdW2xmzt1tqT2KhqSaN0Wr0 Gurk2DAUiSrQp+k9WLGF/YVE5HrElbK5O35g227ccc7MYsmUHvPRqnuYBC2XFol912ME s/27D7otADi29Q1kJvPmNyihgYFl6ZiuRIMTUYzWJhkwWQjZ6hUvW+ASNdfqLTL45Bxk RUmSvuwgkgvG7qJupZ0Ks/dHzD4zkASjM21WP8rud+nuZdLcBujsr0lwP0PVC1b8nvvn PSJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d0mC3YHxzlEQlwMPao/Y7ASve0hKwhscYa/RkKUoFYA=; b=z40UpGrhBvLAiaz95HSWq1WBxoePtA/6h/wWP2Ep4gh5dQoV+EWlVda9kNWY/ZGswJ QjgBQk6nk1If6PXT+EfrHmLiLpZVhtY1DBdjnvU3MznsGKsiOrLVIwiuGo8Q93Sjogq/ DB4zZzc39W6SNqTow8NCY0g07zv5px6sEB026wJYTtWCQ9oVGlHxWUZEtJ6sOAsZgA8P 2zF49tqTrRveuFRSNj855K3N1S8xoWhyJeGyqSWjvnz353AonzdvkwK4OJR5pRSTA0XV wT7nE5lu6gtLqNUWCK3s86dR3XbHnEhHQJW0I14oKnX3u/zh3n43KfE8EorRy4TB9ngW kF+A== X-Gm-Message-State: AFqh2kphfMoSINbS5oh+rG0Vfh6i/6zndkoXta9V+b60DN2v2xOt3vwV 5bX1kX8mT8zAqB7aEIjCOkHc X-Google-Smtp-Source: AMrXdXtuB+Kyv8rWt7p+h2nL/e/HlXilbK3Ue4DDES7s++mjFr9Fvneq56XgcSIUgkMBUG46af0ibg== X-Received: by 2002:a05:6a20:b813:b0:af:b16b:eeb5 with SMTP id fi19-20020a056a20b81300b000afb16beeb5mr6682563pzb.25.1671715136603; Thu, 22 Dec 2022 05:18:56 -0800 (PST) Received: from localhost.localdomain ([117.217.177.99]) by smtp.gmail.com with ESMTPSA id g12-20020a170902fe0c00b001896040022asm491570plj.190.2022.12.22.05.18.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 05:18:55 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v4 12/16] EDAC/device: Make use of poll_msec value in edac_device_ctl_info struct Date: Thu, 22 Dec 2022 18:46:52 +0530 Message-Id: <20221222131656.49584-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> References: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The EDAC drivers may optionally pass the poll_msec value. Use that value if available, else fall back to 1000ms. Cc: # 4.9 Fixes: e27e3dac6517 ("drivers/edac: add edac_device class") Reported-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam --- drivers/edac/edac_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/edac/edac_device.c b/drivers/edac/edac_device.c index 19522c568aa5..19c3ab2a434e 100644 --- a/drivers/edac/edac_device.c +++ b/drivers/edac/edac_device.c @@ -447,7 +447,7 @@ int edac_device_add_device(struct edac_device_ctl_info *edac_dev) * enable workq processing on this instance, * default = 1000 msec */ - edac_device_workq_setup(edac_dev, 1000); + edac_device_workq_setup(edac_dev, edac_dev->poll_msec ? edac_dev->poll_msec : 1000); } else { edac_dev->op_state = OP_RUNNING_INTERRUPT; } From patchwork Thu Dec 22 13:16:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 636029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE6CBC4332F for ; Thu, 22 Dec 2022 13:19:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235365AbiLVNTk (ORCPT ); Thu, 22 Dec 2022 08:19:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235525AbiLVNTG (ORCPT ); Thu, 22 Dec 2022 08:19:06 -0500 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A87822B27E for ; Thu, 22 Dec 2022 05:19:04 -0800 (PST) Received: by mail-pj1-x1034.google.com with SMTP id k88-20020a17090a4ce100b00219d0b857bcso1844843pjh.1 for ; Thu, 22 Dec 2022 05:19:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/mWLM+xjtkcHtTlHLK0FQlJaaC6ncfnZviWhmaPi0lM=; b=TOarD5uKYzdGzBgkCMjwru8cWoEMQy/+vSrMtukdY8EyEsh+D35kd+S7H09cmg6j/Z DULe/DTL/oabOivkhr0/PVxddgKe+CvaCfRUv51KVMkEO6qSZ2RIQfMckDB40BJ6vV0B Ht/puy0DpzttOPl6aeL42ts38AjAOjpblgt8ubv8vSNOc7PTw3CcfEXIkesR1nzJpnny vsPVbWDC+0gKgkSu+UkM+PTw5QswbD718pxnahHcR/Na/mw2cTS6K+WYZyhQZPz87Klt 2iAXonIw9nblXUEpjN5t0nuHlMDysNnt/BtGaZxPOXXc1jhqjuw1LjF+5WdRMt5MpDJM P0PA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/mWLM+xjtkcHtTlHLK0FQlJaaC6ncfnZviWhmaPi0lM=; b=GUi1E2maFKTFmf6jwOU9/066mmhDhaf+6zAu45kZ+gl0cXR9ruQovuWnSY4OgOQGBp xIolAaUxTphAfbz3NRWuRR4xupPm1svCwatHBFpAKlODL3XvDLINcblDnHugEc9by6VJ mlIjp2nGsM6ab6tPZRnNU2fmIwUAkeLpYID2okAVPLEFg80fY519jSiPUc8e5izVHEgl 4Y8fcKJUnDschqAoFC3g6VCoD4MbMgWlZJxgUBw94OyPIoRtSn5jdVBW8AHvV8Khlayu DOa/c4Jykt/9QIZiefWn2g3xlBDxc6naHbp92ILxrE0hD+1tItpxnwbwEPS1hPRSTqYM s8Kg== X-Gm-Message-State: AFqh2kobEIGr0MxilnhPDbZyglLBPGusXRWpKlP5zNjNyGwEFl73e4p7 15z/+pUlXi1eR/McitpsAZpX X-Google-Smtp-Source: AMrXdXudkSeoeZwsmTfGklt2Kh/SAQNWHjc6/RvV92AIBr1XEprSb9dEjdUIK+mW5midVbFz3uGWww== X-Received: by 2002:a17:902:8bc6:b0:187:16c2:d52c with SMTP id r6-20020a1709028bc600b0018716c2d52cmr6442361plo.50.1671715144171; Thu, 22 Dec 2022 05:19:04 -0800 (PST) Received: from localhost.localdomain ([117.217.177.99]) by smtp.gmail.com with ESMTPSA id g12-20020a170902fe0c00b001896040022asm491570plj.190.2022.12.22.05.18.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 05:19:03 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v4 13/16] EDAC/qcom: Add platform_device_id table for module autoloading Date: Thu, 22 Dec 2022 18:46:53 +0530 Message-Id: <20221222131656.49584-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> References: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org platform_device_id table needs to be added so that the driver can be autoloaded when the associated platform device gets registered. Reported-by: Andrew Halaney Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 97a27e42dd61..9e77fa84e84f 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -397,12 +397,19 @@ static int qcom_llcc_edac_remove(struct platform_device *pdev) return 0; } +static const struct platform_device_id qcom_llcc_edac_id_table[] = { + { .name = "qcom_llcc_edac" }, + {} +}; +MODULE_DEVICE_TABLE(platform, qcom_llcc_edac_id_table); + static struct platform_driver qcom_llcc_edac_driver = { .probe = qcom_llcc_edac_probe, .remove = qcom_llcc_edac_remove, .driver = { .name = "qcom_llcc_edac", }, + .id_table = qcom_llcc_edac_id_table, }; module_platform_driver(qcom_llcc_edac_driver); From patchwork Thu Dec 22 13:16:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 636389 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 143E5C4332F for ; Thu, 22 Dec 2022 13:20:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235554AbiLVNUK (ORCPT ); Thu, 22 Dec 2022 08:20:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235709AbiLVNTg (ORCPT ); Thu, 22 Dec 2022 08:19:36 -0500 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A0132CC99 for ; Thu, 22 Dec 2022 05:19:12 -0800 (PST) Received: by mail-pj1-x1030.google.com with SMTP id o31-20020a17090a0a2200b00223fedffb30so1828975pjo.3 for ; Thu, 22 Dec 2022 05:19:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dXKaXgl0o6EC/Ht61vc6HyWaaFSyppq0dnbu5Bb4EnE=; b=UeU8tN3RMctOSr0GBqF9tdf+Fnsp2i8GcHeh4jxA3p9jGCptgfW/UgSuOFRO5dbpse 5uiMnmCmFtKVr3t/fedUbZBr+KJmM9QOYlpBd58Yitx82E7k+xw/ih7Rj+Mdald3jxsa embKcwzVJ06cj+EFQMp/f1/34nzj5ia0daMAt8ViqqC4oK1dPLjRHijOXR1+H1RAH2zm kkGeDE/k5ZgSNKgERTojiwWTS2AwMDvK+M/EQPBm6hT3pRUVkPTzExv8OrBcs2SR5Qzw utWvQI5Tz0as/tGeSavc6Pqmtiirh20BQBrMiy1zz5Ipzb+MveSUoqsAIbfxvrHZ+Iq7 YkFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dXKaXgl0o6EC/Ht61vc6HyWaaFSyppq0dnbu5Bb4EnE=; b=sKtJPc3S+uRtUIReiOxcDZYMWUNLeLXvlKxr5Z4BFezMhZCduFqLJjuf6zl18TQ7XL MNzwBUie/ZY9K20Qs9wbSPPXz0uqGurxMm7Q7A9fYQoISIxaWHb+/XuQWUmuZ/pFk+CC 7wLUpquIZeHvVwnMz72dTHj+JnkUm8hFJ3fJwfYbKp5COhDN9f2Eti8P8lWMSwDYS9OC Ou5epJvqWLZqq2p5d9/WLNJFJLr+36tSMUUL7wXLOlq/4A+xDEWt9h1Nq7lzHu3MyJ9t IUmayE4i4pWxV2CrEItz/WDOuqfAzvkIJQInLgf4/MAF1HrlIBrTZoWGu4g/kerZNiRh N+0g== X-Gm-Message-State: AFqh2koQoIStyUm4grifrQ40RwTxlroh+fyYhXqb5rCt24DyysrT975t ioawyKdI8nl6esysoTzQdOkp X-Google-Smtp-Source: AMrXdXsWQe2JmZT4ybf1Q8yo+pzwkZjnU2NlsEBQ+uWgK1veOwKhyHp+NxSzLqNEnE+w5+11gASKMQ== X-Received: by 2002:a17:902:c40f:b0:189:d4c5:f155 with SMTP id k15-20020a170902c40f00b00189d4c5f155mr7723058plk.63.1671715151974; Thu, 22 Dec 2022 05:19:11 -0800 (PST) Received: from localhost.localdomain ([117.217.177.99]) by smtp.gmail.com with ESMTPSA id g12-20020a170902fe0c00b001896040022asm491570plj.190.2022.12.22.05.19.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 05:19:11 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v4 14/16] EDAC/qcom: Do not pass llcc_driv_data as edac_device_ctl_info's pvt_info Date: Thu, 22 Dec 2022 18:46:54 +0530 Message-Id: <20221222131656.49584-15-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> References: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The memory for "llcc_driv_data" is allocated by the LLCC driver. But when it is passed as "pvt_info" to the EDAC core, it will get freed during the qcom_edac driver release. So when the qcom_edac driver gets probed again, it will try to use the freed data leading to the use-after-free bug. Fix this by not passing "llcc_driv_data" as pvt_info but rather reference it using the "platform_data" in the qcom_edac driver. Cc: # 4.20 Fixes: 27450653f1db ("drivers: edac: Add EDAC driver support for QCOM SoCs") Reported-by: Steev Klimaszewski Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 9e77fa84e84f..3256254c3722 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -252,7 +252,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) static int dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank) { - struct llcc_drv_data *drv = edev_ctl->pvt_info; + struct llcc_drv_data *drv = edev_ctl->dev->platform_data; int ret; ret = dump_syn_reg_values(drv, bank, err_type); @@ -289,7 +289,7 @@ static irqreturn_t llcc_ecc_irq_handler(int irq, void *edev_ctl) { struct edac_device_ctl_info *edac_dev_ctl = edev_ctl; - struct llcc_drv_data *drv = edac_dev_ctl->pvt_info; + struct llcc_drv_data *drv = edac_dev_ctl->dev->platform_data; irqreturn_t irq_rc = IRQ_NONE; u32 drp_error, trp_error, i; int ret; @@ -358,7 +358,6 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev) edev_ctl->dev_name = dev_name(dev); edev_ctl->ctl_name = "llcc"; edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE; - edev_ctl->pvt_info = llcc_driv_data; rc = edac_device_add_device(edev_ctl); if (rc) From patchwork Thu Dec 22 13:16:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 636028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96077C10F1D for ; Thu, 22 Dec 2022 13:20:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235181AbiLVNUj (ORCPT ); Thu, 22 Dec 2022 08:20:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48802 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235084AbiLVNUH (ORCPT ); Thu, 22 Dec 2022 08:20:07 -0500 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6A6632EF9E for ; Thu, 22 Dec 2022 05:19:20 -0800 (PST) Received: by mail-pj1-x102a.google.com with SMTP id p4so1893091pjk.2 for ; Thu, 22 Dec 2022 05:19:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q/CCEXzm8VBt7wKt1RLg7h2Nc3d6gd/IYaWUSllPAi8=; b=Gd+QbFR2qP0meFZfYmKVATjBoSPfN9K06BY91iNpkMgg/uRNzBRuaDUbXDYVM0JF1g lwTCMHsyks415drvMz90yzlm7+eUwVnj/v4JHs2PXceRGvh5Th3I6YuaMqPuH8c+gU/6 QYqjFHXsRI/1U0ujMyVEQsKUzKk7zkr+vAQhdEqrQFtSDEFeot8vebR6pDk+kOLgNmpi uXJC9ZAGh0kt7a9b12P/aUgtfQmRYDu6LtfhFcHyahwa1mLXS1pcFkapD2Ct2s7Y4czS L91d4+WPvHTsRonOYBNrq3/wnUSVova1nyrHv1gPSObSD/qjlQG9lYCAJlyaMBjz3xAg uCgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q/CCEXzm8VBt7wKt1RLg7h2Nc3d6gd/IYaWUSllPAi8=; b=TVRG+jV6k0f6X43ENsZ6rXcVaf4nDay0qF02so9IKv9J8+geJuPqx/LJE5c4LjPaMj JIcewIlrnMzrsYgG0L9Hlgv66zCJGCaNcW/yyR1yKTs5crcnFU+9aGb8cZhFEjVdZuIJ TdXTmlYSPEvwpEI5WYS+6hYaQZIFRiqQ15QEklGEzRaxr8MYheG0049pHQRmfJHRHl4G Jy9BPkX90ha6m1LNU5dAG8PX/aLxpSJZB2R41APNXpYSYzgfmfu46T3cf5Y6LF/EygES 1LhbnLGfbiD50FKiOoOijrG1uSiOBXHNCHdYEsURlmhipPZnI59E5m6vJzeOLM575rev +4YQ== X-Gm-Message-State: AFqh2kqFuEnvuKoqLhsGlkp1EMRhgSVYuesD2G9QQgOi7CYLTMc8LXHi OTOdUvyk7DVQgB6d+hYLVenI X-Google-Smtp-Source: AMrXdXsUdXI6/K+lDCD5US4f8VN2PRaXg4hXFg+YFbNgfDlTNaqeOW6BYS1Y5EWl7w2j7PfldENJBw== X-Received: by 2002:a05:6a21:e389:b0:ad:c694:3fc2 with SMTP id cc9-20020a056a21e38900b000adc6943fc2mr6715971pzc.18.1671715159563; Thu, 22 Dec 2022 05:19:19 -0800 (PST) Received: from localhost.localdomain ([117.217.177.99]) by smtp.gmail.com with ESMTPSA id g12-20020a170902fe0c00b001896040022asm491570plj.190.2022.12.22.05.19.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 05:19:18 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v4 15/16] qcom: llcc/edac: Fix the base address used for accessing LLCC banks Date: Thu, 22 Dec 2022 18:46:55 +0530 Message-Id: <20221222131656.49584-16-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> References: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The Qualcomm LLCC/EDAC drivers were using a fixed register stride for accessing the (Control and Status Registers) CSRs of each LLCC bank. This stride only works for some SoCs like SDM845 for which driver support was initially added. But the later SoCs use different register stride that vary between the banks with holes in-between. So it is not possible to use a single register stride for accessing the CSRs of each bank. By doing so could result in a crash. For fixing this issue, let's obtain the base address of each LLCC bank from devicetree and get rid of the fixed stride. This also means, we no longer need to rely on reg-names property and get the base addresses using index. First index is LLCC bank 0 and last index is LLCC broadcast. If the SoC supports more than one bank, then those needs to be defined in devicetree for index from 1..N-1. Reported-by: Parikshit Pareek Tested-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 14 +++--- drivers/soc/qcom/llcc-qcom.c | 72 +++++++++++++++++------------- include/linux/soc/qcom/llcc-qcom.h | 6 +-- 3 files changed, 48 insertions(+), 44 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 3256254c3722..1d3cc1930a74 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -213,7 +213,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) for (i = 0; i < reg_data.reg_cnt; i++) { synd_reg = reg_data.synd_reg + (i * 4); - ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, + ret = regmap_read(drv->regmaps[bank], synd_reg, &synd_val); if (ret) goto clear; @@ -222,8 +222,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) reg_data.name, i, synd_val); } - ret = regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.count_status_reg, + ret = regmap_read(drv->regmaps[bank], reg_data.count_status_reg, &err_cnt); if (ret) goto clear; @@ -233,8 +232,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n", reg_data.name, err_cnt); - ret = regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.ways_status_reg, + ret = regmap_read(drv->regmaps[bank], reg_data.ways_status_reg, &err_ways); if (ret) goto clear; @@ -296,8 +294,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) /* Iterate over the banks and look for Tag RAM or Data RAM errors */ for (i = 0; i < drv->num_banks; i++) { - ret = regmap_read(drv->regmap, - drv->offsets[i] + DRP_INTERRUPT_STATUS, + ret = regmap_read(drv->regmaps[i], DRP_INTERRUPT_STATUS, &drp_error); if (!ret && (drp_error & SB_ECC_ERROR)) { @@ -312,8 +309,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) if (!ret) irq_rc = IRQ_HANDLED; - ret = regmap_read(drv->regmap, - drv->offsets[i] + TRP_INTERRUPT_0_STATUS, + ret = regmap_read(drv->regmaps[i], TRP_INTERRUPT_0_STATUS, &trp_error); if (!ret && (trp_error & SB_ECC_ERROR)) { diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 23ce2f78c4ed..72f3f2a9aaa0 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -62,8 +62,6 @@ #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c #define LLCC_TRP_ALGO_CFG8 0x21f30 -#define BANK_OFFSET_STRIDE 0x80000 - #define LLCC_VERSION_2_0_0_0 0x02000000 #define LLCC_VERSION_2_1_0_0 0x02010000 #define LLCC_VERSION_4_1_0_0 0x04010000 @@ -898,8 +896,8 @@ static int qcom_llcc_remove(struct platform_device *pdev) return 0; } -static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, - const char *name) +static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, u8 index, + const char *name) { void __iomem *base; struct regmap_config llcc_regmap_config = { @@ -909,7 +907,7 @@ static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, .fast_io = true, }; - base = devm_platform_ioremap_resource_byname(pdev, name); + base = devm_platform_ioremap_resource(pdev, index); if (IS_ERR(base)) return ERR_CAST(base); @@ -927,6 +925,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) const struct llcc_slice_config *llcc_cfg; u32 sz; u32 version; + struct regmap *regmap; drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -934,21 +933,51 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; } - drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base"); - if (IS_ERR(drv_data->regmap)) { - ret = PTR_ERR(drv_data->regmap); + /* Initialize the first LLCC bank regmap */ + regmap = qcom_llcc_init_mmio(pdev, 0, "llcc0_base"); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); goto err; } - drv_data->bcast_regmap = - qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); + cfg = of_device_get_match_data(&pdev->dev); + + ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks); + if (ret) + goto err; + + num_banks &= LLCC_LB_CNT_MASK; + num_banks >>= LLCC_LB_CNT_SHIFT; + drv_data->num_banks = num_banks; + + drv_data->regmaps = devm_kcalloc(dev, num_banks, sizeof(*drv_data->regmaps), GFP_KERNEL); + if (!drv_data->regmaps) { + ret = -ENOMEM; + goto err; + } + + drv_data->regmaps[0] = regmap; + + /* Initialize rest of LLCC bank regmaps */ + for (i = 1; i < num_banks; i++) { + char *base = kasprintf(GFP_KERNEL, "llcc%d_base", i); + + drv_data->regmaps[i] = qcom_llcc_init_mmio(pdev, i, base); + if (IS_ERR(drv_data->regmaps[i])) { + ret = PTR_ERR(drv_data->regmaps[i]); + kfree(base); + goto err; + } + + kfree(base); + } + + drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base"); if (IS_ERR(drv_data->bcast_regmap)) { ret = PTR_ERR(drv_data->bcast_regmap); goto err; } - cfg = of_device_get_match_data(&pdev->dev); - /* Extract version of the IP */ ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO], &version); @@ -957,15 +986,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->version = version; - ret = regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], - &num_banks); - if (ret) - goto err; - - num_banks &= LLCC_LB_CNT_MASK; - num_banks >>= LLCC_LB_CNT_SHIFT; - drv_data->num_banks = num_banks; - llcc_cfg = cfg->sct_data; sz = cfg->size; @@ -973,16 +993,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) if (llcc_cfg[i].slice_id > drv_data->max_slices) drv_data->max_slices = llcc_cfg[i].slice_id; - drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), - GFP_KERNEL); - if (!drv_data->offsets) { - ret = -ENOMEM; - goto err; - } - - for (i = 0; i < num_banks; i++) - drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; - drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices, GFP_KERNEL); if (!drv_data->bitmap) { diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index ad1fd718169d..423220e66026 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -120,7 +120,7 @@ struct llcc_edac_reg_offset { /** * struct llcc_drv_data - Data associated with the llcc driver - * @regmap: regmap associated with the llcc device + * @regmaps: regmaps associated with the llcc device * @bcast_regmap: regmap associated with llcc broadcast offset * @cfg: pointer to the data structure for slice configuration * @edac_reg_offset: Offset of the LLCC EDAC registers @@ -129,12 +129,11 @@ struct llcc_edac_reg_offset { * @max_slices: max slices as read from device tree * @num_banks: Number of llcc banks * @bitmap: Bit map to track the active slice ids - * @offsets: Pointer to the bank offsets array * @ecc_irq: interrupt for llcc cache error detection and reporting * @version: Indicates the LLCC version */ struct llcc_drv_data { - struct regmap *regmap; + struct regmap **regmaps; struct regmap *bcast_regmap; const struct llcc_slice_config *cfg; const struct llcc_edac_reg_offset *edac_reg_offset; @@ -143,7 +142,6 @@ struct llcc_drv_data { u32 max_slices; u32 num_banks; unsigned long *bitmap; - u32 *offsets; int ecc_irq; u32 version; }; From patchwork Thu Dec 22 13:16:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 636388 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 486CBC4332F for ; Thu, 22 Dec 2022 13:20:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235639AbiLVNUw (ORCPT ); Thu, 22 Dec 2022 08:20:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49034 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235709AbiLVNUR (ORCPT ); Thu, 22 Dec 2022 08:20:17 -0500 Received: from mail-pj1-x1032.google.com (mail-pj1-x1032.google.com [IPv6:2607:f8b0:4864:20::1032]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 957822EFB5 for ; Thu, 22 Dec 2022 05:19:27 -0800 (PST) Received: by mail-pj1-x1032.google.com with SMTP id v13-20020a17090a6b0d00b00219c3be9830so1824763pjj.4 for ; Thu, 22 Dec 2022 05:19:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jbPgua9Rs+Y/jmkHHRB8iBOCSrUJRilLgsafIRoyD0w=; b=V+1xpDzJK5x7FCBJez4sQfR8rdWJj1vQ9lRrOrEKRqJZc57KyH4DVPtWM85LfqFP2W T5LE7COXtjTKK1fWVeDgH2TEhbHqGe6UG9r/MJgZP+bgAqE6YuK4sbL36dPuJfntCOAZ i4xobhCatBteqqm6eQ5YRinJeudnjFU/iLlwQ0eanU9ry6B6dFrD5zOIl/wqEtMUxNI9 xcpg92Z4yg7pv0YqwW8m1GwFHm8lS4WTzZ7wSK+gDrs/UNRdTgLI5x1GjVxarIErOqlc XFad4RLzK1I+8m9Zy/r8iTrm2O1HghUt1zsBtM/ILAhCNFcQIJJv93Hzr9tH082GHz8+ xW3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jbPgua9Rs+Y/jmkHHRB8iBOCSrUJRilLgsafIRoyD0w=; b=JHrwupKVw6aO2kPhHFpL5v9jPs/5n7RbUSu9FwUJY8NnKWaZn74Uoo8Bi1rGFfdFg7 vcBNwBcLqEeBtiXrh/ujX7rXSGn7J6YFMm1uoV0r/ToIcCj0FEM11lsD2IMAOwoZ6iN1 VFcKjF2XCp8Gdux4tttoO1L3UR60bSvHyVZq3oI3YTN+qTIE090qLv9GAtLXTgkGYIeI Nn40er7i2kJkBgLNXtzz9NnuK4O7dmH5nLXA60pTCI9rWToBoQOXlbA4Wjb5cKYiE/nW ur/CadyI5ZxJlU/P9UD2QUFH5AnW7RVz+i66uPOZlD1dBQNzJGyTukjfGXpVyiUDtNYI Y0Fg== X-Gm-Message-State: AFqh2koXvsRZB3YiiuMuYOzpOJidj8Xb9sEHIjmMVU9b9exleGFQY5d1 L0WqO9GFSvrheqycvpI5PUZW X-Google-Smtp-Source: AMrXdXveeY7kEuyKhD15VcRWF+Fm6mVBnQfV6NOrNNRz8VI5xwv68Fx04E6C69/sUjakYjWfr8ZCiQ== X-Received: by 2002:a17:902:e742:b0:189:83bb:646f with SMTP id p2-20020a170902e74200b0018983bb646fmr8000265plf.17.1671715167031; Thu, 22 Dec 2022 05:19:27 -0800 (PST) Received: from localhost.localdomain ([117.217.177.99]) by smtp.gmail.com with ESMTPSA id g12-20020a170902fe0c00b001896040022asm491570plj.190.2022.12.22.05.19.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Dec 2022 05:19:26 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: quic_saipraka@quicinc.com, konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v4 16/16] qcom: llcc/edac: Support polling mode for ECC handling Date: Thu, 22 Dec 2022 18:46:56 +0530 Message-Id: <20221222131656.49584-17-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> References: <20221222131656.49584-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Not all Qcom platforms support IRQ mode for ECC handling. For those platforms, the current EDAC driver will not be probed due to missing ECC IRQ in devicetree. So add support for polling mode so that the EDAC driver can be used on all Qcom platforms supporting LLCC. The polling delay of 5000ms is chosen based on Qcom downstream/vendor driver. Reported-by: Luca Weiss Tested-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 37 +++++++++++++++++++++++++----------- drivers/soc/qcom/llcc-qcom.c | 13 ++++++------- 2 files changed, 32 insertions(+), 18 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 1d3cc1930a74..cfcdc35b0373 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -76,6 +76,8 @@ #define DRP0_INTERRUPT_ENABLE BIT(6) #define SB_DB_DRP_INTERRUPT_ENABLE 0x3 +#define ECC_POLL_MSEC 5000 + enum { LLCC_DRAM_CE = 0, LLCC_DRAM_UE, @@ -283,8 +285,7 @@ dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank) return ret; } -static irqreturn_t -llcc_ecc_irq_handler(int irq, void *edev_ctl) +static irqreturn_t llcc_ecc_irq_handler(int irq, void *edev_ctl) { struct edac_device_ctl_info *edac_dev_ctl = edev_ctl; struct llcc_drv_data *drv = edac_dev_ctl->dev->platform_data; @@ -328,6 +329,11 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) return irq_rc; } +static void llcc_ecc_check(struct edac_device_ctl_info *edev_ctl) +{ + llcc_ecc_irq_handler(0, edev_ctl); +} + static int qcom_llcc_edac_probe(struct platform_device *pdev) { struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data; @@ -355,22 +361,31 @@ static int qcom_llcc_edac_probe(struct platform_device *pdev) edev_ctl->ctl_name = "llcc"; edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE; + /* Check if LLCC driver has passed ECC IRQ */ + ecc_irq = llcc_driv_data->ecc_irq; + if (ecc_irq > 0) { + /* Use interrupt mode if IRQ is available */ + edac_op_state = EDAC_OPSTATE_INT; + } else { + /* Fall back to polling mode otherwise */ + edac_op_state = EDAC_OPSTATE_POLL; + edev_ctl->poll_msec = ECC_POLL_MSEC; + edev_ctl->edac_check = llcc_ecc_check; + } + rc = edac_device_add_device(edev_ctl); if (rc) goto out_mem; platform_set_drvdata(pdev, edev_ctl); - /* Request for ecc irq */ - ecc_irq = llcc_driv_data->ecc_irq; - if (ecc_irq < 0) { - rc = -ENODEV; - goto out_dev; - } - rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, + /* Request ECC IRQ if available */ + if (ecc_irq > 0) { + rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler, IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl); - if (rc) - goto out_dev; + if (rc) + goto out_dev; + } return rc; diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 72f3f2a9aaa0..7b7c5a38bac6 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -1011,13 +1011,12 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); - if (drv_data->ecc_irq >= 0) { - llcc_edac = platform_device_register_data(&pdev->dev, - "qcom_llcc_edac", -1, drv_data, - sizeof(*drv_data)); - if (IS_ERR(llcc_edac)) - dev_err(dev, "Failed to register llcc edac driver\n"); - } + + llcc_edac = platform_device_register_data(&pdev->dev, + "qcom_llcc_edac", -1, drv_data, + sizeof(*drv_data)); + if (IS_ERR(llcc_edac)) + dev_err(dev, "Failed to register llcc edac driver\n"); return 0; err: