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Iglesias" , =?utf-8?q?C=C3=A9dric_Le_Go?= =?utf-8?q?ater?= , Alistair Francis , qemu-arm@nongnu.org, Tyrone Ting Subject: [PATCH 1/6] hw/arm/aspeed: Fix smpboot[] on big-endian hosts Date: Thu, 22 Dec 2022 22:55:44 +0100 Message-Id: <20221222215549.86872-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221222215549.86872-1-philmd@linaro.org> References: <20221222215549.86872-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=philmd@linaro.org; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org ARM CPUs fetch instructions in little-endian. smpboot[] encoded instructions are written in little-endian. This is fine on little-endian host, but on big-endian ones the smpboot[] array ends swapped. Use the const_le32() macro so the instructions are always in little-endian in the smpboot[] array. Fixes: 9bb6d14081 ("aspeed: Add boot stub for smp booting") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Cédric Le Goater Signed-off-by: Cédric Le Goater --- hw/arm/aspeed.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 55f114ef72..adff9a0d73 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -194,22 +194,22 @@ static void aspeed_write_smpboot(ARMCPU *cpu, * r1 = AST_SMP_MBOX_FIELD_ENTRY * r0 = AST_SMP_MBOX_FIELD_GOSIGN */ - 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ - 0xe21000ff, /* ands r0, r0, #255 */ - 0xe59f201c, /* ldr r2, [pc, #28] */ - 0xe1822000, /* orr r2, r2, r0 */ + const_le32(0xee100fb0), /* mrc p15, 0, r0, c0, c0, 5 */ + const_le32(0xe21000ff), /* ands r0, r0, #255 */ + const_le32(0xe59f201c), /* ldr r2, [pc, #28] */ + const_le32(0xe1822000), /* orr r2, r2, r0 */ - 0xe59f1018, /* ldr r1, [pc, #24] */ - 0xe59f0018, /* ldr r0, [pc, #24] */ + const_le32(0xe59f1018), /* ldr r1, [pc, #24] */ + const_le32(0xe59f0018), /* ldr r0, [pc, #24] */ - 0xe320f002, /* wfe */ - 0xe5904000, /* ldr r4, [r0] */ - 0xe1520004, /* cmp r2, r4 */ - 0x1afffffb, /* bne */ - 0xe591f000, /* ldr pc, [r1] */ - AST_SMP_MBOX_GOSIGN, - AST_SMP_MBOX_FIELD_ENTRY, - AST_SMP_MBOX_FIELD_GOSIGN, + const_le32(0xe320f002), /* wfe */ + const_le32(0xe5904000), /* ldr r4, [r0] */ + const_le32(0xe1520004), /* cmp r2, r4 */ + const_le32(0x1afffffb), /* bne */ + const_le32(0xe591f000), /* ldr pc, [r1] */ + const_le32(AST_SMP_MBOX_GOSIGN), + const_le32(AST_SMP_MBOX_FIELD_ENTRY), + const_le32(AST_SMP_MBOX_FIELD_GOSIGN) }; rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, From patchwork Thu Dec 22 21:55:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 635953 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp125712pvb; Thu, 22 Dec 2022 13:56:36 -0800 (PST) X-Google-Smtp-Source: AMrXdXtWwXSbhR8zEzFWD2B1Dfud4gJH7rSNuBkN8UHGQXLvNgJ+d70Uen6G+DWT3OdHHpiVHc6V X-Received: by 2002:a0c:e98e:0:b0:4c7:8c96:d2ca with SMTP id z14-20020a0ce98e000000b004c78c96d2camr7250710qvn.15.1671746196240; Thu, 22 Dec 2022 13:56:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671746196; cv=none; d=google.com; s=arc-20160816; b=GWcp4y61Un/yUB9lp73z6O13oubQPSxl6+iGJmhO7uLIo4mkkSMg8kBXikTSAxxVq1 2r0E0qf11RUf2IAzThUvTeWtE+yAk1RwD8dGo+uai4yAOkpuCuXrIv/BP+QYPfHyoMkF QhApGu0UDHs2NGfyLfpb+n1Iow3yiehdJ9NfWxkxwBS9LZjRAAXqDfARlNolNAOFWdQ4 +VkQlri4mdfvHyfvj5QHzck7gV9c4uKefoCHFaV5ynYqpp0swI3hlp4zTsp8T27ajb7I UsCbT5Ca5mJyPn+cZ6ut91PWt4Yo45q1at8tujK9cLC3c3WI80XaatizHVENKqnzy1kX bXJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=AlbISwcoF8H6Ar9FnAMnX+v9JsbwYxtSUgLoTP68Yao=; b=HL+1CG45MdpDwSJ1HVjANZHuYQ4KZUb/7sKsuivTVdPpvQ8EIWsDyC262L9YZXq3J+ UnWHQ5FWqV9Cp0e0+9gxwwOKn6dFwmXMkQTLZ3I5AaUBdcpqyLeh1qLGatiSaFq2pkEC hMwmhNms8242YDq/hO4BCSH95ffrf49z/Pr8YpVA0skLg+M3aIbtH/zPChtXVuBW4W0N l4bPrwQKNSOUoppbuPQCk4pVVnvJfwmDrTUoxq6cDLH714smEdRwda35HkFvIq55s6Cj dVhsKF7CAtvVM2/EYlnuNUX6ngLT7eXgM9Yx5YrVsoWjLx30os8LNOeP1FE+xWIG5w4S rJgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TjwkXWpK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , =?utf-8?q?C=C3=A9dric_Le_Go?= =?utf-8?q?ater?= , Alistair Francis , qemu-arm@nongnu.org, Tyrone Ting Subject: [PATCH 2/6] hw/arm/raspi: Fix smpboot[] on big-endian hosts Date: Thu, 22 Dec 2022 22:55:45 +0100 Message-Id: <20221222215549.86872-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221222215549.86872-1-philmd@linaro.org> References: <20221222215549.86872-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=philmd@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org ARM CPUs fetch instructions in little-endian. smpboot[] encoded instructions are written in little-endian. This is fine on little-endian host, but on big-endian ones the smpboot[] array ends swapped. Use the const_le32() macro so the instructions are always in little-endian in the smpboot[] array. Fixes: 1df7d1f930 ("raspi: add raspberry pi 2 machine") Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/raspi.c | 46 +++++++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 92d068d1f9..72572a45c2 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -125,18 +125,18 @@ static const char *board_type(uint32_t board_rev) static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info) { static const uint32_t smpboot[] = { - 0xe1a0e00f, /* mov lr, pc */ - 0xe3a0fe00 + (BOARDSETUP_ADDR >> 4), /* mov pc, BOARDSETUP_ADDR */ - 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5;get core ID */ - 0xe7e10050, /* ubfx r0, r0, #0, #2 ;extract LSB */ - 0xe59f5014, /* ldr r5, =0x400000CC ;load mbox base */ - 0xe320f001, /* 1: yield */ - 0xe7953200, /* ldr r3, [r5, r0, lsl #4] ;read mbox for our core*/ - 0xe3530000, /* cmp r3, #0 ;spin while zero */ - 0x0afffffb, /* beq 1b */ - 0xe7853200, /* str r3, [r5, r0, lsl #4] ;clear mbox */ - 0xe12fff13, /* bx r3 ;jump to target */ - 0x400000cc, /* (constant: mailbox 3 read/clear base) */ + const_le32(0xe1a0e00f), /* mov lr, pc */ + const_le32(0xe3a0fe00 + (BOARDSETUP_ADDR >> 4)), /* mov pc, BOARDSETUP_ADDR */ + const_le32(0xee100fb0), /* mrc p15, 0, r0, c0, c0, 5;get core ID */ + const_le32(0xe7e10050), /* ubfx r0, r0, #0, #2 ;extract LSB */ + const_le32(0xe59f5014), /* ldr r5, =0x400000CC ;load mbox base */ + const_le32(0xe320f001), /* 1: yield */ + const_le32(0xe7953200), /* ldr r3, [r5, r0, lsl #4] ;read mbox for our core*/ + const_le32(0xe3530000), /* cmp r3, #0 ;spin while zero */ + const_le32(0x0afffffb), /* beq 1b */ + const_le32(0xe7853200), /* str r3, [r5, r0, lsl #4] ;clear mbox */ + const_le32(0xe12fff13), /* bx r3 ;jump to target */ + const_le32(0x400000cc), /* (constant: mailbox 3 read/clear base) */ }; /* check that we don't overrun board setup vectors */ @@ -162,17 +162,17 @@ static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info) * a rom blob, so that the reset for ROM contents zeroes them for us. */ static const uint32_t smpboot[] = { - 0xd2801b05, /* mov x5, 0xd8 */ - 0xd53800a6, /* mrs x6, mpidr_el1 */ - 0x924004c6, /* and x6, x6, #0x3 */ - 0xd503205f, /* spin: wfe */ - 0xf86678a4, /* ldr x4, [x5,x6,lsl #3] */ - 0xb4ffffc4, /* cbz x4, spin */ - 0xd2800000, /* mov x0, #0x0 */ - 0xd2800001, /* mov x1, #0x0 */ - 0xd2800002, /* mov x2, #0x0 */ - 0xd2800003, /* mov x3, #0x0 */ - 0xd61f0080, /* br x4 */ + const_le32(0xd2801b05), /* mov x5, 0xd8 */ + const_le32(0xd53800a6), /* mrs x6, mpidr_el1 */ + const_le32(0x924004c6), /* and x6, x6, #0x3 */ + const_le32(0xd503205f), /* spin: wfe */ + const_le32(0xf86678a4), /* ldr x4, [x5,x6,lsl #3] */ + const_le32(0xb4ffffc4), /* cbz x4, spin */ + const_le32(0xd2800000), /* mov x0, #0x0 */ + const_le32(0xd2800001), /* mov x1, #0x0 */ + const_le32(0xd2800002), /* mov x2, #0x0 */ + const_le32(0xd2800003), /* mov x3, #0x0 */ + const_le32(0xd61f0080), /* br x4 */ }; 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Iglesias" , =?utf-8?q?C=C3=A9dric_Le_Go?= =?utf-8?q?ater?= , Alistair Francis , qemu-arm@nongnu.org, Tyrone Ting Subject: [PATCH 3/6] hw/arm/exynos4210: Remove tswap32() calls and constify smpboot[] Date: Thu, 22 Dec 2022 22:55:46 +0100 Message-Id: <20221222215549.86872-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221222215549.86872-1-philmd@linaro.org> References: <20221222215549.86872-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=philmd@linaro.org; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org ARM CPUs fetch instructions in little-endian. smpboot[] encoded instructions are written in little-endian. We call tswap32() on the array. tswap32 function swap a 32-bit value if the target endianness doesn't match the host one. Otherwise it is a NOP. * On a little-endian host, the array is stored as it. tswap32() is a NOP, and the vCPU fetches the instructions as it, in little-endian. * On a big-endian host, the array is stored as it. tswap32() swap the instructions to little-endian, and the vCPU fetches the instructions as it, in little-endian. Using tswap() on system emulation is a bit odd: while the target particularities might change the system emulation, the host ones (such its endianness) shouldn't interfere. We can simplify by using const_le32() to always store the instructions in the array in little-endian, removing the need for the dubious tswap(). Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/exynos4210.c | 48 ++++++++++++++++++++------------------------- 1 file changed, 21 insertions(+), 27 deletions(-) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 8dafa2215b..89ee83456d 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -468,35 +468,29 @@ static const MemoryRegionOps exynos4210_chipid_and_omr_ops = { } }; -void exynos4210_write_secondary(ARMCPU *cpu, - const struct arm_boot_info *info) +void exynos4210_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info) { - int n; - uint32_t smpboot[] = { - 0xe59f3034, /* ldr r3, External gic_cpu_if */ - 0xe59f2034, /* ldr r2, Internal gic_cpu_if */ - 0xe59f0034, /* ldr r0, startaddr */ - 0xe3a01001, /* mov r1, #1 */ - 0xe5821000, /* str r1, [r2] */ - 0xe5831000, /* str r1, [r3] */ - 0xe3a010ff, /* mov r1, #0xff */ - 0xe5821004, /* str r1, [r2, #4] */ - 0xe5831004, /* str r1, [r3, #4] */ - 0xf57ff04f, /* dsb */ - 0xe320f003, /* wfi */ - 0xe5901000, /* ldr r1, [r0] */ - 0xe1110001, /* tst r1, r1 */ - 0x0afffffb, /* beq */ - 0xe12fff11, /* bx r1 */ - EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, - 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ - 0 /* bootreg: Boot register address is held here */ + const uint32_t smpboot[] = { + const_le32(0xe59f3034), /* ldr r3, External gic_cpu_if */ + const_le32(0xe59f2034), /* ldr r2, Internal gic_cpu_if */ + const_le32(0xe59f0034), /* ldr r0, startaddr */ + const_le32(0xe3a01001), /* mov r1, #1 */ + const_le32(0xe5821000), /* str r1, [r2] */ + const_le32(0xe5831000), /* str r1, [r3] */ + const_le32(0xe3a010ff), /* mov r1, #0xff */ + const_le32(0xe5821004), /* str r1, [r2, #4] */ + const_le32(0xe5831004), /* str r1, [r3, #4] */ + const_le32(0xf57ff04f), /* dsb */ + const_le32(0xe320f003), /* wfi */ + const_le32(0xe5901000), /* ldr r1, [r0] */ + const_le32(0xe1110001), /* tst r1, r1 */ + const_le32(0x0afffffb), /* beq */ + const_le32(0xe12fff11), /* bx r1 */ + const_le32(EXYNOS4210_EXT_GIC_CPU_BASE_ADDR), + cpu_to_le32(info->gic_cpu_if_addr), /* base address of Internal GIC CPU interface */ + cpu_to_le32(info->smp_bootreg_addr) /* Boot register address is held here */ }; - smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; - smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; - for (n = 0; n < ARRAY_SIZE(smpboot); n++) { - smpboot[n] = tswap32(smpboot[n]); - } + rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), info->smp_loader_start); } From patchwork Thu Dec 22 21:55:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 635958 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp126234pvb; Thu, 22 Dec 2022 13:58:32 -0800 (PST) X-Google-Smtp-Source: AMrXdXuUZjG23vfGTr+NWg9WMzOiXY4yHUSs8KixlnnZloqazpy3HQehZTd/OiRzTCY3MB5bPBaW X-Received: by 2002:a05:6214:450c:b0:4c7:a44:4843 with SMTP id oo12-20020a056214450c00b004c70a444843mr10889043qvb.10.1671746312243; Thu, 22 Dec 2022 13:58:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671746312; cv=none; d=google.com; s=arc-20160816; b=q+PTl+7wfc+4nbBaYKjX+7yA3PooUisYs6HOLCk6ZI1xd7pWxeLEu6Ay1Terpcso6t SVR9nhYI8r3X3WyM1t087bOYv9YZpwOKrsVLL3Cz9ZQG++ZTs95r0Y1IVOU4Lf/JM4K2 SX1vmWI0P1X9dfJLrkyOSyaNu4Od4DTempgiomh9kU5osMHZXeLrDttDfEwBCme5/hc4 TqQJBPE4lARhFeGFRQBWDuFMv0TZu7h3SAziwfV1w2fDejyZadqUBu2R36+k9AapCJTD vMRWneI9Bus0Hoh7b+d7X1sPGn3/8KB6RwaVJDdsYqx4nG2OvWHOKJTuZPh1JsE9AE7g zmdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=tY6SKki/uWVAIv0MsBbw55az0oWSvt0PY3G9FmsSaas=; b=WMA4Y08RaF1KEIl0xb36wwKoRozlShArEiUwGYncXHSGuqok+rtNGlVJMF1Pz6QdGK jemH8/9zMtugxUdttol+d5NobIRrGPuaz9VH+DTCLG6C3YfMNf6nprY9eif0A7hLBqIP WK+KTCP88KETyWYTGM6/1r+JZhmcjoGTAjqlG7KVeMwgtw9GNajF0M77oOLbqbRM5Wak Eh83DglKi/F39rKIHeaLljpVzDkHQtsP8GRbxa1O7SPfMgPido8bHafymRbjx/YvZozb rXhn9H2IfeiL+D5cMLdulSexrOhslXTw3euilhnWWZx+leV0dJE8Gn4DktDUl1ZmyaMI 2tfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dL2p6foo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , =?utf-8?q?C=C3=A9dric_Le_Go?= =?utf-8?q?ater?= , Alistair Francis , qemu-arm@nongnu.org, Tyrone Ting Subject: [PATCH 4/6] hw/arm/npcm7xx: Remove tswap32() calls and constify smpboot[] Date: Thu, 22 Dec 2022 22:55:47 +0100 Message-Id: <20221222215549.86872-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221222215549.86872-1-philmd@linaro.org> References: <20221222215549.86872-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=philmd@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org ARM CPUs fetch instructions in little-endian. smpboot[] encoded instructions are written in little-endian. We call tswap32() on the array. tswap32 function swap a 32-bit value if the target endianness doesn't match the host one. Otherwise it is a NOP. * On a little-endian host, the array is stored as it. tswap32() is a NOP, and the vCPU fetches the instructions as it, in little-endian. * On a big-endian host, the array is stored as it. tswap32() swap the instructions to little-endian, and the vCPU fetches the instructions as it, in little-endian. Using tswap() on system emulation is a bit odd: while the target particularities might change the system emulation, the host ones (such its endianness) shouldn't interfere. We can simplify by using const_le32() to always store the instructions in the array in little-endian, removing the need for the dubious tswap(). Signed-off-by: Philippe Mathieu-Daudé --- Note there is still a tswap() call in npcm7xx_init_fuses() --- hw/arm/npcm7xx.c | 49 ++++++++++++++++++++---------------------------- 1 file changed, 20 insertions(+), 29 deletions(-) diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index d85cc02765..2976192731 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -291,22 +291,18 @@ static const struct { static void npcm7xx_write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) { - uint32_t board_setup[] = { - 0xe59f0010, /* ldr r0, clk_base_addr */ - 0xe59f1010, /* ldr r1, pllcon1_value */ - 0xe5801010, /* str r1, [r0, #16] */ - 0xe59f100c, /* ldr r1, clksel_value */ - 0xe5801004, /* str r1, [r0, #4] */ - 0xe12fff1e, /* bx lr */ - NPCM7XX_CLK_BA, - NPCM7XX_PLLCON1_FIXUP_VAL, - NPCM7XX_CLKSEL_FIXUP_VAL, + static const uint32_t board_setup[] = { + const_le32(0xe59f0010), /* ldr r0, clk_base_addr */ + const_le32(0xe59f1010), /* ldr r1, pllcon1_value */ + const_le32(0xe5801010), /* str r1, [r0, #16] */ + const_le32(0xe59f100c), /* ldr r1, clksel_value */ + const_le32(0xe5801004), /* str r1, [r0, #4] */ + const_le32(0xe12fff1e), /* bx lr */ + const_le32(NPCM7XX_CLK_BA), + const_le32(NPCM7XX_PLLCON1_FIXUP_VAL), + const_le32(NPCM7XX_CLKSEL_FIXUP_VAL), }; - int i; - for (i = 0; i < ARRAY_SIZE(board_setup); i++) { - board_setup[i] = tswap32(board_setup[i]); - } rom_add_blob_fixed("board-setup", board_setup, sizeof(board_setup), info->board_setup_addr); } @@ -321,22 +317,17 @@ static void npcm7xx_write_secondary_boot(ARMCPU *cpu, * we need to provide our own smpboot stub that can not use 'wfi', it has * to spin the secondary CPU until the first CPU writes to the SCRPAD reg. */ - uint32_t smpboot[] = { - 0xe59f2018, /* ldr r2, bootreg_addr */ - 0xe3a00000, /* mov r0, #0 */ - 0xe5820000, /* str r0, [r2] */ - 0xe320f002, /* wfe */ - 0xe5921000, /* ldr r1, [r2] */ - 0xe1110001, /* tst r1, r1 */ - 0x0afffffb, /* beq */ - 0xe12fff11, /* bx r1 */ - NPCM7XX_SMP_BOOTREG_ADDR, + static const uint32_t smpboot[] = { + const_le32(0xe59f2018), /* ldr r2, bootreg_addr */ + const_le32(0xe3a00000), /* mov r0, #0 */ + const_le32(0xe5820000), /* str r0, [r2] */ + const_le32(0xe320f002), /* wfe */ + const_le32(0xe5921000), /* ldr r1, [r2] */ + const_le32(0xe1110001), /* tst r1, r1 */ + const_le32(0x0afffffb), /* beq */ + const_le32(0xe12fff11), /* bx r1 */ + const_le32(NPCM7XX_SMP_BOOTREG_ADDR), }; - int i; - - for (i = 0; i < ARRAY_SIZE(smpboot); i++) { - smpboot[i] = tswap32(smpboot[i]); - } rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), NPCM7XX_SMP_LOADER_START); From patchwork Thu Dec 22 21:55:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 635955 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp126055pvb; Thu, 22 Dec 2022 13:57:56 -0800 (PST) X-Google-Smtp-Source: AMrXdXvqwCyUU/sw5WJqyoA5J/5olWJoF6ZRe6qBE1c7y3WxuRT2PpZW26tkXLAi4eIovSeArj+D X-Received: by 2002:a05:622a:30d:b0:3a7:e783:7b6 with SMTP id q13-20020a05622a030d00b003a7e78307b6mr12737749qtw.5.1671746276314; Thu, 22 Dec 2022 13:57:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671746276; cv=none; d=google.com; s=arc-20160816; b=Ch8hCoYPwVa57Gma2sHAmmqAlk+iNDfR8zU7wLZX+w2rWKrfiLibH5mWviSLDxiCis yRUhClP2l5LjhwsWGUwhJWUDSgtjvRG2iXjDNVDZv2qmvLyjDYeReTZXRhX6IEtmse9d taDTl2FzSj8Q3mLgMryABwfePvzu0yyGbSQzuVH+W3gm8ns8voN0ts5ZiSxaRqj267oC AW4kfTuUaPDwZ5OguQqJmWdxdg+N4198RREGgg+Y4R39Opwxx2XrM/yQzuCPohfG8iGb A0osd7UAsVRW3IFA6r1CD7iF/issFB1+KNWXxmTZwE/3OP22G4nq2UMVD+aW4ULJmaQm IqRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=eJ7KNsaeAIcuwibRTmPK9N9xgsftdW4nEKhohT2Tqnw=; b=ZbmpAsWmaawHzJWdvCnFTim0mUObTWSyOZE64uaGS3i24hLa8kFOobhlLKTl323dpl mqfas/CTSlYq8zI8L0mAga4s2UMfkveudK+0s0SBRiZWGgSqjZR3XTltKazgNB5it6Ua pGKQl6hB1739bRwt6J38jHX7MJ8c5zoQfA19afnL2wlGbGgcUUlKgELdGru7sYUTormt B/hEf93kjRYyhCJ2YlG0fUnzJSv/6Qyw0Jr0kW93lLzCW/Qj2SmMV/RXhVCJoNBP2cYx ipHZhb38F24CuZ38OG+zdZnJ/Ir2wElQ3ulNIb5OsDC1MFx32aRsWf6uyHfIClonPmRd pZuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iEJLpHzx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , =?utf-8?q?C=C3=A9dric_Le_Go?= =?utf-8?q?ater?= , Alistair Francis , qemu-arm@nongnu.org, Tyrone Ting Subject: [PATCH 5/6] hw/arm/xilinx_zynq: Remove tswap32() calls and constify smpboot[] Date: Thu, 22 Dec 2022 22:55:48 +0100 Message-Id: <20221222215549.86872-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221222215549.86872-1-philmd@linaro.org> References: <20221222215549.86872-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=philmd@linaro.org; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org ARM CPUs fetch instructions in little-endian. smpboot[] encoded instructions are written in little-endian. We call tswap32() on the array. tswap32 function swap a 32-bit value if the target endianness doesn't match the host one. Otherwise it is a NOP. * On a little-endian host, the array is stored as it. tswap32() is a NOP, and the vCPU fetches the instructions as it, in little-endian. * On a big-endian host, the array is stored as it. tswap32() swap the instructions to little-endian, and the vCPU fetches the instructions as it, in little-endian. Using tswap() on system emulation is a bit odd: while the target particularities might change the system emulation, the host ones (such its endianness) shouldn't interfere. We can simplify by using const_le32() to always store the instructions in the array in little-endian, removing the need for the dubious tswap(). Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/xilinx_zynq.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 3190cc0b8d..4316143b71 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -71,6 +71,11 @@ static const int dma_irqs[8] = { #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */ +struct ZynqMachineState { + MachineState parent; + Clock *ps_clk; +}; + #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ extract32((x), 12, 4) << 16) @@ -79,29 +84,21 @@ static const int dma_irqs[8] = { */ #define SLCR_WRITE(addr, val) \ - 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \ - 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ - 0xe5801000 + (addr) - -struct ZynqMachineState { - MachineState parent; - Clock *ps_clk; -}; + cpu_to_le32(0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16))), /* movw r1 ... */ \ + cpu_to_le32(0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16))), /* movt r1 ... */ \ + const_le32(0xe5801000 + (addr)) static void zynq_write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) { - int n; - uint32_t board_setup_blob[] = { - 0xe3a004f8, /* mov r0, #0xf8000000 */ + const uint32_t board_setup_blob[] = { + const_le32(0xe3a004f8), /* mov r0, #0xf8000000 */ SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY), SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008), SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY), - 0xe12fff1e, /* bx lr */ + const_le32(0xe12fff1e) /* bx lr */ }; - for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { - board_setup_blob[n] = tswap32(board_setup_blob[n]); - } + rom_add_blob_fixed("board-setup", board_setup_blob, sizeof(board_setup_blob), BOARD_SETUP_ADDR); } From patchwork Thu Dec 22 21:55:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 635957 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp126164pvb; Thu, 22 Dec 2022 13:58:17 -0800 (PST) X-Google-Smtp-Source: AMrXdXuia9McvSGMguYi7k/d0jfTpF45AOO82/cZSAkxbZq4W5k+/Nmiog7rmqMGvGhyv1xqJmP3 X-Received: by 2002:a05:622a:1f17:b0:3a9:8370:63d4 with SMTP id ca23-20020a05622a1f1700b003a9837063d4mr18209936qtb.42.1671746296923; Thu, 22 Dec 2022 13:58:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671746296; cv=none; d=google.com; s=arc-20160816; b=km6u0nWVOCaexIsFNRurpl1JvL6E9LQNkOERgBePwPx4FXRSailtU+8LcAyWRNz89O uu0Cakgg8KvhK5RObYLfxyXuHzBtBP5SgqaWn/7uWEMcO4VD4MoyaFLFdpDvWyFSwFwm NBi76Q7Pf/YCuArCiddeuvYcNoAlY1Isd0/Nscjr9YBQfNx19c0Z9ZZX90DZlgR8BKiI W29+rywH46WkiYI8CXIXlMAQXecGpaaDZu6mXULP4USxhpaBYOMM/wM2L1BWu7dNTYJ8 WhLUE3Yk27HbDntWC7ubtoQ6ZBJEYUwKD77n0PZHg/y3JaEifUTvwBgxMQeFvJPQSjqG Nsmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oaCMViCuj4W9XyEnm5VQb8sPut9cn3g3RlnYgzpwXls=; b=CT2DR1eBAqur1HDWEj2HEaLRcdX8ikkhla6XKPW2HTmeyrHUMdnLWcDOoAqB4SElnU tENJL14s5qZ9GvLFPW+HVx+FZ2C06Spu3fH6HmztianL0bZ8mlPkH1NWYLdwQq4fNSab 62+EvJE3KMnVggZGDECEH626scBbCE50O+kP60/GBg5nYQrdX/mFd4on3ZSa37W7t/42 /C35T8B0dHOzR2ICOV+nRk2DMH5CO/r6WDeIxVKAvU/eySwLV8yzmOdSy9hcfMjEaRSk mLJfboUpr+z7KTjwGlXo4qjnjN5ehgUMIy8VQLwEOXkHHO3TbVxo+C85eakafZ0bimso /dnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b63W81rK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Iglesias" , =?utf-8?q?C=C3=A9dric_Le_Go?= =?utf-8?q?ater?= , Alistair Francis , qemu-arm@nongnu.org, Tyrone Ting Subject: [PATCH 6/6] hw/arm/boot: Remove tswap32() calls and constify board_setup_blob[] Date: Thu, 22 Dec 2022 22:55:49 +0100 Message-Id: <20221222215549.86872-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221222215549.86872-1-philmd@linaro.org> References: <20221222215549.86872-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=philmd@linaro.org; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org ARM CPUs fetch instructions in little-endian. board_setup_blob[] encoded instructions are written in little-endian. We call tswap32() on the array. tswap32 function swap a 32-bit value if the target endianness doesn't match the host one. Otherwise it is a NOP. * On a little-endian host, the array is stored as it. tswap32() is a NOP, and the vCPU fetches the instructions as it, in little-endian. * On a big-endian host, the array is stored as it. tswap32() swap the instructions to little-endian, and the vCPU fetches the instructions as it, in little-endian. Using tswap() on system emulation is a bit odd: while the target particularities might change the system emulation, the host ones (such its endianness) shouldn't interfere. We can simplify by using const_le32() to always store the instructions in the array in little-endian, removing the need for the dubious tswap(). Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/boot.c | 52 ++++++++++++++++++++++----------------------------- 1 file changed, 22 insertions(+), 30 deletions(-) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 3d7d11f782..22a100f19b 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -189,7 +189,7 @@ static void write_bootloader(const char *name, hwaddr addr, default: abort(); } - code[i] = tswap32(insn); + code[i] = cpu_to_le32(insn); } assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE); @@ -222,34 +222,33 @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, hwaddr mvbar_addr) { AddressSpace *as = arm_boot_address_space(cpu, info); - int n; - uint32_t mvbar_blob[] = { + static const uint32_t mvbar_blob[] = { /* mvbar_addr: secure monitor vectors * Default unimplemented and unused vectors to spin. Makes it * easier to debug (as opposed to the CPU running away). */ - 0xeafffffe, /* (spin) */ - 0xeafffffe, /* (spin) */ - 0xe1b0f00e, /* movs pc, lr ;SMC exception return */ - 0xeafffffe, /* (spin) */ - 0xeafffffe, /* (spin) */ - 0xeafffffe, /* (spin) */ - 0xeafffffe, /* (spin) */ - 0xeafffffe, /* (spin) */ + const_le32(0xeafffffe), /* (spin) */ + const_le32(0xeafffffe), /* (spin) */ + const_le32(0xe1b0f00e), /* movs pc, lr ;SMC exception return */ + const_le32(0xeafffffe), /* (spin) */ + const_le32(0xeafffffe), /* (spin) */ + const_le32(0xeafffffe), /* (spin) */ + const_le32(0xeafffffe), /* (spin) */ + const_le32(0xeafffffe) /* (spin) */ }; - uint32_t board_setup_blob[] = { + const uint32_t board_setup_blob[] = { /* board setup addr */ - 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */ - 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */ - 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */ - 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */ - 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ - 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ - 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */ - 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ - 0xe1a0100e, /* mov r1, lr ;save LR across SMC */ - 0xe1600070, /* smc #0 ;call monitor to flush SCR */ - 0xe1a0f001, /* mov pc, r1 ;return */ + const_le32(0xee110f51), /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */ + const_le32(0xe3800b03), /* orr r0, #0xc00 ;set CP11, CP10 */ + const_le32(0xee010f51), /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */ + const_le32(0xe3a00e00 + (mvbar_addr >> 4)), /* mov r0, #mvbar_addr */ + const_le32(0xee0c0f30), /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */ + const_le32(0xee110f11), /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */ + const_le32(0xe3800031), /* orr r0, #0x31 ;enable AW, FW, NS */ + const_le32(0xee010f11), /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */ + const_le32(0xe1a0100e), /* mov r1, lr ;save LR across SMC */ + const_le32(0xe1600070), /* smc #0 ;call monitor to flush SCR */ + const_le32(0xe1a0f001) /* mov pc, r1 ;return */ }; /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */ @@ -259,15 +258,8 @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr) || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr)); - for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) { - mvbar_blob[n] = tswap32(mvbar_blob[n]); - } rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob), mvbar_addr, as); - - for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { - board_setup_blob[n] = tswap32(board_setup_blob[n]); - } rom_add_blob_fixed_as("board-setup", board_setup_blob, sizeof(board_setup_blob), info->board_setup_addr, as); }