From patchwork Tue Dec 20 02:47:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635931 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB95CC10F1D for ; Tue, 20 Dec 2022 02:47:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229977AbiLTCr3 (ORCPT ); Mon, 19 Dec 2022 21:47:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232883AbiLTCr1 (ORCPT ); Mon, 19 Dec 2022 21:47:27 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 507F513D65 for ; Mon, 19 Dec 2022 18:47:26 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id z26so16560915lfu.8 for ; Mon, 19 Dec 2022 18:47:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ms1zUNlDRsohNrXvw0gNoQaDLt0r2JwKikY8Nms/5Pg=; b=kRooxlmCt/VjLbn5kXtyZKyPGe5+A3FDiF+jq65Tdgmhbe+UCcE63dQ7X+WB5QoYRg 9polnWe/Qp1zCb1Ukd38mrBDIKIxBFREoxY1xcfHE0jWFlIHZKEgdhI/bNMuUKVDzBub GFSWoiSCcnMQgq1VbJbR+/kC72w6JTByeAm0k52kCyKc9fk4wBA1dYk2Km1pJCxSEtgi taU1VXe4B03su4JXTnLjP5JwZb8ngkRH3//8Kljn4cF+c0/J1CsAYV0FqGd8v/RgCQrr MmNfl6u9jANde8tBC8IoCuuzLdB7cYeInXW5Qx6kCKI50hdZuPsbVJuXjxXoMAPWOmEx WWqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ms1zUNlDRsohNrXvw0gNoQaDLt0r2JwKikY8Nms/5Pg=; b=wZttzORWn7T50kv5Y3PP43Nz51V6rv/OA7NRPlOrA5nyLC77BXxicK5oRRRECHPrTz 4Zi01Lld72thFwh+cuLtVyMECWrtNch/Yd86fA7Kmth9oReWCaM81mZSxj8+QysawORr URAqd4bqkngcu9hmkOoA99Zwp7X7O86MRA961CqOF2wMFMiKfY0YnCCFCEBuTQ/wBYfn 5P96U0WPaRI6DYp2/w8aX3ZkpDY2FVZzsr8artpGimjitm8VfyfQ/Zbk4AuaP7zeri/+ /HK5oB5a/iBzNw85ajFowdtBlKt0NbGHK8FX+DXul1LhmQHoplYI90acX1+jNa7JOsm6 8Qwg== X-Gm-Message-State: ANoB5pmLIddYTjAl9o84NN3ihS5tBXXEbVmBw06gxIr9eLC+DDGzq8nM H7kzXT0TN3ujWErZNaTILcb4DA== X-Google-Smtp-Source: AA0mqf4yjU9amk5WZAyYKV+jkCrn8WwniNKlWzMxdJXpdLB/Q3UrJzXfkLS4i0W6kekMcPYdSTbBng== X-Received: by 2002:a05:6512:1599:b0:4b6:f119:c820 with SMTP id bp25-20020a056512159900b004b6f119c820mr10407208lfb.40.1671504445926; Mon, 19 Dec 2022 18:47:25 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id e13-20020a05651236cd00b004b5a85e369asm1274866lfs.252.2022.12.19.18.47.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 18:47:25 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 04/15] thermal/drivers/tsens: Drop unnecessary hw_ids Date: Tue, 20 Dec 2022 04:47:10 +0200 Message-Id: <20221220024721.947147-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> References: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The tsens driver defaults to using hw_id equal to the index of the sensor. Thus it is superfluous to declare such hw_id arrays. Drop such arrays from mdm9607 and msm8976 data. Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 1 - drivers/thermal/qcom/tsens-v1.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 04d012e4f728..0bc4e5cec184 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -635,7 +635,6 @@ static const struct tsens_ops ops_9607 = { struct tsens_plat_data data_9607 = { .num_sensors = 5, .ops = &ops_9607, - .hw_ids = (unsigned int []){ 0, 1, 2, 3, 4 }, .feat = &tsens_v0_1_feat, .fields = tsens_v0_1_regfields, }; diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 1d7f8a80bd13..96ef12d47bff 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -387,7 +387,6 @@ static const struct tsens_ops ops_8976 = { struct tsens_plat_data data_8976 = { .num_sensors = 11, .ops = &ops_8976, - .hw_ids = (unsigned int[]){0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, .feat = &tsens_v1_feat, .fields = tsens_v1_regfields, }; From patchwork Tue Dec 20 02:47:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635930 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CD0CC46467 for ; Tue, 20 Dec 2022 02:47:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232809AbiLTCrb (ORCPT ); Mon, 19 Dec 2022 21:47:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39246 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232911AbiLTCr3 (ORCPT ); Mon, 19 Dec 2022 21:47:29 -0500 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 211B513CC6 for ; Mon, 19 Dec 2022 18:47:28 -0800 (PST) Received: by mail-lf1-x12a.google.com with SMTP id p36so16543098lfa.12 for ; Mon, 19 Dec 2022 18:47:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V7pw5sy4GHoiVeao2U3KoW+RiJYHiL2flqfvF1Vr6T4=; b=Ahu6umBtsTAmFKHZc3zRr5TH5jpmUzw+al7//r4BVR7m3nd8s1fOQy2Ontgl1d1QtI EBgwf+vJa4Fl5LTOL96I1GguYyGQlwnEXubG20x4KbNa8eaEWmVvF2FHFDuQer/+hhiE aKu9siy2lzbqTuYZ8Pt/wn+em71CLqEVutvdIFHIvl5ogKUlwA4FqYDGIkfhiH+jfTUg Dc+fd99M4p6xzzdtUAD6cO8ozXnTMYzX348l13XS9xC7v20fAak2MBGE4HdMVtwAEjRd xU7r94+B6y9En4xPIT+UDlhUKZtGV9HsQxcnBTAbN6C1V6Va0jTw1Y7ULMJmVZ4MXnfU +5gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V7pw5sy4GHoiVeao2U3KoW+RiJYHiL2flqfvF1Vr6T4=; b=2Wo5CWXOx0RvWufvzfjnZsBr08sMsenhhwaV5/GydoBl1fXzU89kkiKU5djHt+TuTA hhDR/z3AE+0EwELKNTcxMqDUD4T2eErUcQkMPZhzXFN4NrnCEM1xOjhGVuifSNp4L9K9 b31ibQhuVjP0oYKzO3SGf3WngVFn3Xi9NC8Uz4fqy/BsXTfSDilMn1J8Mqs3MsUaiB6v GF+TzZ0KoNCp9rkn5mijx6m2Km0dfddMFCMRwnFhbSX0tf2+7NmB3QL89eePIYOTlI64 PSCUbwwYeaCoEnFlkEPZMhM9Q61HCT7thstjiIejPxl5UuVCK92WYxtj2Qcvb7F6d3KM fi3w== X-Gm-Message-State: ANoB5pk+cpTsfXirJ4T23djixqQ4hGdnI0lfR5hBk5mZZupFL7IMFqKk obuo1SXPIQaieh0WpB2F1TAQAw== X-Google-Smtp-Source: AA0mqf5GbLoYnbfWia4zjxfzB3sEDJ4IbFrXh7Q292Wg1oMTGpA+nHPBXwyXqpdrqLpX8yrsHT8R4g== X-Received: by 2002:a05:6512:3e06:b0:4b5:9bfa:801a with SMTP id i6-20020a0565123e0600b004b59bfa801amr14031302lfv.46.1671504447678; Mon, 19 Dec 2022 18:47:27 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id e13-20020a05651236cd00b004b5a85e369asm1274866lfs.252.2022.12.19.18.47.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 18:47:27 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v3 06/15] thermal/drivers/tsens: Sort out msm8976 vs msm8956 data Date: Tue, 20 Dec 2022 04:47:12 +0200 Message-Id: <20221220024721.947147-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> References: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Tsens driver mentions that msm8976 data should be used for both msm8976 and msm8956 SoCs. This is not quite correct, as according to the vendor kernels, msm8976 should use standard slope values (3200), while msm8956 really uses the slope values found in the driver. Add separate compatibility string for msm8956, move slope value overrides to the corresponding init function and use the standard compute_intercept_slope() function for both platforms. Fixes: 0e580290170d ("thermal: qcom: tsens-v1: Add support for MSM8956 and MSM8976") Cc: AngeloGioacchino Del Regno Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v1.c | 56 ++++++++++++++++++--------------- drivers/thermal/qcom/tsens.c | 3 ++ drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 34 insertions(+), 27 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index a7f53966156b..83c2853546d0 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -137,30 +137,6 @@ #define CAL_SEL_MASK 7 #define CAL_SEL_SHIFT 0 -static void compute_intercept_slope_8976(struct tsens_priv *priv, - u32 *p1, u32 *p2, u32 mode) -{ - int i; - - priv->sensor[0].slope = 3313; - priv->sensor[1].slope = 3275; - priv->sensor[2].slope = 3320; - priv->sensor[3].slope = 3246; - priv->sensor[4].slope = 3279; - priv->sensor[5].slope = 3257; - priv->sensor[6].slope = 3234; - priv->sensor[7].slope = 3269; - priv->sensor[8].slope = 3255; - priv->sensor[9].slope = 3239; - priv->sensor[10].slope = 3286; - - for (i = 0; i < priv->num_sensors; i++) { - priv->sensor[i].offset = (p1[i] * SLOPE_FACTOR) - - (CAL_DEGC_PT1 * - priv->sensor[i].slope); - } -} - static int calibrate_v1(struct tsens_priv *priv) { u32 base0 = 0, base1 = 0; @@ -286,7 +262,7 @@ static int calibrate_8976(struct tsens_priv *priv) break; } - compute_intercept_slope_8976(priv, p1, p2, mode); + compute_intercept_slope(priv, p1, p2, mode); kfree(qfprom_cdata); return 0; @@ -360,6 +336,22 @@ static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0), }; +static int __init init_8956(struct tsens_priv *priv) { + priv->sensor[0].slope = 3313; + priv->sensor[1].slope = 3275; + priv->sensor[2].slope = 3320; + priv->sensor[3].slope = 3246; + priv->sensor[4].slope = 3279; + priv->sensor[5].slope = 3257; + priv->sensor[6].slope = 3234; + priv->sensor[7].slope = 3269; + priv->sensor[8].slope = 3255; + priv->sensor[9].slope = 3239; + priv->sensor[10].slope = 3286; + + return init_common(priv); +} + static const struct tsens_ops ops_generic_v1 = { .init = init_common, .calibrate = calibrate_v1, @@ -372,13 +364,25 @@ struct tsens_plat_data data_tsens_v1 = { .fields = tsens_v1_regfields, }; +static const struct tsens_ops ops_8956 = { + .init = init_8956, + .calibrate = calibrate_8976, + .get_temp = get_temp_tsens_valid, +}; + +struct tsens_plat_data data_8956 = { + .num_sensors = 11, + .ops = &ops_8956, + .feat = &tsens_v1_feat, + .fields = tsens_v1_regfields, +}; + static const struct tsens_ops ops_8976 = { .init = init_common, .calibrate = calibrate_8976, .get_temp = get_temp_tsens_valid, }; -/* Valid for both MSM8956 and MSM8976. */ struct tsens_plat_data data_8976 = { .num_sensors = 11, .ops = &ops_8976, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index b5b136ff323f..b191e19df93d 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -983,6 +983,9 @@ static const struct of_device_id tsens_table[] = { }, { .compatible = "qcom,msm8939-tsens", .data = &data_8939, + }, { + .compatible = "qcom,msm8956-tsens", + .data = &data_8956, }, { .compatible = "qcom,msm8960-tsens", .data = &data_8960, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 899af128855f..7dd5fc246894 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -594,7 +594,7 @@ extern struct tsens_plat_data data_8960; extern struct tsens_plat_data data_8916, data_8939, data_8974, data_9607; /* TSENS v1 targets */ -extern struct tsens_plat_data data_tsens_v1, data_8976; +extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956; /* TSENS v2 targets */ extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; From patchwork Tue Dec 20 02:47:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635929 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C77A4C4708E for ; Tue, 20 Dec 2022 02:47:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232589AbiLTCrd (ORCPT ); Mon, 19 Dec 2022 21:47:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232897AbiLTCrc (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id e13-20020a05651236cd00b004b5a85e369asm1274866lfs.252.2022.12.19.18.47.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 18:47:29 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Shawn Guo , Bryan O'Donoghue Subject: [PATCH v3 08/15] thermal/drivers/tsens: Drop single-cell code for msm8939 Date: Tue, 20 Dec 2022 04:47:14 +0200 Message-Id: <20221220024721.947147-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> References: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org There is no dtsi file for msm8939 in the kernel sources. Drop the compatibility with unofficial dtsi and remove support for handling the single-cell calibration data on msm8939. Cc: Shawn Guo Cc: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 146 ++---------------------------- 1 file changed, 7 insertions(+), 139 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 7f87b403c6fa..8f1ea7075354 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -48,63 +48,6 @@ #define MSM8916_CAL_SEL_MASK 0xe0000000 #define MSM8916_CAL_SEL_SHIFT 29 -/* eeprom layout data for 8939 */ -#define MSM8939_BASE0_MASK 0x000000ff -#define MSM8939_BASE1_MASK 0xff000000 -#define MSM8939_BASE0_SHIFT 0 -#define MSM8939_BASE1_SHIFT 24 - -#define MSM8939_S0_P1_MASK 0x000001f8 -#define MSM8939_S1_P1_MASK 0x001f8000 -#define MSM8939_S2_P1_MASK_0_4 0xf8000000 -#define MSM8939_S2_P1_MASK_5 0x00000001 -#define MSM8939_S3_P1_MASK 0x00001f80 -#define MSM8939_S4_P1_MASK 0x01f80000 -#define MSM8939_S5_P1_MASK 0x00003f00 -#define MSM8939_S6_P1_MASK 0x03f00000 -#define MSM8939_S7_P1_MASK 0x0000003f -#define MSM8939_S8_P1_MASK 0x0003f000 -#define MSM8939_S9_P1_MASK 0x07e00000 - -#define MSM8939_S0_P2_MASK 0x00007e00 -#define MSM8939_S1_P2_MASK 0x07e00000 -#define MSM8939_S2_P2_MASK 0x0000007e -#define MSM8939_S3_P2_MASK 0x0007e000 -#define MSM8939_S4_P2_MASK 0x7e000000 -#define MSM8939_S5_P2_MASK 0x000fc000 -#define MSM8939_S6_P2_MASK 0xfc000000 -#define MSM8939_S7_P2_MASK 0x00000fc0 -#define MSM8939_S8_P2_MASK 0x00fc0000 -#define MSM8939_S9_P2_MASK_0_4 0xf8000000 -#define MSM8939_S9_P2_MASK_5 0x00002000 - -#define MSM8939_S0_P1_SHIFT 3 -#define MSM8939_S1_P1_SHIFT 15 -#define MSM8939_S2_P1_SHIFT_0_4 27 -#define MSM8939_S2_P1_SHIFT_5 0 -#define MSM8939_S3_P1_SHIFT 7 -#define MSM8939_S4_P1_SHIFT 19 -#define MSM8939_S5_P1_SHIFT 8 -#define MSM8939_S6_P1_SHIFT 20 -#define MSM8939_S7_P1_SHIFT 0 -#define MSM8939_S8_P1_SHIFT 12 -#define MSM8939_S9_P1_SHIFT 21 - -#define MSM8939_S0_P2_SHIFT 9 -#define MSM8939_S1_P2_SHIFT 21 -#define MSM8939_S2_P2_SHIFT 1 -#define MSM8939_S3_P2_SHIFT 13 -#define MSM8939_S4_P2_SHIFT 25 -#define MSM8939_S5_P2_SHIFT 14 -#define MSM8939_S6_P2_SHIFT 26 -#define MSM8939_S7_P2_SHIFT 6 -#define MSM8939_S8_P2_SHIFT 18 -#define MSM8939_S9_P2_SHIFT_0_4 27 -#define MSM8939_S9_P2_SHIFT_5 13 - -#define MSM8939_CAL_SEL_MASK 0x7 -#define MSM8939_CAL_SEL_SHIFT 0 - /* eeprom layout data for 8974 */ #define BASE1_MASK 0xff #define S0_P1_MASK 0x3f00 @@ -284,81 +227,6 @@ static int calibrate_8916(struct tsens_priv *priv) return 0; } -static int calibrate_8939(struct tsens_priv *priv) -{ - int base0 = 0, base1 = 0, i; - u32 p1[10], p2[10]; - int mode = 0; - u32 *qfprom_cdata; - u32 cdata[6]; - int ret; - - ret = tsens_calibrate_common(priv); - if (!ret) - return 0; - - qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); - if (IS_ERR(qfprom_cdata)) - return PTR_ERR(qfprom_cdata); - - /* Mapping between qfprom nvmem and calibration data */ - cdata[0] = qfprom_cdata[12]; - cdata[1] = qfprom_cdata[13]; - cdata[2] = qfprom_cdata[0]; - cdata[3] = qfprom_cdata[1]; - cdata[4] = qfprom_cdata[22]; - cdata[5] = qfprom_cdata[21]; - - mode = (cdata[0] & MSM8939_CAL_SEL_MASK) >> MSM8939_CAL_SEL_SHIFT; - dev_dbg(priv->dev, "calibration mode is %d\n", mode); - - switch (mode) { - case TWO_PT_CALIB: - base1 = (cdata[3] & MSM8939_BASE1_MASK) >> MSM8939_BASE1_SHIFT; - p2[0] = (cdata[0] & MSM8939_S0_P2_MASK) >> MSM8939_S0_P2_SHIFT; - p2[1] = (cdata[0] & MSM8939_S1_P2_MASK) >> MSM8939_S1_P2_SHIFT; - p2[2] = (cdata[1] & MSM8939_S2_P2_MASK) >> MSM8939_S2_P2_SHIFT; - p2[3] = (cdata[1] & MSM8939_S3_P2_MASK) >> MSM8939_S3_P2_SHIFT; - p2[4] = (cdata[1] & MSM8939_S4_P2_MASK) >> MSM8939_S4_P2_SHIFT; - p2[5] = (cdata[2] & MSM8939_S5_P2_MASK) >> MSM8939_S5_P2_SHIFT; - p2[6] = (cdata[2] & MSM8939_S6_P2_MASK) >> MSM8939_S6_P2_SHIFT; - p2[7] = (cdata[3] & MSM8939_S7_P2_MASK) >> MSM8939_S7_P2_SHIFT; - p2[8] = (cdata[3] & MSM8939_S8_P2_MASK) >> MSM8939_S8_P2_SHIFT; - p2[9] = (cdata[4] & MSM8939_S9_P2_MASK_0_4) >> MSM8939_S9_P2_SHIFT_0_4; - p2[9] |= ((cdata[5] & MSM8939_S9_P2_MASK_5) >> MSM8939_S9_P2_SHIFT_5) << 5; - for (i = 0; i < priv->num_sensors; i++) - p2[i] = (base1 + p2[i]) << 2; - fallthrough; - case ONE_PT_CALIB2: - base0 = (cdata[2] & MSM8939_BASE0_MASK) >> MSM8939_BASE0_SHIFT; - p1[0] = (cdata[0] & MSM8939_S0_P1_MASK) >> MSM8939_S0_P1_SHIFT; - p1[1] = (cdata[0] & MSM8939_S1_P1_MASK) >> MSM8939_S1_P1_SHIFT; - p1[2] = (cdata[0] & MSM8939_S2_P1_MASK_0_4) >> MSM8939_S2_P1_SHIFT_0_4; - p1[2] |= ((cdata[1] & MSM8939_S2_P1_MASK_5) >> MSM8939_S2_P1_SHIFT_5) << 5; - p1[3] = (cdata[1] & MSM8939_S3_P1_MASK) >> MSM8939_S3_P1_SHIFT; - p1[4] = (cdata[1] & MSM8939_S4_P1_MASK) >> MSM8939_S4_P1_SHIFT; - p1[5] = (cdata[2] & MSM8939_S5_P1_MASK) >> MSM8939_S5_P1_SHIFT; - p1[6] = (cdata[2] & MSM8939_S6_P1_MASK) >> MSM8939_S6_P1_SHIFT; - p1[7] = (cdata[3] & MSM8939_S7_P1_MASK) >> MSM8939_S7_P1_SHIFT; - p1[8] = (cdata[3] & MSM8939_S8_P1_MASK) >> MSM8939_S8_P1_SHIFT; - p1[9] = (cdata[4] & MSM8939_S9_P1_MASK) >> MSM8939_S9_P1_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p1[i] = ((base0) + p1[i]) << 2; - break; - default: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] = 500; - p2[i] = 780; - } - break; - } - - compute_intercept_slope(priv, p1, p2, mode); - kfree(qfprom_cdata); - - return 0; -} - static int calibrate_8974(struct tsens_priv *priv) { int base1 = 0, base2 = 0, i; @@ -598,6 +466,12 @@ static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = { [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0), }; +static const struct tsens_ops ops_v0_1 = { + .init = init_common, + .calibrate = tsens_calibrate_common, + .get_temp = get_temp_common, +}; + static const struct tsens_ops ops_8916 = { .init = init_common, .calibrate = calibrate_8916, @@ -613,15 +487,9 @@ struct tsens_plat_data data_8916 = { .fields = tsens_v0_1_regfields, }; -static const struct tsens_ops ops_8939 = { - .init = init_common, - .calibrate = calibrate_8939, - .get_temp = get_temp_common, -}; - struct tsens_plat_data data_8939 = { .num_sensors = 10, - .ops = &ops_8939, + .ops = &ops_v0_1, .hw_ids = (unsigned int []){ 0, 1, 2, 3, 5, 6, 7, 8, 9, 10 }, .feat = &tsens_v0_1_feat, From patchwork Tue Dec 20 02:47:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635928 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F771C54EBD for ; Tue, 20 Dec 2022 02:47:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232716AbiLTCre (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id e13-20020a05651236cd00b004b5a85e369asm1274866lfs.252.2022.12.19.18.47.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 18:47:30 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 09/15] thermal/drivers/tsens: Drop single-cell code for mdm9607 Date: Tue, 20 Dec 2022 04:47:15 +0200 Message-Id: <20221220024721.947147-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> References: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org There is no dtsi file for mdm9607 in the kernel sources. Drop the compatibility with unofficial dtsi and remove support for handling the single-cell calibration data on mdm9607. Cc: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 95 +------------------------------ 1 file changed, 1 insertion(+), 94 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 8f1ea7075354..caffcf9905b9 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -133,39 +133,6 @@ #define BIT_APPEND 0x3 -/* eeprom layout data for mdm9607 */ -#define MDM9607_BASE0_MASK 0x000000ff -#define MDM9607_BASE1_MASK 0x000ff000 -#define MDM9607_BASE0_SHIFT 0 -#define MDM9607_BASE1_SHIFT 12 - -#define MDM9607_S0_P1_MASK 0x00003f00 -#define MDM9607_S1_P1_MASK 0x03f00000 -#define MDM9607_S2_P1_MASK 0x0000003f -#define MDM9607_S3_P1_MASK 0x0003f000 -#define MDM9607_S4_P1_MASK 0x0000003f - -#define MDM9607_S0_P2_MASK 0x000fc000 -#define MDM9607_S1_P2_MASK 0xfc000000 -#define MDM9607_S2_P2_MASK 0x00000fc0 -#define MDM9607_S3_P2_MASK 0x00fc0000 -#define MDM9607_S4_P2_MASK 0x00000fc0 - -#define MDM9607_S0_P1_SHIFT 8 -#define MDM9607_S1_P1_SHIFT 20 -#define MDM9607_S2_P1_SHIFT 0 -#define MDM9607_S3_P1_SHIFT 12 -#define MDM9607_S4_P1_SHIFT 0 - -#define MDM9607_S0_P2_SHIFT 14 -#define MDM9607_S1_P2_SHIFT 26 -#define MDM9607_S2_P2_SHIFT 6 -#define MDM9607_S3_P2_SHIFT 18 -#define MDM9607_S4_P2_SHIFT 6 - -#define MDM9607_CAL_SEL_MASK 0x00700000 -#define MDM9607_CAL_SEL_SHIFT 20 - static int calibrate_8916(struct tsens_priv *priv) { int base0 = 0, base1 = 0, i; @@ -363,60 +330,6 @@ static int calibrate_8974(struct tsens_priv *priv) return 0; } -static int calibrate_9607(struct tsens_priv *priv) -{ - int base, i; - u32 p1[5], p2[5]; - int mode = 0; - u32 *qfprom_cdata; - int ret; - - ret = tsens_calibrate_common(priv); - if (!ret) - return 0; - - qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); - if (IS_ERR(qfprom_cdata)) - return PTR_ERR(qfprom_cdata); - - mode = (qfprom_cdata[2] & MDM9607_CAL_SEL_MASK) >> MDM9607_CAL_SEL_SHIFT; - dev_dbg(priv->dev, "calibration mode is %d\n", mode); - - switch (mode) { - case TWO_PT_CALIB: - base = (qfprom_cdata[2] & MDM9607_BASE1_MASK) >> MDM9607_BASE1_SHIFT; - p2[0] = (qfprom_cdata[0] & MDM9607_S0_P2_MASK) >> MDM9607_S0_P2_SHIFT; - p2[1] = (qfprom_cdata[0] & MDM9607_S1_P2_MASK) >> MDM9607_S1_P2_SHIFT; - p2[2] = (qfprom_cdata[1] & MDM9607_S2_P2_MASK) >> MDM9607_S2_P2_SHIFT; - p2[3] = (qfprom_cdata[1] & MDM9607_S3_P2_MASK) >> MDM9607_S3_P2_SHIFT; - p2[4] = (qfprom_cdata[2] & MDM9607_S4_P2_MASK) >> MDM9607_S4_P2_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p2[i] = ((base + p2[i]) << 2); - fallthrough; - case ONE_PT_CALIB2: - base = (qfprom_cdata[0] & MDM9607_BASE0_MASK); - p1[0] = (qfprom_cdata[0] & MDM9607_S0_P1_MASK) >> MDM9607_S0_P1_SHIFT; - p1[1] = (qfprom_cdata[0] & MDM9607_S1_P1_MASK) >> MDM9607_S1_P1_SHIFT; - p1[2] = (qfprom_cdata[1] & MDM9607_S2_P1_MASK) >> MDM9607_S2_P1_SHIFT; - p1[3] = (qfprom_cdata[1] & MDM9607_S3_P1_MASK) >> MDM9607_S3_P1_SHIFT; - p1[4] = (qfprom_cdata[2] & MDM9607_S4_P1_MASK) >> MDM9607_S4_P1_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p1[i] = ((base + p1[i]) << 2); - break; - default: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] = 500; - p2[i] = 780; - } - break; - } - - compute_intercept_slope(priv, p1, p2, mode); - kfree(qfprom_cdata); - - return 0; -} - /* v0.1: 8916, 8939, 8974, 9607 */ static struct tsens_features tsens_v0_1_feat = { @@ -509,15 +422,9 @@ struct tsens_plat_data data_8974 = { .fields = tsens_v0_1_regfields, }; -static const struct tsens_ops ops_9607 = { - .init = init_common, - .calibrate = calibrate_9607, - .get_temp = get_temp_common, -}; - struct tsens_plat_data data_9607 = { .num_sensors = 5, - .ops = &ops_9607, + .ops = &ops_v0_1, .feat = &tsens_v0_1_feat, .fields = tsens_v0_1_regfields, }; From patchwork Tue Dec 20 02:47:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3A37C3DA78 for ; Tue, 20 Dec 2022 02:47:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232946AbiLTCrk (ORCPT ); Mon, 19 Dec 2022 21:47:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39474 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232969AbiLTCrg (ORCPT ); Mon, 19 Dec 2022 21:47:36 -0500 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3D60F13DE5 for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id e13-20020a05651236cd00b004b5a85e369asm1274866lfs.252.2022.12.19.18.47.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 18:47:31 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v3 10/15] thermal/drivers/tsens: Drop single-cell code for msm8976/msm8956 Date: Tue, 20 Dec 2022 04:47:16 +0200 Message-Id: <20221220024721.947147-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> References: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org There is no dtsi file for msm8976 in the kernel sources. Drop the compatibility with unofficial dtsi and remove support for handling the single-cell calibration data on msm8976. Cc: AngeloGioacchino Del Regno Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v1.c | 126 +------------------------------- 1 file changed, 2 insertions(+), 124 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 89955522041d..9151c1043a11 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -21,63 +21,6 @@ #define TM_HIGH_LOW_INT_STATUS_OFF 0x0088 #define TM_HIGH_LOW_Sn_INT_THRESHOLD_OFF 0x0090 -/* eeprom layout data for msm8956/76 (v1) */ -#define MSM8976_BASE0_MASK 0xff -#define MSM8976_BASE1_MASK 0xff -#define MSM8976_BASE1_SHIFT 8 - -#define MSM8976_S0_P1_MASK 0x3f00 -#define MSM8976_S1_P1_MASK 0x3f00000 -#define MSM8976_S2_P1_MASK 0x3f -#define MSM8976_S3_P1_MASK 0x3f000 -#define MSM8976_S4_P1_MASK 0x3f00 -#define MSM8976_S5_P1_MASK 0x3f00000 -#define MSM8976_S6_P1_MASK 0x3f -#define MSM8976_S7_P1_MASK 0x3f000 -#define MSM8976_S8_P1_MASK 0x1f8 -#define MSM8976_S9_P1_MASK 0x1f8000 -#define MSM8976_S10_P1_MASK 0xf8000000 -#define MSM8976_S10_P1_MASK_1 0x1 - -#define MSM8976_S0_P2_MASK 0xfc000 -#define MSM8976_S1_P2_MASK 0xfc000000 -#define MSM8976_S2_P2_MASK 0xfc0 -#define MSM8976_S3_P2_MASK 0xfc0000 -#define MSM8976_S4_P2_MASK 0xfc000 -#define MSM8976_S5_P2_MASK 0xfc000000 -#define MSM8976_S6_P2_MASK 0xfc0 -#define MSM8976_S7_P2_MASK 0xfc0000 -#define MSM8976_S8_P2_MASK 0x7e00 -#define MSM8976_S9_P2_MASK 0x7e00000 -#define MSM8976_S10_P2_MASK 0x7e - -#define MSM8976_S0_P1_SHIFT 8 -#define MSM8976_S1_P1_SHIFT 20 -#define MSM8976_S2_P1_SHIFT 0 -#define MSM8976_S3_P1_SHIFT 12 -#define MSM8976_S4_P1_SHIFT 8 -#define MSM8976_S5_P1_SHIFT 20 -#define MSM8976_S6_P1_SHIFT 0 -#define MSM8976_S7_P1_SHIFT 12 -#define MSM8976_S8_P1_SHIFT 3 -#define MSM8976_S9_P1_SHIFT 15 -#define MSM8976_S10_P1_SHIFT 27 -#define MSM8976_S10_P1_SHIFT_1 0 - -#define MSM8976_S0_P2_SHIFT 14 -#define MSM8976_S1_P2_SHIFT 26 -#define MSM8976_S2_P2_SHIFT 6 -#define MSM8976_S3_P2_SHIFT 18 -#define MSM8976_S4_P2_SHIFT 14 -#define MSM8976_S5_P2_SHIFT 26 -#define MSM8976_S6_P2_SHIFT 6 -#define MSM8976_S7_P2_SHIFT 18 -#define MSM8976_S8_P2_SHIFT 9 -#define MSM8976_S9_P2_SHIFT 21 -#define MSM8976_S10_P2_SHIFT 1 - -#define MSM8976_CAL_SEL_MASK 0x3 - /* eeprom layout data for qcs404/405 (v1) */ #define BASE0_MASK 0x000007f8 #define BASE1_MASK 0x0007f800 @@ -207,71 +150,6 @@ static int calibrate_v1(struct tsens_priv *priv) return 0; } -static int calibrate_8976(struct tsens_priv *priv) -{ - int base0 = 0, base1 = 0, i; - u32 p1[11], p2[11]; - int mode = 0, tmp = 0; - u32 *qfprom_cdata; - - qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); - if (IS_ERR(qfprom_cdata)) - return PTR_ERR(qfprom_cdata); - - mode = (qfprom_cdata[4] & MSM8976_CAL_SEL_MASK); - dev_dbg(priv->dev, "calibration mode is %d\n", mode); - - switch (mode) { - case TWO_PT_CALIB: - base1 = (qfprom_cdata[2] & MSM8976_BASE1_MASK) >> MSM8976_BASE1_SHIFT; - p2[0] = (qfprom_cdata[0] & MSM8976_S0_P2_MASK) >> MSM8976_S0_P2_SHIFT; - p2[1] = (qfprom_cdata[0] & MSM8976_S1_P2_MASK) >> MSM8976_S1_P2_SHIFT; - p2[2] = (qfprom_cdata[1] & MSM8976_S2_P2_MASK) >> MSM8976_S2_P2_SHIFT; - p2[3] = (qfprom_cdata[1] & MSM8976_S3_P2_MASK) >> MSM8976_S3_P2_SHIFT; - p2[4] = (qfprom_cdata[2] & MSM8976_S4_P2_MASK) >> MSM8976_S4_P2_SHIFT; - p2[5] = (qfprom_cdata[2] & MSM8976_S5_P2_MASK) >> MSM8976_S5_P2_SHIFT; - p2[6] = (qfprom_cdata[3] & MSM8976_S6_P2_MASK) >> MSM8976_S6_P2_SHIFT; - p2[7] = (qfprom_cdata[3] & MSM8976_S7_P2_MASK) >> MSM8976_S7_P2_SHIFT; - p2[8] = (qfprom_cdata[4] & MSM8976_S8_P2_MASK) >> MSM8976_S8_P2_SHIFT; - p2[9] = (qfprom_cdata[4] & MSM8976_S9_P2_MASK) >> MSM8976_S9_P2_SHIFT; - p2[10] = (qfprom_cdata[5] & MSM8976_S10_P2_MASK) >> MSM8976_S10_P2_SHIFT; - - for (i = 0; i < priv->num_sensors; i++) - p2[i] = ((base1 + p2[i]) << 2); - fallthrough; - case ONE_PT_CALIB2: - base0 = qfprom_cdata[0] & MSM8976_BASE0_MASK; - p1[0] = (qfprom_cdata[0] & MSM8976_S0_P1_MASK) >> MSM8976_S0_P1_SHIFT; - p1[1] = (qfprom_cdata[0] & MSM8976_S1_P1_MASK) >> MSM8976_S1_P1_SHIFT; - p1[2] = (qfprom_cdata[1] & MSM8976_S2_P1_MASK) >> MSM8976_S2_P1_SHIFT; - p1[3] = (qfprom_cdata[1] & MSM8976_S3_P1_MASK) >> MSM8976_S3_P1_SHIFT; - p1[4] = (qfprom_cdata[2] & MSM8976_S4_P1_MASK) >> MSM8976_S4_P1_SHIFT; - p1[5] = (qfprom_cdata[2] & MSM8976_S5_P1_MASK) >> MSM8976_S5_P1_SHIFT; - p1[6] = (qfprom_cdata[3] & MSM8976_S6_P1_MASK) >> MSM8976_S6_P1_SHIFT; - p1[7] = (qfprom_cdata[3] & MSM8976_S7_P1_MASK) >> MSM8976_S7_P1_SHIFT; - p1[8] = (qfprom_cdata[4] & MSM8976_S8_P1_MASK) >> MSM8976_S8_P1_SHIFT; - p1[9] = (qfprom_cdata[4] & MSM8976_S9_P1_MASK) >> MSM8976_S9_P1_SHIFT; - p1[10] = (qfprom_cdata[4] & MSM8976_S10_P1_MASK) >> MSM8976_S10_P1_SHIFT; - tmp = (qfprom_cdata[5] & MSM8976_S10_P1_MASK_1) << MSM8976_S10_P1_SHIFT_1; - p1[10] |= tmp; - - for (i = 0; i < priv->num_sensors; i++) - p1[i] = (((base0) + p1[i]) << 2); - break; - default: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] = 500; - p2[i] = 780; - } - break; - } - - compute_intercept_slope(priv, p1, p2, mode); - kfree(qfprom_cdata); - - return 0; -} - /* v1.x: msm8956,8976,qcs404,405 */ static struct tsens_features tsens_v1_feat = { @@ -370,7 +248,7 @@ struct tsens_plat_data data_tsens_v1 = { static const struct tsens_ops ops_8956 = { .init = init_8956, - .calibrate = calibrate_8976, + .calibrate = tsens_calibrate_common, .get_temp = get_temp_tsens_valid, }; @@ -383,7 +261,7 @@ struct tsens_plat_data data_8956 = { static const struct tsens_ops ops_8976 = { .init = init_common, - .calibrate = calibrate_8976, + .calibrate = tsens_calibrate_common, .get_temp = get_temp_tsens_valid, }; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id e13-20020a05651236cd00b004b5a85e369asm1274866lfs.252.2022.12.19.18.47.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 18:47:34 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 13/15] arm64: dts: qcom: qcs404: specify per-sensor calibration cells Date: Tue, 20 Dec 2022 04:47:19 +0200 Message-Id: <20221220024721.947147-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> References: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 121 +++++++++++++++++++++++++-- 1 file changed, 116 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index a5324eecb50a..362764347006 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -366,13 +366,102 @@ qfprom: qfprom@a4000 { reg = <0x000a4000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0x1f8 0x14>; - }; cpr_efuse_speedbin: speedbin@13c { reg = <0x13c 0x4>; bits = <2 3>; }; + tsens_s0_p1: s0_p1@1f8 { + reg = <0x1f8 0x1>; + bits = <0 6>; + }; + tsens_s0_p2: s0_p2@1f8 { + reg = <0x1f8 0x2>; + bits = <6 6>; + }; + tsens_s1_p1: s1_p1@1f9 { + reg = <0x1f9 0x2>; + bits = <4 6>; + }; + tsens_s1_p2: s1_p2@1fa { + reg = <0x1fa 0x1>; + bits = <2 6>; + }; + tsens_s2_p1: s2_p1@1fb { + reg = <0x1fb 0x1>; + bits = <0 6>; + }; + tsens_s2_p2: s2_p2@1fb { + reg = <0x1fb 0x2>; + bits = <6 6>; + }; + tsens_s3_p1: s3_p1@1fc { + reg = <0x1fc 0x2>; + bits = <4 6>; + }; + tsens_s3_p2: s3_p2@1fd { + reg = <0x1fd 0x1>; + bits = <2 6>; + }; + tsens_s4_p1: s4_p1@1fe { + reg = <0x1fe 0x1>; + bits = <0 6>; + }; + tsens_s4_p2: s4_p2@1fe { + reg = <0x1fe 0x2>; + bits = <6 6>; + }; + tsens_s5_p1: s5_p1@200 { + reg = <0x200 0x1>; + bits = <0 6>; + }; + tsens_s5_p2: s5_p2@200 { + reg = <0x200 0x2>; + bits = <6 6>; + }; + tsens_s6_p1: s6_p1@201 { + reg = <0x201 0x2>; + bits = <4 6>; + }; + tsens_s6_p2: s6_p2@202 { + reg = <0x202 0x1>; + bits = <2 6>; + }; + tsens_s7_p1: s7_p1@203 { + reg = <0x203 0x1>; + bits = <0 6>; + }; + tsens_s7_p2: s7_p2@203 { + reg = <0x203 0x2>; + bits = <6 6>; + }; + tsens_s8_p1: s8_p1@204 { + reg = <0x204 0x2>; + bits = <4 6>; + }; + tsens_s8_p2: s8_p2@205 { + reg = <0x205 0x1>; + bits = <2 6>; + }; + tsens_s9_p1: s9_p1@206 { + reg = <0x206 0x1>; + bits = <0 6>; + }; + tsens_s9_p2: s9_p2@206 { + reg = <0x206 0x2>; + bits = <6 6>; + }; + tsens_mode: mode@208 { + reg = <0x208 1>; + bits = <0 3>; + }; + tsens_base1: base1@208 { + reg = <0x208 2>; + bits = <3 8>; + }; + tsens_base2: base2@208 { + reg = <0x209 2>; + bits = <3 8>; + }; cpr_efuse_quot_offset1: qoffset1@231 { reg = <0x231 0x4>; bits = <4 7>; @@ -447,8 +536,30 @@ tsens: thermal-sensor@4a9000 { compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; reg = <0x004a9000 0x1000>, /* TM */ <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>; - nvmem-cell-names = "calib"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2"; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id e13-20020a05651236cd00b004b5a85e369asm1274866lfs.252.2022.12.19.18.47.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 18:47:36 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 15/15] ARM: dts: qcom-apq8084: specify per-sensor calibration cells Date: Tue, 20 Dec 2022 04:47:21 +0200 Message-Id: <20221220024721.947147-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> References: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8084.dtsi | 262 +++++++++++++++++++++++++++- 1 file changed, 256 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index fe30abfff90a..f0f788ac38f0 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -249,11 +249,209 @@ qfprom: qfprom@fc4bc000 { reg = <0xfc4bc000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_calib: calib@d0 { - reg = <0xd0 0x18>; + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 8>; }; - tsens_backup: backup@440 { - reg = <0x440 0x10>; + tsens_s0_p1: s0_p1@d1 { + reg = <0xd1 0x1>; + bits = <0 6>; + }; + tsens_s1_p1: s1_p1@d2 { + reg = <0xd1 0x2>; + bits = <6 6>; + }; + tsens_s2_p1: s2_p1@d2 { + reg = <0xd2 0x2>; + bits = <4 6>; + }; + tsens_s3_p1: s3_p1@d3 { + reg = <0xd3 0x1>; + bits = <2 6>; + }; + tsens_s4_p1: s4_p1@d4 { + reg = <0xd4 0x1>; + bits = <0 6>; + }; + tsens_s5_p1: s5_p1@d4 { + reg = <0xd4 0x2>; + bits = <6 6>; + }; + tsens_s6_p1: s6_p1@d5 { + reg = <0xd5 0x2>; + bits = <4 6>; + }; + tsens_s7_p1: s7_p1@d6 { + reg = <0xd6 0x1>; + bits = <2 6>; + }; + tsens_s8_p1: s8_p1@d7 { + reg = <0xd7 0x1>; + bits = <0 6>; + }; + tsens_mode: mode@d7 { + reg = <0xd7 0x1>; + bits = <6 2>; + }; + tsens_s9_p1: s9_p1@d8 { + reg = <0xd8 0x1>; + bits = <0 6>; + }; + tsens_s10_p1: s10_p1@d8 { + reg = <0xd8 0x2>; + bits = <6 6>; + }; + tsens_base2: base2@d9 { + reg = <0xd9 0x2>; + bits = <4 8>; + }; + tsens_s0_p2: s0_p2@da { + reg = <0xda 0x2>; + bits = <4 6>; + }; + tsens_s1_p2: s1_p2@db { + reg = <0xdb 0x1>; + bits = <2 6>; + }; + tsens_s2_p2: s2_p2@dc { + reg = <0xdc 0x1>; + bits = <0 6>; + }; + tsens_s3_p2: s3_p2@dc { + reg = <0xdc 0x2>; + bits = <6 6>; + }; + tsens_s4_p2: s4_p2@dd { + reg = <0xdd 0x2>; + bits = <4 6>; + }; + tsens_s5_p2: s5_p2@de { + reg = <0xde 0x2>; + bits = <2 6>; + }; + tsens_s6_p2: s6_p2@df { + reg = <0xdf 0x1>; + bits = <0 6>; + }; + tsens_s7_p2: s7_p2@e0 { + reg = <0xe0 0x1>; + bits = <0 6>; + }; + tsens_s8_p2: s8_p2@e0 { + reg = <0xe0 0x2>; + bits = <6 6>; + }; + tsens_s9_p2: s9_p2@e1 { + reg = <0xe1 0x2>; + bits = <4 6>; + }; + tsens_s10_p2: s10_p2@e2 { + reg = <0xe2 0x2>; + bits = <2 6>; + }; + tsens_s5_p2_backup: s5_p2_backup@e3 { + reg = <0xe3 0x2>; + bits = <0 6>; + }; + tsens_mode_backup: mode_backup@e3 { + reg = <0xe3 0x1>; + bits = <6 2>; + }; + tsens_s6_p2_backup: s6_p2_backup@e4 { + reg = <0xe4 0x1>; + bits = <0 6>; + }; + tsens_s7_p2_backup: s7_p2_backup@e4 { + reg = <0xe4 0x2>; + bits = <6 6>; + }; + tsens_s8_p2_backup: s8_p2_backup@e5 { + reg = <0xe5 0x2>; + bits = <4 6>; + }; + tsens_s9_p2_backup: s9_p2_backup@e6 { + reg = <0xe6 0x2>; + bits = <2 6>; + }; + tsens_s10_p2_backup: s10_p2_backup@e7 { + reg = <0xe7 0x1>; + bits = <0 6>; + }; + tsens_base1_backup: base1_backup@440 { + reg = <0x440 0x1>; + bits = <0 8>; + }; + tsens_s0_p1_backup: s0_p1_backup@441 { + reg = <0x441 0x1>; + bits = <0 6>; + }; + tsens_s1_p1_backup: s1_p1_backup@442 { + reg = <0x441 0x2>; + bits = <6 6>; + }; + tsens_s2_p1_backup: s2_p1_backup@442 { + reg = <0x442 0x2>; + bits = <4 6>; + }; + tsens_s3_p1_backup: s3_p1_backup@443 { + reg = <0x443 0x1>; + bits = <2 6>; + }; + tsens_s4_p1_backup: s4_p1_backup@444 { + reg = <0x444 0x1>; + bits = <0 6>; + }; + tsens_s5_p1_backup: s5_p1_backup@444 { + reg = <0x444 0x2>; + bits = <6 6>; + }; + tsens_s6_p1_backup: s6_p1_backup@445 { + reg = <0x445 0x2>; + bits = <4 6>; + }; + tsens_s7_p1_backup: s7_p1_backup@446 { + reg = <0x446 0x1>; + bits = <2 6>; + }; + tsens_use_backup: use_backup@447 { + reg = <0x447 0x1>; + bits = <5 3>; + }; + tsens_s8_p1_backup: s8_p1_backup@448 { + reg = <0x448 0x1>; + bits = <0 6>; + }; + tsens_s9_p1_backup: s9_p1_backup@448 { + reg = <0x448 0x2>; + bits = <6 6>; + }; + tsens_s10_p1_backup: s10_p1_backup@449 { + reg = <0x449 0x2>; + bits = <4 6>; + }; + tsens_base2_backup: base2_backup@44a { + reg = <0x44a 0x2>; + bits = <2 8>; + }; + tsens_s0_p2_backup: s0_p2_backup@44b { + reg = <0x44b 0x3>; + bits = <2 6>; + }; + tsens_s1_p2_backup: s1_p2_backup@44c { + reg = <0x44c 0x1>; + bits = <0 6>; + }; + tsens_s2_p2_backup: s2_p2_backup@44c { + reg = <0x44c 0x2>; + bits = <6 6>; + }; + tsens_s3_p2_backup: s3_p2_backup@44d { + reg = <0x44d 0x2>; + bits = <4 6>; + }; + tsens_s4_p2_backup: s4_p2_backup@44e { + reg = <0x44e 0x1>; + bits = <2 6>; }; }; @@ -261,8 +459,60 @@ tsens: thermal-sensor@fc4a8000 { compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; reg = <0xfc4a9000 0x1000>, /* TM */ <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>, + <&tsens_use_backup>, + <&tsens_mode_backup>, + <&tsens_base1_backup>, <&tsens_base2_backup>, + <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, + <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, + <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, + <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, + <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, + <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, + <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, + <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, + <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, + <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, + <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2", + "use_backup", + "mode_backup", + "base1_backup", "base2_backup", + "s0_p1_backup", "s0_p2_backup", + "s1_p1_backup", "s1_p2_backup", + "s2_p1_backup", "s2_p2_backup", + "s3_p1_backup", "s3_p2_backup", + "s4_p1_backup", "s4_p2_backup", + "s5_p1_backup", "s5_p2_backup", + "s6_p1_backup", "s6_p2_backup", + "s7_p1_backup", "s7_p2_backup", + "s8_p1_backup", "s8_p2_backup", + "s9_p1_backup", "s9_p2_backup", + "s10_p1_backup", "s10_p2_backup"; #qcom,sensors = <11>; interrupts = ; interrupt-names = "uplow";