From patchwork Wed Dec 21 00:02:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 635820 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48B0BC4332F for ; Wed, 21 Dec 2022 00:03:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234287AbiLUADC (ORCPT ); Tue, 20 Dec 2022 19:03:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44758 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234238AbiLUADB (ORCPT ); Tue, 20 Dec 2022 19:03:01 -0500 Received: from mail-wr1-x42a.google.com (mail-wr1-x42a.google.com [IPv6:2a00:1450:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 439A31C900; Tue, 20 Dec 2022 16:03:00 -0800 (PST) Received: by mail-wr1-x42a.google.com with SMTP id y16so13456597wrm.2; Tue, 20 Dec 2022 16:03:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=M1g/qK+wITcmMNBzaKxGBCpgwiK6fj9WTq342zlrl9U=; b=Ua0sxbOPrzWv+NNn2uxUgOEQEzqxLhlVwhO637MFvOZWWBlgRQH/rREgDkhXAl9y9b mIcOn1TuRwM4UwuxFF6hyc2pBvlrEsdsTSeEz7WFUgWRBaDZRP7f9NBE0UBXe7u/xpOg 3yiL3Cixg8QeJJgPEEMoaB0waB8s2MkBHW/aXXQH74ETLk31uLHJdskA91I3MnD7gZxQ zQqK5n7r+OYz06PbohEtHTNIIrzEjLXiwclY6QMGB1yut1YxmI8YNwh2L/SRWc37dMIN IAoOYRG71JYE/FuPib/NijuoDl1M6s0oxEVq8exQBmXAyQZJrmkvvJ4LvUj1KkllsT21 1+PQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=M1g/qK+wITcmMNBzaKxGBCpgwiK6fj9WTq342zlrl9U=; b=KH2jO9IGmflZOWMn7UXigkX73vkTVRP2QJqzx1y4wSWBrm/B7NXRkldmYRG9yin9v3 FuxJxgdAS80ym3AtsagFz97hQFw6oapINr4MIcoixDPM42Plk4JunvQsgsTp1ri0woYL EuPTYkS8Ru0WXyauurjddQS8D7663wpXm4g8PqtxHcpc/o0/rctXt0URP+UacjHWvCYN nieiTFbxMphwVAbSdcso/i5/eS4vagVpx0qii0g44cOgf8fEldqkMU2Oh+XqVs/qFSW1 RftlgQ0hXfnEbtw4nHrqjOJUh1yPYBmmuSWei9/uZFDFjbPZhO2qe7bh8LtzUp8XGGts T/tA== X-Gm-Message-State: ANoB5pmBfDsSJEnjnC/F9c1y1CsZAzOgtA1IDoImR7pws+GC5WteTYr7 CCufYbVpkZwfFfA5X5VvZKc= X-Google-Smtp-Source: AA0mqf49swmiA1NfsE48IIYpD/gm+EK08KkuDqNydVay+PXkoEPAOluFubQk/lNISxWQzkd4bPiYsw== X-Received: by 2002:adf:f3cd:0:b0:241:f95f:eef8 with SMTP id g13-20020adff3cd000000b00241f95feef8mr27395099wrp.11.1671580978710; Tue, 20 Dec 2022 16:02:58 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2501:c701:1595:a48c:95a8:15e0]) by smtp.gmail.com with ESMTPSA id f2-20020a5d50c2000000b002362f6fcaf5sm13740150wrt.48.2022.12.20.16.02.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 16:02:58 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 2/9] dt-bindings: interrupt-controller: irqc-rzg2l: Drop RZG2L_NMI macro Date: Wed, 21 Dec 2022 00:02:35 +0000 Message-Id: <20221221000242.340202-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar NMI interrupt is not an external interrupt as compared to IRQ0-7 and TINT0-31 on RZ/G2L SoC, so there is no need for RZG2L_NMI macro. Signed-off-by: Lad Prabhakar Acked-by: Krzysztof Kozlowski --- v1 -> v2 * New patch --- include/dt-bindings/interrupt-controller/irqc-rzg2l.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h index 34ce778885a1..dd2da795208d 100644 --- a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h +++ b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h @@ -9,9 +9,6 @@ #ifndef __DT_BINDINGS_IRQC_RZG2L_H #define __DT_BINDINGS_IRQC_RZG2L_H -/* NMI maps to SPI0 */ -#define RZG2L_NMI 0 - /* IRQ0-7 map to SPI1-8 */ #define RZG2L_IRQ0 1 #define RZG2L_IRQ1 2 From patchwork Wed Dec 21 00:02:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 635819 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D000C46467 for ; Wed, 21 Dec 2022 00:03:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234296AbiLUADD (ORCPT ); Tue, 20 Dec 2022 19:03:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234279AbiLUADC (ORCPT ); Tue, 20 Dec 2022 19:03:02 -0500 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63E531EEFD; Tue, 20 Dec 2022 16:03:01 -0800 (PST) Received: by mail-wr1-x42d.google.com with SMTP id y16so13456624wrm.2; Tue, 20 Dec 2022 16:03:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=za2L0CKEB7yf2ik8Iuj/BZryf3LCWxSxvd2XuC3OlRk=; b=X/t0b3H3+hjQwrCd7kME8ld6CwGzkx1Sjj3O8mKERT01ouSPCaqiklUT3UTBUCKSIh k8wZX0/dK4zJmDFAsw/LGHkn3BdI037YIjGcDUK6auDDqVPa6Z+Fjy2UyhVGpkvVmgAa rYeogGch+W0v2/YhTtRU5SLw55o8De8tcZUokc8bWTooFiVDsdXSBHfpLUwhPq9VpdNB rdYC0vRcXWsKsHMry5T5tis1+J7IrLaQUQEcvcvQme9stNtSFZaLbRCsRKxdSXJYg+wa LgTjrWdVzL3jpo5toTCT0Jl3v+FEkzuPs/Oyk5daqj9zgbwKqxBl6bENjndXS9kAskQF 8Ajw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=za2L0CKEB7yf2ik8Iuj/BZryf3LCWxSxvd2XuC3OlRk=; b=dAr+guZ5RhInNn3FOrf9laFPw1QcNorI2k3eCAQxWhIYxXvlM9FxdH977ak1pv85OD u9TZhLMuhakTmXUplWp0928MyV1CcomF+6hs06X3g77TaLCVJlNBB0oN+JrraTrPoaNw 5nMUSYqwo5XDySZAQDRzAea6OrL+fLMPIcGtOZdCaCwFNcQTqdpbu7DWBnCEfBIU7ob1 6ZE5scxFE1JSJhLKATfcBnQUlXi6xIKacJBf7kuy4Zw4xdW/Nf8bSiry4LcbHX2ePhTv 1f0hZKJoMZT4tbk28N5o1tWK5RCwlD/vgI1uID/eDdKw4KUTahuRIc6DKhuvH9w1U48O ksrw== X-Gm-Message-State: AFqh2kpj+RfdraKLiqjVjxy75umz08K1BmtcMAgzkZuvSkFmRdKhioOO 1lb8wAAAS8nZT18MEwuI6D4= X-Google-Smtp-Source: AMrXdXu6jEh2mcbeZvR7xwuBfasOURRH24VBC4lgSlkhlPru3BjcxJmCfN4Lda+xirYzlxyl5+iX3w== X-Received: by 2002:a05:6000:819:b0:242:192c:9b34 with SMTP id bt25-20020a056000081900b00242192c9b34mr2762999wrb.59.1671580979914; Tue, 20 Dec 2022 16:02:59 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2501:c701:1595:a48c:95a8:15e0]) by smtp.gmail.com with ESMTPSA id f2-20020a5d50c2000000b002362f6fcaf5sm13740150wrt.48.2022.12.20.16.02.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 16:02:59 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 3/9] irqchip: irq-renesas-rzg2l: Skip mapping NMI interrupt as part of hierarchy domain Date: Wed, 21 Dec 2022 00:02:36 +0000 Message-Id: <20221221000242.340202-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar NMI interrupt is not an external interrupt as compared to the IRQ0-7 and TINT0-31, this means we need to install the irq handler for NMI in the IRQC driver and not include it as part of IRQ domain. This patch skips mapping NMI interrupt as part of the IRQ domain hierarchy. Fixes: 3fed09559cd8 ("irqchip: Add RZ/G2L IA55 Interrupt Controller driver") Signed-off-by: Lad Prabhakar --- v1 -> v2 * New patch --- drivers/irqchip/irq-renesas-rzg2l.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c index 25fd8ee66565..7918fe201218 100644 --- a/drivers/irqchip/irq-renesas-rzg2l.c +++ b/drivers/irqchip/irq-renesas-rzg2l.c @@ -23,7 +23,8 @@ #define IRQC_IRQ_COUNT 8 #define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT) #define IRQC_TINT_COUNT 32 -#define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT) + /* IRQ0-7 + TINT0-31 */ +#define IRQC_NUM_HIERARCHY_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT - 1) #define ISCR 0x10 #define IITSR 0x14 @@ -58,7 +59,8 @@ struct rzg2l_irqc_priv { void __iomem *base; - struct irq_fwspec fwspec[IRQC_NUM_IRQ]; + /* IRQ0-7 + TINT0-31 will be part of hierarchy domain */ + struct irq_fwspec fwspec[IRQC_NUM_HIERARCHY_IRQ]; raw_spinlock_t lock; }; @@ -99,7 +101,7 @@ static void rzg2l_irqc_eoi(struct irq_data *d) raw_spin_lock(&priv->lock); if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) rzg2l_irq_eoi(d); - else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) + else if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ) rzg2l_tint_eoi(d); raw_spin_unlock(&priv->lock); irq_chip_eoi_parent(d); @@ -109,7 +111,7 @@ static void rzg2l_irqc_irq_disable(struct irq_data *d) { unsigned int hw_irq = irqd_to_hwirq(d); - if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { + if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ) { struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); u32 offset = hw_irq - IRQC_TINT_START; u32 tssr_offset = TSSR_OFFSET(offset); @@ -129,7 +131,7 @@ static void rzg2l_irqc_irq_enable(struct irq_data *d) { unsigned int hw_irq = irqd_to_hwirq(d); - if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { + if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ) { struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); unsigned long tint = (uintptr_t)d->chip_data; u32 offset = hw_irq - IRQC_TINT_START; @@ -228,7 +230,7 @@ static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) ret = rzg2l_irq_set_type(d, type); - else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) + else if (hw_irq >= IRQC_TINT_START && hw_irq <= IRQC_NUM_HIERARCHY_IRQ) ret = rzg2l_tint_set_edge(d, type); if (ret) return ret; @@ -280,7 +282,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq, return -EINVAL; } - if (hwirq > (IRQC_NUM_IRQ - 1)) + if (!hwirq || hwirq > IRQC_NUM_HIERARCHY_IRQ) return -EINVAL; ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &irqc_chip, @@ -288,7 +290,7 @@ static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq, if (ret) return ret; - return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]); + return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq - 1]); } static const struct irq_domain_ops rzg2l_irqc_domain_ops = { @@ -304,12 +306,12 @@ static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, unsigned int i; int ret; - for (i = 0; i < IRQC_NUM_IRQ; i++) { + for (i = 1; i <= IRQC_NUM_HIERARCHY_IRQ; i++) { ret = of_irq_parse_one(np, i, &map); if (ret) return ret; of_phandle_args_to_fwspec(np, map.args, map.args_count, - &priv->fwspec[i]); + &priv->fwspec[i - 1]); } return 0; @@ -366,7 +368,7 @@ static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) raw_spin_lock_init(&priv->lock); - irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ, + irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_HIERARCHY_IRQ, node, &rzg2l_irqc_domain_ops, priv); if (!irq_domain) { From patchwork Wed Dec 21 00:02:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 635818 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F4FFC4167B for ; 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Tue, 20 Dec 2022 16:03:01 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 5/9] pinctrl: renesas: rzg2l: Fix configuring the GPIO pins as interrupts Date: Wed, 21 Dec 2022 00:02:38 +0000 Message-Id: <20221221000242.340202-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar On the RZ/G2UL SoC we have less number of pins compared to RZ/G2L and also the pin configs are completely different. This patch makes sure we use the appropriate pin configs for each SoC (which is passed as part of the OF data) while configuring the GPIO pin as interrupts instead of using rzg2l_gpio_configs[] for all the SoCs. Fixes: bfc69bdbaad1 ("pinctrl: renesas: rzg2l: Add RZ/G2UL support") Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v1 -> v2 * Fixed comments pointed by Geert for variable naming * Added RB tag --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 4e79b2961232..03e9462f39b1 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -127,6 +127,7 @@ struct rzg2l_dedicated_configs { struct rzg2l_pinctrl_data { const char * const *port_pins; const u32 *port_pin_configs; + unsigned int n_ports; struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; unsigned int n_dedicated_pins; @@ -1121,7 +1122,7 @@ static struct { } }; -static int rzg2l_gpio_get_gpioint(unsigned int virq) +static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data) { unsigned int gpioint; unsigned int i; @@ -1130,13 +1131,13 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq) port = virq / 8; bit = virq % 8; - if (port >= ARRAY_SIZE(rzg2l_gpio_configs) || - bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) + if (port >= data->n_ports || + bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port])) return -EINVAL; gpioint = bit; for (i = 0; i < port; i++) - gpioint += RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[i]); + gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]); return gpioint; } @@ -1236,7 +1237,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, unsigned long flags; int gpioint, irq; - gpioint = rzg2l_gpio_get_gpioint(child); + gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data); if (gpioint < 0) return gpioint; @@ -1310,8 +1311,8 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, port = offset / 8; bit = offset % 8; - if (port >= ARRAY_SIZE(rzg2l_gpio_configs) || - bit >= RZG2L_GPIO_PORT_GET_PINCNT(rzg2l_gpio_configs[port])) + if (port >= pctrl->data->n_ports || + bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port])) clear_bit(offset, valid_mask); } } @@ -1516,6 +1517,7 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) static struct rzg2l_pinctrl_data r9a07g043_data = { .port_pins = rzg2l_gpio_names, .port_pin_configs = r9a07g043_gpio_configs, + .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs), .dedicated_pins = rzg2l_dedicated_pins.common, .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), @@ -1524,6 +1526,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { static struct rzg2l_pinctrl_data r9a07g044_data = { .port_pins = rzg2l_gpio_names, .port_pin_configs = rzg2l_gpio_configs, + .n_ports = ARRAY_SIZE(rzg2l_gpio_configs), .dedicated_pins = rzg2l_dedicated_pins.common, .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names), .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + From patchwork Wed Dec 21 00:02:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 635817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 105FDC3DA7D for ; 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Tue, 20 Dec 2022 16:03:02 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 6/9] pinctrl: renesas: rzg2l: Add BUILD_BUG_ON() checks Date: Wed, 21 Dec 2022 00:02:39 +0000 Message-Id: <20221221000242.340202-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar Add BUILD_BUG_ON() checks to avoid overflows for GPIO configs for each supported SoC. While at it, for readability set n_port_pins based on the GPIO pin configs and not on GPIO names for r9a07g044_data as done for r9a07g043_data. Suggested-by: Geert Uytterhoeven Signed-off-by: Lad Prabhakar --- v1 -> v2 * New patch --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 03e9462f39b1..8036485f2e92 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -1465,6 +1465,12 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev) struct rzg2l_pinctrl *pctrl; int ret; + BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT > + ARRAY_SIZE(rzg2l_gpio_names)); + + BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > + ARRAY_SIZE(rzg2l_gpio_names)); + pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) return -ENOMEM; @@ -1528,7 +1534,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = { .port_pin_configs = rzg2l_gpio_configs, .n_ports = ARRAY_SIZE(rzg2l_gpio_configs), .dedicated_pins = rzg2l_dedicated_pins.common, - .n_port_pins = ARRAY_SIZE(rzg2l_gpio_names), + .n_port_pins = ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), }; 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Tue, 20 Dec 2022 16:03:06 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2501:c701:1595:a48c:95a8:15e0]) by smtp.gmail.com with ESMTPSA id f2-20020a5d50c2000000b002362f6fcaf5sm13740150wrt.48.2022.12.20.16.03.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 16:03:05 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v2 9/9] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1} Date: Wed, 21 Dec 2022 00:02:42 +0000 Message-Id: <20221221000242.340202-10-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20221221000242.340202-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and ETH1 respectively. Signed-off-by: Lad Prabhakar --- v1 -> v2 * No change --- arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 931efc07d6fb..49ecd33aeeb8 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include / { @@ -77,6 +78,8 @@ phy0: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = ; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -104,6 +107,8 @@ phy1: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = ; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -151,7 +156,8 @@ eth0_pins: eth0 { , /* ET0_RXD0 */ , /* ET0_RXD1 */ , /* ET0_RXD2 */ - ; /* ET0_RXD3 */ + , /* ET0_RXD3 */ + ; /* IRQ2 */ }; eth1_pins: eth1 { @@ -169,7 +175,8 @@ eth1_pins: eth1 { , /* ET1_RXD0 */ , /* ET1_RXD1 */ , /* ET1_RXD2 */ - ; /* ET1_RXD3 */ + , /* ET1_RXD3 */ + ; /* IRQ7 */ }; sdhi0_emmc_pins: sd0emmc {