From patchwork Wed Dec 21 21:09:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 636149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 881FBC41535 for ; Wed, 21 Dec 2022 21:09:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234634AbiLUVJm (ORCPT ); Wed, 21 Dec 2022 16:09:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234633AbiLUVJk (ORCPT ); Wed, 21 Dec 2022 16:09:40 -0500 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 72E7B22281; Wed, 21 Dec 2022 13:09:39 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,263,1665414000"; d="scan'208";a="144108258" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 22 Dec 2022 06:09:39 +0900 Received: from mulinux.example.org (unknown [10.226.92.211]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 29FF140DC546; Thu, 22 Dec 2022 06:09:33 +0900 (JST) From: Fabrizio Castro To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sebastian Reichel , Geert Uytterhoeven Cc: Fabrizio Castro , Lee Jones , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org, Laurent Pinchart , Jacopo Mondi Subject: [PATCH v2 1/4] dt-bindings: mfd: Add RZ/V2M PWC Date: Wed, 21 Dec 2022 21:09:14 +0000 Message-Id: <20221221210917.458537-2-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221221210917.458537-1-fabrizio.castro.jz@renesas.com> References: <20221221210917.458537-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Renesas RZ/V2M External Power Sequence Controller (PWC) IP is a multi-function device, and it's capable of: * external power supply on/off sequence generation * on/off signal generation for the LPDDR4 core power supply (LPVDD) * key input signals processing * general-purpose output pins Add the corresponding dt-bindings. Signed-off-by: Fabrizio Castro --- v1->v2: I have dropped syscon, simple-mfd, regmap, offset, and the child nodes. .../bindings/mfd/renesas,rzv2m-pwc.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc.yaml diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc.yaml new file mode 100644 index 000000000000..e6794c5152d5 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/renesas,rzv2m-pwc.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/renesas,rzv2m-pwc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2M External Power Sequence Controller (PWC) + +description: |+ + The PWC IP found in the RZ/V2M family of chips comes with the below + capabilities + - external power supply on/off sequence generation + - on/off signal generation for the LPDDR4 core power supply (LPVDD) + - key input signals processing + - general-purpose output pins + +maintainers: + - Fabrizio Castro + +properties: + compatible: + items: + - enum: + - renesas,r9a09g011-pwc # RZ/V2M + - renesas,r9a09g055-pwc # RZ/V2MA + - const: renesas,rzv2m-pwc + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + renesas,rzv2m-pwc-power: + description: The PWC is used to control the system power supplies. + type: boolean + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + pwc: pwc@a3700000 { + compatible = "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc"; + reg = <0xa3700000 0x800>; + gpio-controller; + #gpio-cells = <2>; + renesas,rzv2m-pwc-power; + }; From patchwork Wed Dec 21 21:09:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 635761 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78961C4167B for ; Wed, 21 Dec 2022 21:09:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234887AbiLUVJw (ORCPT ); Wed, 21 Dec 2022 16:09:52 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234825AbiLUVJu (ORCPT ); Wed, 21 Dec 2022 16:09:50 -0500 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 89BC2264B9; Wed, 21 Dec 2022 13:09:45 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,263,1665414000"; d="scan'208";a="144108268" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 22 Dec 2022 06:09:44 +0900 Received: from mulinux.example.org (unknown [10.226.92.211]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id CD59B40DC546; Thu, 22 Dec 2022 06:09:39 +0900 (JST) From: Fabrizio Castro To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sebastian Reichel , Geert Uytterhoeven Cc: Fabrizio Castro , Lee Jones , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org, Laurent Pinchart , Jacopo Mondi Subject: [PATCH v2 2/4] mfd: Add RZ/V2M PWC core driver Date: Wed, 21 Dec 2022 21:09:15 +0000 Message-Id: <20221221210917.458537-3-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221221210917.458537-1-fabrizio.castro.jz@renesas.com> References: <20221221210917.458537-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The External Power Sequence Controller (PWC) IP (found in the RZ/V2M SoC) is a controller for external power supplies (regulators and power switches), and it supports the following features: it generates a power on/off sequence for external power supplies, it generates an on/off sequence for the LPDDR4 core power supply (LPVDD), it comes with General-Purpose Outputs, and it processes key input signals. The PWC is basically a Multi-Function Device (MFD), its software support comes with a core driver, and specialized drivers for its specific features. This patch adds the core driver for the RZ/V2M PWC IP. Signed-off-by: Fabrizio Castro --- v1->v2: This is a new driver, to match the relevant compatible string and instantiate the relevant mfd device drivers drivers/mfd/Kconfig | 14 +++++++++ drivers/mfd/Makefile | 1 + drivers/mfd/rzv2m-pwc.c | 70 +++++++++++++++++++++++++++++++++++++++++ drivers/mfd/rzv2m-pwc.h | 18 +++++++++++ 4 files changed, 103 insertions(+) create mode 100644 drivers/mfd/rzv2m-pwc.c create mode 100644 drivers/mfd/rzv2m-pwc.h diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 30db49f31866..ac4403e4f3cb 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2265,5 +2265,19 @@ config MFD_RSMU_SPI Additional drivers must be enabled in order to use the functionality of the device. +config MFD_RZV2M_PWC_CORE + tristate "Renesas RZ/V2M PWC Core Driver" + select MFD_CORE + depends on ARCH_R9A09G011 || COMPILE_TEST + help + Select this option to enable the RZ/V2M External Power Sequence + Controller (PWC) core driver. + + The PWC is a controller for external power supplies (regulators and + power switches), and it supports the following features: it generates + a power on/off sequence for external power supplies, it generates an + on/off sequence for the LPDDR4 core power supply (LPVDD), it comes + with General-Purpose Outputs, and it processes key input signals. + endmenu endif diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 457471478a93..e39252a2df23 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -278,3 +278,4 @@ rsmu-i2c-objs := rsmu_core.o rsmu_i2c.o rsmu-spi-objs := rsmu_core.o rsmu_spi.o obj-$(CONFIG_MFD_RSMU_I2C) += rsmu-i2c.o obj-$(CONFIG_MFD_RSMU_SPI) += rsmu-spi.o +obj-$(CONFIG_MFD_RZV2M_PWC_CORE) += rzv2m-pwc.o diff --git a/drivers/mfd/rzv2m-pwc.c b/drivers/mfd/rzv2m-pwc.c new file mode 100644 index 000000000000..f9055fcafda2 --- /dev/null +++ b/drivers/mfd/rzv2m-pwc.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Renesas Electronics Corporation + * + * Core driver for the Renesas RZ/V2M External Power Sequence Controller (PWC) + */ + +#include +#include +#include +#include "rzv2m-pwc.h" + +static const struct mfd_cell rzv2m_pwc_gpio_devs[] = { + { .name = "gpio_rzv2m_pwc", }, +}; + +static const struct mfd_cell rzv2m_pwc_poweroff_devs[] = { + { .name = "rzv2m_pwc_poweroff", }, +}; + +static int rzv2m_pwc_probe(struct platform_device *pdev) +{ + struct rzv2m_pwc_priv *priv; + int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + platform_set_drvdata(pdev, priv); + + ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO, + rzv2m_pwc_gpio_devs, + ARRAY_SIZE(rzv2m_pwc_gpio_devs), NULL, 0, + NULL); + if (ret) + return ret; + + if (of_property_read_bool(pdev->dev.of_node, "renesas,rzv2m-pwc-power")) + ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO, + rzv2m_pwc_poweroff_devs, + ARRAY_SIZE(rzv2m_pwc_poweroff_devs), + NULL, 0, NULL); + + return ret; +} + +static const struct of_device_id rzv2m_pwc_of_match[] = { + { .compatible = "renesas,rzv2m-pwc" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rzv2m_pwc_of_match); + +static struct platform_driver rzv2m_pwc_driver = { + .probe = rzv2m_pwc_probe, + .driver = { + .name = "rzv2m_pwc", + .of_match_table = of_match_ptr(rzv2m_pwc_of_match), + }, +}; +module_platform_driver(rzv2m_pwc_driver); + +MODULE_SOFTDEP("post: gpio_rzv2m_pwc rzv2m_pwc_poweroff"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Fabrizio Castro "); +MODULE_DESCRIPTION("Renesas RZ/V2M PWC core driver"); diff --git a/drivers/mfd/rzv2m-pwc.h b/drivers/mfd/rzv2m-pwc.h new file mode 100644 index 000000000000..8f3d777557c9 --- /dev/null +++ b/drivers/mfd/rzv2m-pwc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2022 Renesas Electronics Corporation + */ + +#ifndef __LINUX_RZV2M_PWC_H__ +#define __LINUX_RZV2M_PWC_H__ + +#define PWC_PWCRST 0x00 +#define PWC_PWCCKEN 0x04 +#define PWC_PWCCTL 0x50 +#define PWC_GPIO 0x80 + +struct rzv2m_pwc_priv { + void __iomem *base; +}; + +#endif /* __LINUX_RZV2M_PWC_H__ */ From patchwork Wed Dec 21 21:09:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 636148 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 910CFC4332F for ; Wed, 21 Dec 2022 21:10:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234976AbiLUVKH (ORCPT ); Wed, 21 Dec 2022 16:10:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234923AbiLUVJz (ORCPT ); Wed, 21 Dec 2022 16:09:55 -0500 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id D54E427174; Wed, 21 Dec 2022 13:09:50 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,263,1665414000"; d="scan'208";a="146995954" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 22 Dec 2022 06:09:50 +0900 Received: from mulinux.example.org (unknown [10.226.92.211]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 86F4040DC546; Thu, 22 Dec 2022 06:09:45 +0900 (JST) From: Fabrizio Castro To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sebastian Reichel , Geert Uytterhoeven Cc: Fabrizio Castro , Lee Jones , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org, Laurent Pinchart , Jacopo Mondi Subject: [PATCH v2 3/4] gpio: Add support for the Renesas RZ/V2M PWC GPIOs Date: Wed, 21 Dec 2022 21:09:16 +0000 Message-Id: <20221221210917.458537-4-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221221210917.458537-1-fabrizio.castro.jz@renesas.com> References: <20221221210917.458537-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The RZ/V2M SoC contains an External Power Sequence Controller (PWC) module. The PWC module provides an external power supply on/off sequence, on/off signal for the LPDDR4 core power supply, General-Purpose Outputs, and key input signals. Add a driver for controlling the General-Purpose Outputs. Signed-off-by: Fabrizio Castro Reviewed-by: Linus Walleij --- v1->v2: Dropped OF match table and syscon as a result of the change in DT model drivers/gpio/Kconfig | 10 ++++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-rzv2m-pwc.c | 105 ++++++++++++++++++++++++++++++++++ 3 files changed, 116 insertions(+) create mode 100644 drivers/gpio/gpio-rzv2m-pwc.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index ec7cfd4f52b1..4c77fb6966e0 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -553,6 +553,16 @@ config GPIO_ROCKCHIP help Say yes here to support GPIO on Rockchip SoCs. +config GPIO_RZV2M_PWC + tristate "Renesas RZ/V2M PWC GPIO support" + depends on MFD_RZV2M_PWC_CORE || COMPILE_TEST + help + Say yes here to support the External Power Sequence Controller (PWC) + GPIO controller driver for RZ/V2M devices. + + The PWSDxSEL pins can be used as General-Purpose Ouputs. + Their output is low by default. + config GPIO_SAMA5D2_PIOBU tristate "SAMA5D2 PIOBU GPIO support" depends on MFD_SYSCON diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 010587025fc8..a5c159ae9db5 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -132,6 +132,7 @@ obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o obj-$(CONFIG_GPIO_REALTEK_OTTO) += gpio-realtek-otto.o obj-$(CONFIG_GPIO_REG) += gpio-reg.o obj-$(CONFIG_GPIO_ROCKCHIP) += gpio-rockchip.o +obj-$(CONFIG_GPIO_RZV2M_PWC) += gpio-rzv2m-pwc.o obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o diff --git a/drivers/gpio/gpio-rzv2m-pwc.c b/drivers/gpio/gpio-rzv2m-pwc.c new file mode 100644 index 000000000000..19bdb949b3d3 --- /dev/null +++ b/drivers/gpio/gpio-rzv2m-pwc.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Renesas Electronics Corporation + * + * GPIO driver for Renesas RZ/V2M External Power Sequence Controller (PWC) + */ + +#include +#include +#include +#include "../mfd/rzv2m-pwc.h" + +struct rzv2m_pwc_gpio_priv { + void __iomem *base; + struct gpio_chip gp; + DECLARE_BITMAP(ch_en_bits, 2); +}; + +static void rzv2m_pwc_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct rzv2m_pwc_gpio_priv *priv = gpiochip_get_data(chip); + u32 reg; + + /* BIT 16 enables write to BIT 0, and BIT 17 enables write to BIT 1 */ + reg = BIT(offset + 16); + if (value) + reg |= BIT(offset); + + writel(reg, priv->base + PWC_GPIO); + + if (value) + set_bit(offset, priv->ch_en_bits); + else + clear_bit(offset, priv->ch_en_bits); +} + +static int rzv2m_pwc_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct rzv2m_pwc_gpio_priv *priv = gpiochip_get_data(chip); + + return test_bit(offset, priv->ch_en_bits); +} + +static int rzv2m_pwc_gpio_direction_output(struct gpio_chip *gc, + unsigned int nr, int value) +{ + if (nr > 1) + return -EINVAL; + + rzv2m_pwc_gpio_set(gc, nr, value); + + return 0; +} + +static const struct gpio_chip rzv2m_pwc_gc = { + .label = "gpio_rzv2m_pwc", + .owner = THIS_MODULE, + .get = rzv2m_pwc_gpio_get, + .set = rzv2m_pwc_gpio_set, + .direction_output = rzv2m_pwc_gpio_direction_output, + .can_sleep = false, + .ngpio = 2, + .base = -1, +}; + +static int rzv2m_pwc_gpio_probe(struct platform_device *pdev) +{ + struct rzv2m_pwc_priv *pdata = dev_get_drvdata(pdev->dev.parent); + struct rzv2m_pwc_gpio_priv *priv; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = pdata->base; + /* + * The register used by this driver cannot be read, therefore set the + * outputs to their default values and initialize priv->ch_en_bits + * accordingly. BIT 16 enables write to BIT 0, BIT 17 enables write to + * BIT 1, and the default value of both BIT 0 and BIT 1 is 0. + */ + writel(BIT(17) | BIT(16), priv->base + PWC_GPIO); + bitmap_zero(priv->ch_en_bits, 2); + + priv->gp = rzv2m_pwc_gc; + priv->gp.parent = pdev->dev.parent; + priv->gp.fwnode = dev_fwnode(pdev->dev.parent); + + return devm_gpiochip_add_data(&pdev->dev, &priv->gp, priv); +} + +static struct platform_driver rzv2m_pwc_gpio_driver = { + .probe = rzv2m_pwc_gpio_probe, + .driver = { + .name = "gpio_rzv2m_pwc", + }, +}; +module_platform_driver(rzv2m_pwc_gpio_driver); + +MODULE_ALIAS("platform:gpio_rzv2m_pwc"); +MODULE_SOFTDEP("pre: rzv2m_pwc"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Fabrizio Castro "); +MODULE_DESCRIPTION("Renesas RZ/V2M PWC GPIO"); From patchwork Wed Dec 21 21:09:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 635760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E40BDC10F1B for ; Wed, 21 Dec 2022 21:10:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234970AbiLUVKg (ORCPT ); Wed, 21 Dec 2022 16:10:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234967AbiLUVKH (ORCPT ); Wed, 21 Dec 2022 16:10:07 -0500 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A8B8E27B00; Wed, 21 Dec 2022 13:09:57 -0800 (PST) X-IronPort-AV: E=Sophos;i="5.96,263,1665414000"; d="scan'208";a="146995973" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 22 Dec 2022 06:09:56 +0900 Received: from mulinux.example.org (unknown [10.226.92.211]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 3E65F40DC546; Thu, 22 Dec 2022 06:09:50 +0900 (JST) From: Fabrizio Castro To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Sebastian Reichel , Geert Uytterhoeven Cc: Fabrizio Castro , Lee Jones , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Chris Paterson , Biju Das , linux-renesas-soc@vger.kernel.org, Laurent Pinchart , Jacopo Mondi Subject: [PATCH v2 4/4] power: reset: Add new driver for RZ/V2M PWC poweroff Date: Wed, 21 Dec 2022 21:09:17 +0000 Message-Id: <20221221210917.458537-5-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221221210917.458537-1-fabrizio.castro.jz@renesas.com> References: <20221221210917.458537-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The RZ/V2M PWC IP controls external power supplies and therefore can turn the power supplies off when powering down the system. Add driver to poweroff the system. Signed-off-by: Fabrizio Castro --- v1->v2: Dropped OF match table and syscon as a result of the change in DT model drivers/power/reset/Kconfig | 9 ++++ drivers/power/reset/Makefile | 1 + drivers/power/reset/rzv2m-pwc-poweroff.c | 67 ++++++++++++++++++++++++ 3 files changed, 77 insertions(+) create mode 100644 drivers/power/reset/rzv2m-pwc-poweroff.c diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig index a8c46ba5878f..1fcf691ae68e 100644 --- a/drivers/power/reset/Kconfig +++ b/drivers/power/reset/Kconfig @@ -303,4 +303,13 @@ config POWER_MLXBF help This driver supports reset or low power mode handling for Mellanox BlueField. +config POWER_RESET_RZV2M_PWC + tristate "Renesas RZ/V2M PWC Power OFF support" + depends on MFD_RZV2M_PWC_CORE || COMPILE_TEST + help + The RZ/V2M PWC IP controls external power supplies and therefore can + turn the power supplies off when powering down the system. + Enable this driver when PWC is in control of the system power supplies + and it's the preferred way to shutdown the system. + endif diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile index 0a39424fc558..f05a8abff2eb 100644 --- a/drivers/power/reset/Makefile +++ b/drivers/power/reset/Makefile @@ -36,3 +36,4 @@ obj-$(CONFIG_SYSCON_REBOOT_MODE) += syscon-reboot-mode.o obj-$(CONFIG_POWER_RESET_SC27XX) += sc27xx-poweroff.o obj-$(CONFIG_NVMEM_REBOOT_MODE) += nvmem-reboot-mode.o obj-$(CONFIG_POWER_MLXBF) += pwr-mlxbf.o +obj-$(CONFIG_POWER_RESET_RZV2M_PWC) += rzv2m-pwc-poweroff.o diff --git a/drivers/power/reset/rzv2m-pwc-poweroff.c b/drivers/power/reset/rzv2m-pwc-poweroff.c new file mode 100644 index 000000000000..f5bc383c22e1 --- /dev/null +++ b/drivers/power/reset/rzv2m-pwc-poweroff.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022 Renesas Electronics Corporation + * + * Reset driver for Renesas RZ/V2M External Power Sequence Controller (PWC) + */ + +#include +#include +#include +#include +#include "../../mfd/rzv2m-pwc.h" + +#define PWC_PWCRST_RSTSOFTAX 0x1 +#define PWC_PWCCKEN_ENGCKMAIN 0x1 +#define PWC_PWCCTL_PWOFF 0x1 + +struct rzv2m_pwc_poweroff_priv { + void __iomem *base; + struct device *dev; +}; + +static int rzv2m_pwc_poweroff(struct sys_off_data *data) +{ + struct rzv2m_pwc_poweroff_priv *priv = + (struct rzv2m_pwc_poweroff_priv *)data->cb_data; + + writel(PWC_PWCRST_RSTSOFTAX, priv->base + PWC_PWCRST); + writel(PWC_PWCCKEN_ENGCKMAIN, priv->base + PWC_PWCCKEN); + writel(PWC_PWCCTL_PWOFF, priv->base + PWC_PWCCTL); + + mdelay(150); + + dev_err(priv->dev, "Failed to power off the system"); + + return NOTIFY_DONE; +} + +static int rzv2m_pwc_poweroff_probe(struct platform_device *pdev) +{ + struct rzv2m_pwc_priv *pdata = dev_get_drvdata(pdev->dev.parent); + struct rzv2m_pwc_poweroff_priv *priv; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base = pdata->base; + priv->dev = &pdev->dev; + + return devm_register_power_off_handler(&pdev->dev, rzv2m_pwc_poweroff, + priv); +} + +static struct platform_driver rzv2m_pwc_poweroff_driver = { + .probe = rzv2m_pwc_poweroff_probe, + .driver = { + .name = "rzv2m_pwc_poweroff", + }, +}; +module_platform_driver(rzv2m_pwc_poweroff_driver); + +MODULE_ALIAS("platform:rzv2m_pwc_poweroff"); +MODULE_SOFTDEP("pre: rzv2m_pwc"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Fabrizio Castro "); +MODULE_DESCRIPTION("Renesas RZ/V2M PWC power OFF driver");