From patchwork Tue Dec 20 02:47:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635715 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3CF3C3DA7B for ; Tue, 20 Dec 2022 02:47:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232906AbiLTCr2 (ORCPT ); Mon, 19 Dec 2022 21:47:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39188 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230090AbiLTCr1 (ORCPT ); Mon, 19 Dec 2022 21:47:27 -0500 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E173713D55 for ; Mon, 19 Dec 2022 18:47:25 -0800 (PST) Received: by mail-lf1-x132.google.com with SMTP id b3so16626979lfv.2 for ; Mon, 19 Dec 2022 18:47:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FjTuXszLa3PpvcC6GObAES0NeWmHYF7aB2zTBhEiXEk=; b=ee42aMWfnHOOTkMbfGJpqmAkXFBhPOXz2Zi0utvhysgnT2JBKd3rXpiY9hpjkml9sw +CJfUfqxofaO0bXe7ARd8rTeAPr97702zSWyf8cBwWLhh2Ad+133/s1vONFGOvycQlgo l3cVeqAeZPEODJjPjpVybHwS/NK0Se5kDrvM9iL1UZVc9qUigBxoi9FSmoCq+I9cAeQ9 /N1h864XE2k23dVqrJ1QIpqGm9rvkrI19c/b8SjknhZPi6GUvJFPrtLFxZg6D3vI3qOp eOGgot61ejWNOlcnXP1H471gwEpl0cR7d2qiuLjZgJW3+881d+yEoiGoke3TDKtDe460 ZJnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FjTuXszLa3PpvcC6GObAES0NeWmHYF7aB2zTBhEiXEk=; b=0+n9vjonh4P3sr/S0IiDNU5Xr/Sp4kG+moo2t7aGqwGV3ykaneID3GNXXMAYHb3php GMOrIFKJxDiiEvMIoOLPQuLLQr3GWMTCmB6DHPVJvYnGk0DeZ/BFfxYrrLz/bFHEE8AJ PA84FewwsgfnKBjz75/9bUb5HGF3s3NOrWC3XqjZGwuUDtV0u0V7OEvhWqq9YZeuGtsL 3eJvWGojx9cAZzRBbMCkoPzDTzmx7NyvVSKVykgl8eI2dViMOMT4/URgNkWVrtC+yHTP Y0FeV08ZHe8o0fsjQkA7juPYFvV82pRj1iDD6hi0W55/VFLWxbHhoPYD/iL4h0yZksgF OqZg== X-Gm-Message-State: AFqh2krLlpaagj2Lis0+P53dfph4y/l5ISMI/kZtjAawRtrcCV9RCrQe g0fLLtv8QyOzkV1wVb+R2RPP7g== X-Google-Smtp-Source: AMrXdXsAi+pQ7ZLNoxrVYL8ynWSDhmBf3tJWDRCPoJx/S8lpqFdXCbEbKrmzegbNxcSS27ZQt5xzxg== X-Received: by 2002:a19:2d59:0:b0:4b5:1414:415f with SMTP id t25-20020a192d59000000b004b51414415fmr147928lft.59.1671504444223; Mon, 19 Dec 2022 18:47:24 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id e13-20020a05651236cd00b004b5a85e369asm1274866lfs.252.2022.12.19.18.47.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 18:47:23 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 02/15] dt-bindings: thermal: tsens: support per-sensor calibration cells Date: Tue, 20 Dec 2022 04:47:08 +0200 Message-Id: <20221220024721.947147-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> References: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Allow specifying the exact calibration mode and calibration data as nvmem cells, rather than specifying just a single calibration data blob. Acked-by: Krzysztof Kozlowski Reviewed-by: Amit Kucheria Signed-off-by: Dmitry Baryshkov --- .../bindings/thermal/qcom-tsens.yaml | 64 ++++++++++++++++--- 1 file changed, 54 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index f3660af0b3bf..da7b5bd4abd5 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -81,18 +81,62 @@ properties: maxItems: 2 nvmem-cells: - minItems: 1 - maxItems: 2 - description: - Reference to an nvmem node for the calibration data + oneOf: + - minItems: 1 + maxItems: 2 + description: + Reference to an nvmem node for the calibration data + - minItems: 5 + maxItems: 35 + description: | + Reference to nvmem cells for the calibration mode, two calibration + bases and two cells per each sensor nvmem-cell-names: - minItems: 1 - items: - - const: calib - - enum: - - calib_backup - - calib_sel + oneOf: + - minItems: 1 + items: + - const: calib + - enum: + - calib_backup + - calib_sel + - minItems: 5 + items: + - const: mode + - const: base1 + - const: base2 + - const: s0_p1 + - const: s0_p2 + - const: s1_p1 + - const: s1_p2 + - const: s2_p1 + - const: s2_p2 + - const: s3_p1 + - const: s3_p2 + - const: s4_p1 + - const: s4_p2 + - const: s5_p1 + - const: s5_p2 + - const: s6_p1 + - const: s6_p2 + - const: s7_p1 + - const: s7_p2 + - const: s8_p1 + - const: s8_p2 + - const: s9_p1 + - const: s9_p2 + - const: s10_p1 + - const: s10_p2 + - const: s11_p1 + - const: s11_p2 + - const: s12_p1 + - const: s12_p2 + - const: s13_p1 + - const: s13_p2 + - const: s14_p1 + - const: s14_p2 + - const: s15_p1 + - const: s15_p2 "#qcom,sensors": description: From patchwork Tue Dec 20 02:47:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635714 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1AAC3C4332F for ; Tue, 20 Dec 2022 02:47:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232883AbiLTCra (ORCPT ); Mon, 19 Dec 2022 21:47:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232897AbiLTCr2 (ORCPT ); Mon, 19 Dec 2022 21:47:28 -0500 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 32FAE12763 for ; Mon, 19 Dec 2022 18:47:27 -0800 (PST) Received: by mail-lf1-x136.google.com with SMTP id o6so11705500lfi.5 for ; Mon, 19 Dec 2022 18:47:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j6cA4Rv7ZGDOj4S5hrIclxaFxqbwYxf0WlThWIKncNA=; b=rUvApwrSs9vfqMF8Vi8V3PDqUh98q/tIojUp9FEPgX3MGwGR69faAxsLZxLKHbaW1S MW78lft/1pBBSt4kil8sBMV5PFNpT1ql/hhGm5r3VFdTP4KSj3D1xeYA8ilj4I4yGF9m iEiBwXVTIpXYmXnuS0DxEcNoY5OLmtQrJt1wtgrM1VB45BdI117v9xzLm/y2msyhoduE wvlz33uBQ03ErA/EHDHBgxfjFT12Z43BU3eYi1NJv23FyOpeTrMbm9FiT7C5WyJJuFUP fZqa9+iklIAjrU4aFEvXPbFKPhsaCoIyzeppFfeqj9lt1Wbxn6hz3jwEYjzlHwK1Ok4N 0/NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j6cA4Rv7ZGDOj4S5hrIclxaFxqbwYxf0WlThWIKncNA=; b=zQJztuCD0lhC/kpF1NAT4Q6cLPxJnwp0v9Rz3FftjdrPoqR/eQkbCfueJ4DnwC8HRr N5bTp/GYnW7ZqMK0PvY7Dp9RQLbJho5BYSZrxKZ6VdnNufMj4SQKBB3x1DEx8JPlJv0Y xGRjlO1XelljOMaYsfP2PvZ/NejuAmmrkONOqB4EAKsibhdKr8r1qxrhLOO9MkfTP/ku kIjUPa9bBEXmWewsYxtldgqC/EKPrCGPL7C11YNwK+BwDuVTBpdMLsm5/fLNQLgutK12 QQ+9euXATJ0f8Qza9qPN/+elwCvx00kVRf42ewZwCVZAqCIzkSisbGly3rtl9ci+Mpfb B8Ag== X-Gm-Message-State: ANoB5pkpTIUQj4nlGN+8IrMH7yBkKEKnoFSv4B5V6wV1y5PxK38djhjr Y9OvT7+o+kb0iPpRs4TXMnecrA== X-Google-Smtp-Source: AA0mqf715PGiK/skZorsDOENFytM9RM+oBCdBzGyr61asr6z7VClRX1OV3qERQpG1a7XFGWIfKH5nQ== X-Received: by 2002:a05:6512:3092:b0:4a4:68b7:e736 with SMTP id z18-20020a056512309200b004a468b7e736mr15617696lfd.32.1671504446773; Mon, 19 Dec 2022 18:47:26 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id e13-20020a05651236cd00b004b5a85e369asm1274866lfs.252.2022.12.19.18.47.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 18:47:26 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v3 05/15] thermal/drivers/tsens: Drop msm8976-specific defines Date: Tue, 20 Dec 2022 04:47:11 +0200 Message-Id: <20221220024721.947147-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> References: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop msm8976-specific defines, which duplicate generic ones. Fixes: 0e580290170d ("thermal: qcom: tsens-v1: Add support for MSM8956 and MSM8976") Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v1.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 96ef12d47bff..a7f53966156b 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -78,11 +78,6 @@ #define MSM8976_CAL_SEL_MASK 0x3 -#define MSM8976_CAL_DEGC_PT1 30 -#define MSM8976_CAL_DEGC_PT2 120 -#define MSM8976_SLOPE_FACTOR 1000 -#define MSM8976_SLOPE_DEFAULT 3200 - /* eeprom layout data for qcs404/405 (v1) */ #define BASE0_MASK 0x000007f8 #define BASE1_MASK 0x0007f800 @@ -160,8 +155,8 @@ static void compute_intercept_slope_8976(struct tsens_priv *priv, priv->sensor[10].slope = 3286; for (i = 0; i < priv->num_sensors; i++) { - priv->sensor[i].offset = (p1[i] * MSM8976_SLOPE_FACTOR) - - (MSM8976_CAL_DEGC_PT1 * + priv->sensor[i].offset = (p1[i] * SLOPE_FACTOR) - + (CAL_DEGC_PT1 * priv->sensor[i].slope); } } From patchwork Tue Dec 20 02:47:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635713 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AF94C54E76 for ; Tue, 20 Dec 2022 02:47:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232920AbiLTCrd (ORCPT ); Mon, 19 Dec 2022 21:47:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39280 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232921AbiLTCra (ORCPT ); Mon, 19 Dec 2022 21:47:30 -0500 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DDF013D08 for ; Mon, 19 Dec 2022 18:47:29 -0800 (PST) Received: by mail-lf1-x134.google.com with SMTP id o6so11705532lfi.5 for ; Mon, 19 Dec 2022 18:47:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V7pw5sy4GHoiVeao2U3KoW+RiJYHiL2flqfvF1Vr6T4=; b=Ahu6umBtsTAmFKHZc3zRr5TH5jpmUzw+al7//r4BVR7m3nd8s1fOQy2Ontgl1d1QtI EBgwf+vJa4Fl5LTOL96I1GguYyGQlwnEXubG20x4KbNa8eaEWmVvF2FHFDuQer/+hhiE aKu9siy2lzbqTuYZ8Pt/wn+em71CLqEVutvdIFHIvl5ogKUlwA4FqYDGIkfhiH+jfTUg Dc+fd99M4p6xzzdtUAD6cO8ozXnTMYzX348l13XS9xC7v20fAak2MBGE4HdMVtwAEjRd xU7r94+B6y9En4xPIT+UDlhUKZtGV9HsQxcnBTAbN6C1V6Va0jTw1Y7ULMJmVZ4MXnfU +5gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=V7pw5sy4GHoiVeao2U3KoW+RiJYHiL2flqfvF1Vr6T4=; b=TLm2nPqZdsCOc+U00vnxyul1Hky8+zXvQHydDpxpQ4X7PG7PHzWLHZH/JnXRRkF5S0 poJACmxg44hOTEVtWChZApsNtjtzBWSYxJEqegawFZ8VBvcx0Vaf3V6Fu+bdZ9x32re4 IY0IiAoC36UMnAr3hlC4mQkA7RSr/ZCYx2NnTO4KVsUoYW8R4rq4egtARFzAwf5d32QS PzKSrxMWkUN2+6tsN/nGQK6OmbY76LQatjZ8CVRgHoYz+UAscCw40K7lV8aJ2dMUvhFx +VNRl7VG+yZ5IAtYqcxQigjC0FMMPtwfuRH7QLF46ttzmjn4OOneKMNiwv4+T/1EalsO EGvg== X-Gm-Message-State: ANoB5pnUGtXz9uXpRFWmEilYA3BRSdw8i41gP0Xp3i0yY2j83PPyixa3 fBntrv1qLRMY9bIsEFYhzkCDWA== X-Google-Smtp-Source: AA0mqf5GbLoYnbfWia4zjxfzB3sEDJ4IbFrXh7Q292Wg1oMTGpA+nHPBXwyXqpdrqLpX8yrsHT8R4g== X-Received: by 2002:a05:6512:3e06:b0:4b5:9bfa:801a with SMTP id i6-20020a0565123e0600b004b59bfa801amr14031302lfv.46.1671504447678; Mon, 19 Dec 2022 18:47:27 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id e13-20020a05651236cd00b004b5a85e369asm1274866lfs.252.2022.12.19.18.47.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 18:47:27 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v3 06/15] thermal/drivers/tsens: Sort out msm8976 vs msm8956 data Date: Tue, 20 Dec 2022 04:47:12 +0200 Message-Id: <20221220024721.947147-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> References: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Tsens driver mentions that msm8976 data should be used for both msm8976 and msm8956 SoCs. This is not quite correct, as according to the vendor kernels, msm8976 should use standard slope values (3200), while msm8956 really uses the slope values found in the driver. Add separate compatibility string for msm8956, move slope value overrides to the corresponding init function and use the standard compute_intercept_slope() function for both platforms. Fixes: 0e580290170d ("thermal: qcom: tsens-v1: Add support for MSM8956 and MSM8976") Cc: AngeloGioacchino Del Regno Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v1.c | 56 ++++++++++++++++++--------------- drivers/thermal/qcom/tsens.c | 3 ++ drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 34 insertions(+), 27 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index a7f53966156b..83c2853546d0 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -137,30 +137,6 @@ #define CAL_SEL_MASK 7 #define CAL_SEL_SHIFT 0 -static void compute_intercept_slope_8976(struct tsens_priv *priv, - u32 *p1, u32 *p2, u32 mode) -{ - int i; - - priv->sensor[0].slope = 3313; - priv->sensor[1].slope = 3275; - priv->sensor[2].slope = 3320; - priv->sensor[3].slope = 3246; - priv->sensor[4].slope = 3279; - priv->sensor[5].slope = 3257; - priv->sensor[6].slope = 3234; - priv->sensor[7].slope = 3269; - priv->sensor[8].slope = 3255; - priv->sensor[9].slope = 3239; - priv->sensor[10].slope = 3286; - - for (i = 0; i < priv->num_sensors; i++) { - priv->sensor[i].offset = (p1[i] * SLOPE_FACTOR) - - (CAL_DEGC_PT1 * - priv->sensor[i].slope); - } -} - static int calibrate_v1(struct tsens_priv *priv) { u32 base0 = 0, base1 = 0; @@ -286,7 +262,7 @@ static int calibrate_8976(struct tsens_priv *priv) break; } - compute_intercept_slope_8976(priv, p1, p2, mode); + compute_intercept_slope(priv, p1, p2, mode); kfree(qfprom_cdata); return 0; @@ -360,6 +336,22 @@ static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0), }; +static int __init init_8956(struct tsens_priv *priv) { + priv->sensor[0].slope = 3313; + priv->sensor[1].slope = 3275; + priv->sensor[2].slope = 3320; + priv->sensor[3].slope = 3246; + priv->sensor[4].slope = 3279; + priv->sensor[5].slope = 3257; + priv->sensor[6].slope = 3234; + priv->sensor[7].slope = 3269; + priv->sensor[8].slope = 3255; + priv->sensor[9].slope = 3239; + priv->sensor[10].slope = 3286; + + return init_common(priv); +} + static const struct tsens_ops ops_generic_v1 = { .init = init_common, .calibrate = calibrate_v1, @@ -372,13 +364,25 @@ struct tsens_plat_data data_tsens_v1 = { .fields = tsens_v1_regfields, }; +static const struct tsens_ops ops_8956 = { + .init = init_8956, + .calibrate = calibrate_8976, + .get_temp = get_temp_tsens_valid, +}; + +struct tsens_plat_data data_8956 = { + .num_sensors = 11, + .ops = &ops_8956, + .feat = &tsens_v1_feat, + .fields = tsens_v1_regfields, +}; + static const struct tsens_ops ops_8976 = { .init = init_common, .calibrate = calibrate_8976, .get_temp = get_temp_tsens_valid, }; -/* Valid for both MSM8956 and MSM8976. */ struct tsens_plat_data data_8976 = { .num_sensors = 11, .ops = &ops_8976, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index b5b136ff323f..b191e19df93d 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -983,6 +983,9 @@ static const struct of_device_id tsens_table[] = { }, { .compatible = "qcom,msm8939-tsens", .data = &data_8939, + }, { + .compatible = "qcom,msm8956-tsens", + .data = &data_8956, }, { .compatible = "qcom,msm8960-tsens", .data = &data_8960, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 899af128855f..7dd5fc246894 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -594,7 +594,7 @@ extern struct tsens_plat_data data_8960; extern struct tsens_plat_data data_8916, data_8939, data_8974, data_9607; /* TSENS v1 targets */ -extern struct tsens_plat_data data_tsens_v1, data_8976; +extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956; /* TSENS v2 targets */ extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; From patchwork Tue Dec 20 02:47:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635712 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFBEFC3DA7B for ; Tue, 20 Dec 2022 02:47:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232839AbiLTCrd (ORCPT ); Mon, 19 Dec 2022 21:47:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232589AbiLTCrb (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id e13-20020a05651236cd00b004b5a85e369asm1274866lfs.252.2022.12.19.18.47.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 18:47:29 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Shawn Guo , Bryan O'Donoghue Subject: [PATCH v3 08/15] thermal/drivers/tsens: Drop single-cell code for msm8939 Date: Tue, 20 Dec 2022 04:47:14 +0200 Message-Id: <20221220024721.947147-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> References: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There is no dtsi file for msm8939 in the kernel sources. Drop the compatibility with unofficial dtsi and remove support for handling the single-cell calibration data on msm8939. Cc: Shawn Guo Cc: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 146 ++---------------------------- 1 file changed, 7 insertions(+), 139 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 7f87b403c6fa..8f1ea7075354 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -48,63 +48,6 @@ #define MSM8916_CAL_SEL_MASK 0xe0000000 #define MSM8916_CAL_SEL_SHIFT 29 -/* eeprom layout data for 8939 */ -#define MSM8939_BASE0_MASK 0x000000ff -#define MSM8939_BASE1_MASK 0xff000000 -#define MSM8939_BASE0_SHIFT 0 -#define MSM8939_BASE1_SHIFT 24 - -#define MSM8939_S0_P1_MASK 0x000001f8 -#define MSM8939_S1_P1_MASK 0x001f8000 -#define MSM8939_S2_P1_MASK_0_4 0xf8000000 -#define MSM8939_S2_P1_MASK_5 0x00000001 -#define MSM8939_S3_P1_MASK 0x00001f80 -#define MSM8939_S4_P1_MASK 0x01f80000 -#define MSM8939_S5_P1_MASK 0x00003f00 -#define MSM8939_S6_P1_MASK 0x03f00000 -#define MSM8939_S7_P1_MASK 0x0000003f -#define MSM8939_S8_P1_MASK 0x0003f000 -#define MSM8939_S9_P1_MASK 0x07e00000 - -#define MSM8939_S0_P2_MASK 0x00007e00 -#define MSM8939_S1_P2_MASK 0x07e00000 -#define MSM8939_S2_P2_MASK 0x0000007e -#define MSM8939_S3_P2_MASK 0x0007e000 -#define MSM8939_S4_P2_MASK 0x7e000000 -#define MSM8939_S5_P2_MASK 0x000fc000 -#define MSM8939_S6_P2_MASK 0xfc000000 -#define MSM8939_S7_P2_MASK 0x00000fc0 -#define MSM8939_S8_P2_MASK 0x00fc0000 -#define MSM8939_S9_P2_MASK_0_4 0xf8000000 -#define MSM8939_S9_P2_MASK_5 0x00002000 - -#define MSM8939_S0_P1_SHIFT 3 -#define MSM8939_S1_P1_SHIFT 15 -#define MSM8939_S2_P1_SHIFT_0_4 27 -#define MSM8939_S2_P1_SHIFT_5 0 -#define MSM8939_S3_P1_SHIFT 7 -#define MSM8939_S4_P1_SHIFT 19 -#define MSM8939_S5_P1_SHIFT 8 -#define MSM8939_S6_P1_SHIFT 20 -#define MSM8939_S7_P1_SHIFT 0 -#define MSM8939_S8_P1_SHIFT 12 -#define MSM8939_S9_P1_SHIFT 21 - -#define MSM8939_S0_P2_SHIFT 9 -#define MSM8939_S1_P2_SHIFT 21 -#define MSM8939_S2_P2_SHIFT 1 -#define MSM8939_S3_P2_SHIFT 13 -#define MSM8939_S4_P2_SHIFT 25 -#define MSM8939_S5_P2_SHIFT 14 -#define MSM8939_S6_P2_SHIFT 26 -#define MSM8939_S7_P2_SHIFT 6 -#define MSM8939_S8_P2_SHIFT 18 -#define MSM8939_S9_P2_SHIFT_0_4 27 -#define MSM8939_S9_P2_SHIFT_5 13 - -#define MSM8939_CAL_SEL_MASK 0x7 -#define MSM8939_CAL_SEL_SHIFT 0 - /* eeprom layout data for 8974 */ #define BASE1_MASK 0xff #define S0_P1_MASK 0x3f00 @@ -284,81 +227,6 @@ static int calibrate_8916(struct tsens_priv *priv) return 0; } -static int calibrate_8939(struct tsens_priv *priv) -{ - int base0 = 0, base1 = 0, i; - u32 p1[10], p2[10]; - int mode = 0; - u32 *qfprom_cdata; - u32 cdata[6]; - int ret; - - ret = tsens_calibrate_common(priv); - if (!ret) - return 0; - - qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); - if (IS_ERR(qfprom_cdata)) - return PTR_ERR(qfprom_cdata); - - /* Mapping between qfprom nvmem and calibration data */ - cdata[0] = qfprom_cdata[12]; - cdata[1] = qfprom_cdata[13]; - cdata[2] = qfprom_cdata[0]; - cdata[3] = qfprom_cdata[1]; - cdata[4] = qfprom_cdata[22]; - cdata[5] = qfprom_cdata[21]; - - mode = (cdata[0] & MSM8939_CAL_SEL_MASK) >> MSM8939_CAL_SEL_SHIFT; - dev_dbg(priv->dev, "calibration mode is %d\n", mode); - - switch (mode) { - case TWO_PT_CALIB: - base1 = (cdata[3] & MSM8939_BASE1_MASK) >> MSM8939_BASE1_SHIFT; - p2[0] = (cdata[0] & MSM8939_S0_P2_MASK) >> MSM8939_S0_P2_SHIFT; - p2[1] = (cdata[0] & MSM8939_S1_P2_MASK) >> MSM8939_S1_P2_SHIFT; - p2[2] = (cdata[1] & MSM8939_S2_P2_MASK) >> MSM8939_S2_P2_SHIFT; - p2[3] = (cdata[1] & MSM8939_S3_P2_MASK) >> MSM8939_S3_P2_SHIFT; - p2[4] = (cdata[1] & MSM8939_S4_P2_MASK) >> MSM8939_S4_P2_SHIFT; - p2[5] = (cdata[2] & MSM8939_S5_P2_MASK) >> MSM8939_S5_P2_SHIFT; - p2[6] = (cdata[2] & MSM8939_S6_P2_MASK) >> MSM8939_S6_P2_SHIFT; - p2[7] = (cdata[3] & MSM8939_S7_P2_MASK) >> MSM8939_S7_P2_SHIFT; - p2[8] = (cdata[3] & MSM8939_S8_P2_MASK) >> MSM8939_S8_P2_SHIFT; - p2[9] = (cdata[4] & MSM8939_S9_P2_MASK_0_4) >> MSM8939_S9_P2_SHIFT_0_4; - p2[9] |= ((cdata[5] & MSM8939_S9_P2_MASK_5) >> MSM8939_S9_P2_SHIFT_5) << 5; - for (i = 0; i < priv->num_sensors; i++) - p2[i] = (base1 + p2[i]) << 2; - fallthrough; - case ONE_PT_CALIB2: - base0 = (cdata[2] & MSM8939_BASE0_MASK) >> MSM8939_BASE0_SHIFT; - p1[0] = (cdata[0] & MSM8939_S0_P1_MASK) >> MSM8939_S0_P1_SHIFT; - p1[1] = (cdata[0] & MSM8939_S1_P1_MASK) >> MSM8939_S1_P1_SHIFT; - p1[2] = (cdata[0] & MSM8939_S2_P1_MASK_0_4) >> MSM8939_S2_P1_SHIFT_0_4; - p1[2] |= ((cdata[1] & MSM8939_S2_P1_MASK_5) >> MSM8939_S2_P1_SHIFT_5) << 5; - p1[3] = (cdata[1] & MSM8939_S3_P1_MASK) >> MSM8939_S3_P1_SHIFT; - p1[4] = (cdata[1] & MSM8939_S4_P1_MASK) >> MSM8939_S4_P1_SHIFT; - p1[5] = (cdata[2] & MSM8939_S5_P1_MASK) >> MSM8939_S5_P1_SHIFT; - p1[6] = (cdata[2] & MSM8939_S6_P1_MASK) >> MSM8939_S6_P1_SHIFT; - p1[7] = (cdata[3] & MSM8939_S7_P1_MASK) >> MSM8939_S7_P1_SHIFT; - p1[8] = (cdata[3] & MSM8939_S8_P1_MASK) >> MSM8939_S8_P1_SHIFT; - p1[9] = (cdata[4] & MSM8939_S9_P1_MASK) >> MSM8939_S9_P1_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p1[i] = ((base0) + p1[i]) << 2; - break; - default: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] = 500; - p2[i] = 780; - } - break; - } - - compute_intercept_slope(priv, p1, p2, mode); - kfree(qfprom_cdata); - - return 0; -} - static int calibrate_8974(struct tsens_priv *priv) { int base1 = 0, base2 = 0, i; @@ -598,6 +466,12 @@ static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = { [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0), }; +static const struct tsens_ops ops_v0_1 = { + .init = init_common, + .calibrate = tsens_calibrate_common, + .get_temp = get_temp_common, +}; + static const struct tsens_ops ops_8916 = { .init = init_common, .calibrate = calibrate_8916, @@ -613,15 +487,9 @@ struct tsens_plat_data data_8916 = { .fields = tsens_v0_1_regfields, }; -static const struct tsens_ops ops_8939 = { - .init = init_common, - .calibrate = calibrate_8939, - .get_temp = get_temp_common, -}; - struct tsens_plat_data data_8939 = { .num_sensors = 10, - .ops = &ops_8939, + .ops = &ops_v0_1, .hw_ids = (unsigned int []){ 0, 1, 2, 3, 5, 6, 7, 8, 9, 10 }, .feat = &tsens_v0_1_feat, From patchwork Tue Dec 20 02:47:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635711 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A13F0C4708D for ; Tue, 20 Dec 2022 02:47:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232958AbiLTCrg (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id e13-20020a05651236cd00b004b5a85e369asm1274866lfs.252.2022.12.19.18.47.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 18:47:31 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v3 10/15] thermal/drivers/tsens: Drop single-cell code for msm8976/msm8956 Date: Tue, 20 Dec 2022 04:47:16 +0200 Message-Id: <20221220024721.947147-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> References: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There is no dtsi file for msm8976 in the kernel sources. Drop the compatibility with unofficial dtsi and remove support for handling the single-cell calibration data on msm8976. Cc: AngeloGioacchino Del Regno Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v1.c | 126 +------------------------------- 1 file changed, 2 insertions(+), 124 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 89955522041d..9151c1043a11 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -21,63 +21,6 @@ #define TM_HIGH_LOW_INT_STATUS_OFF 0x0088 #define TM_HIGH_LOW_Sn_INT_THRESHOLD_OFF 0x0090 -/* eeprom layout data for msm8956/76 (v1) */ -#define MSM8976_BASE0_MASK 0xff -#define MSM8976_BASE1_MASK 0xff -#define MSM8976_BASE1_SHIFT 8 - -#define MSM8976_S0_P1_MASK 0x3f00 -#define MSM8976_S1_P1_MASK 0x3f00000 -#define MSM8976_S2_P1_MASK 0x3f -#define MSM8976_S3_P1_MASK 0x3f000 -#define MSM8976_S4_P1_MASK 0x3f00 -#define MSM8976_S5_P1_MASK 0x3f00000 -#define MSM8976_S6_P1_MASK 0x3f -#define MSM8976_S7_P1_MASK 0x3f000 -#define MSM8976_S8_P1_MASK 0x1f8 -#define MSM8976_S9_P1_MASK 0x1f8000 -#define MSM8976_S10_P1_MASK 0xf8000000 -#define MSM8976_S10_P1_MASK_1 0x1 - -#define MSM8976_S0_P2_MASK 0xfc000 -#define MSM8976_S1_P2_MASK 0xfc000000 -#define MSM8976_S2_P2_MASK 0xfc0 -#define MSM8976_S3_P2_MASK 0xfc0000 -#define MSM8976_S4_P2_MASK 0xfc000 -#define MSM8976_S5_P2_MASK 0xfc000000 -#define MSM8976_S6_P2_MASK 0xfc0 -#define MSM8976_S7_P2_MASK 0xfc0000 -#define MSM8976_S8_P2_MASK 0x7e00 -#define MSM8976_S9_P2_MASK 0x7e00000 -#define MSM8976_S10_P2_MASK 0x7e - -#define MSM8976_S0_P1_SHIFT 8 -#define MSM8976_S1_P1_SHIFT 20 -#define MSM8976_S2_P1_SHIFT 0 -#define MSM8976_S3_P1_SHIFT 12 -#define MSM8976_S4_P1_SHIFT 8 -#define MSM8976_S5_P1_SHIFT 20 -#define MSM8976_S6_P1_SHIFT 0 -#define MSM8976_S7_P1_SHIFT 12 -#define MSM8976_S8_P1_SHIFT 3 -#define MSM8976_S9_P1_SHIFT 15 -#define MSM8976_S10_P1_SHIFT 27 -#define MSM8976_S10_P1_SHIFT_1 0 - -#define MSM8976_S0_P2_SHIFT 14 -#define MSM8976_S1_P2_SHIFT 26 -#define MSM8976_S2_P2_SHIFT 6 -#define MSM8976_S3_P2_SHIFT 18 -#define MSM8976_S4_P2_SHIFT 14 -#define MSM8976_S5_P2_SHIFT 26 -#define MSM8976_S6_P2_SHIFT 6 -#define MSM8976_S7_P2_SHIFT 18 -#define MSM8976_S8_P2_SHIFT 9 -#define MSM8976_S9_P2_SHIFT 21 -#define MSM8976_S10_P2_SHIFT 1 - -#define MSM8976_CAL_SEL_MASK 0x3 - /* eeprom layout data for qcs404/405 (v1) */ #define BASE0_MASK 0x000007f8 #define BASE1_MASK 0x0007f800 @@ -207,71 +150,6 @@ static int calibrate_v1(struct tsens_priv *priv) return 0; } -static int calibrate_8976(struct tsens_priv *priv) -{ - int base0 = 0, base1 = 0, i; - u32 p1[11], p2[11]; - int mode = 0, tmp = 0; - u32 *qfprom_cdata; - - qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); - if (IS_ERR(qfprom_cdata)) - return PTR_ERR(qfprom_cdata); - - mode = (qfprom_cdata[4] & MSM8976_CAL_SEL_MASK); - dev_dbg(priv->dev, "calibration mode is %d\n", mode); - - switch (mode) { - case TWO_PT_CALIB: - base1 = (qfprom_cdata[2] & MSM8976_BASE1_MASK) >> MSM8976_BASE1_SHIFT; - p2[0] = (qfprom_cdata[0] & MSM8976_S0_P2_MASK) >> MSM8976_S0_P2_SHIFT; - p2[1] = (qfprom_cdata[0] & MSM8976_S1_P2_MASK) >> MSM8976_S1_P2_SHIFT; - p2[2] = (qfprom_cdata[1] & MSM8976_S2_P2_MASK) >> MSM8976_S2_P2_SHIFT; - p2[3] = (qfprom_cdata[1] & MSM8976_S3_P2_MASK) >> MSM8976_S3_P2_SHIFT; - p2[4] = (qfprom_cdata[2] & MSM8976_S4_P2_MASK) >> MSM8976_S4_P2_SHIFT; - p2[5] = (qfprom_cdata[2] & MSM8976_S5_P2_MASK) >> MSM8976_S5_P2_SHIFT; - p2[6] = (qfprom_cdata[3] & MSM8976_S6_P2_MASK) >> MSM8976_S6_P2_SHIFT; - p2[7] = (qfprom_cdata[3] & MSM8976_S7_P2_MASK) >> MSM8976_S7_P2_SHIFT; - p2[8] = (qfprom_cdata[4] & MSM8976_S8_P2_MASK) >> MSM8976_S8_P2_SHIFT; - p2[9] = (qfprom_cdata[4] & MSM8976_S9_P2_MASK) >> MSM8976_S9_P2_SHIFT; - p2[10] = (qfprom_cdata[5] & MSM8976_S10_P2_MASK) >> MSM8976_S10_P2_SHIFT; - - for (i = 0; i < priv->num_sensors; i++) - p2[i] = ((base1 + p2[i]) << 2); - fallthrough; - case ONE_PT_CALIB2: - base0 = qfprom_cdata[0] & MSM8976_BASE0_MASK; - p1[0] = (qfprom_cdata[0] & MSM8976_S0_P1_MASK) >> MSM8976_S0_P1_SHIFT; - p1[1] = (qfprom_cdata[0] & MSM8976_S1_P1_MASK) >> MSM8976_S1_P1_SHIFT; - p1[2] = (qfprom_cdata[1] & MSM8976_S2_P1_MASK) >> MSM8976_S2_P1_SHIFT; - p1[3] = (qfprom_cdata[1] & MSM8976_S3_P1_MASK) >> MSM8976_S3_P1_SHIFT; - p1[4] = (qfprom_cdata[2] & MSM8976_S4_P1_MASK) >> MSM8976_S4_P1_SHIFT; - p1[5] = (qfprom_cdata[2] & MSM8976_S5_P1_MASK) >> MSM8976_S5_P1_SHIFT; - p1[6] = (qfprom_cdata[3] & MSM8976_S6_P1_MASK) >> MSM8976_S6_P1_SHIFT; - p1[7] = (qfprom_cdata[3] & MSM8976_S7_P1_MASK) >> MSM8976_S7_P1_SHIFT; - p1[8] = (qfprom_cdata[4] & MSM8976_S8_P1_MASK) >> MSM8976_S8_P1_SHIFT; - p1[9] = (qfprom_cdata[4] & MSM8976_S9_P1_MASK) >> MSM8976_S9_P1_SHIFT; - p1[10] = (qfprom_cdata[4] & MSM8976_S10_P1_MASK) >> MSM8976_S10_P1_SHIFT; - tmp = (qfprom_cdata[5] & MSM8976_S10_P1_MASK_1) << MSM8976_S10_P1_SHIFT_1; - p1[10] |= tmp; - - for (i = 0; i < priv->num_sensors; i++) - p1[i] = (((base0) + p1[i]) << 2); - break; - default: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] = 500; - p2[i] = 780; - } - break; - } - - compute_intercept_slope(priv, p1, p2, mode); - kfree(qfprom_cdata); - - return 0; -} - /* v1.x: msm8956,8976,qcs404,405 */ static struct tsens_features tsens_v1_feat = { @@ -370,7 +248,7 @@ struct tsens_plat_data data_tsens_v1 = { static const struct tsens_ops ops_8956 = { .init = init_8956, - .calibrate = calibrate_8976, + .calibrate = tsens_calibrate_common, .get_temp = get_temp_tsens_valid, }; @@ -383,7 +261,7 @@ struct tsens_plat_data data_8956 = { static const struct tsens_ops ops_8976 = { .init = init_common, - .calibrate = calibrate_8976, + .calibrate = tsens_calibrate_common, .get_temp = get_temp_tsens_valid, }; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id e13-20020a05651236cd00b004b5a85e369asm1274866lfs.252.2022.12.19.18.47.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 18:47:32 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 12/15] arm64: dts: qcom: msm8916: specify per-sensor calibration cells Date: Tue, 20 Dec 2022 04:47:18 +0200 Message-Id: <20221220024721.947147-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> References: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 70 ++++++++++++++++++++++++--- 1 file changed, 64 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 2ca8e977fc2a..af7ba66bb7cd 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -442,11 +442,57 @@ qfprom: qfprom@5c000 { reg = <0x0005c000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0xd0 0x8>; + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 7>; }; - tsens_calsel: calsel@ec { - reg = <0xec 0x4>; + tsens_s0_p1: s0_p1@d0 { + reg = <0xd0 0x2>; + bits = <7 5>; + }; + tsens_s0_p2: s0_p2@d1 { + reg = <0xd1 0x2>; + bits = <4 5>; + }; + tsens_s1_p1: s1_p1@d2 { + reg = <0xd2 0x1>; + bits = <1 5>; + }; + tsens_s1_p2: s1_p2@d2 { + reg = <0xd2 0x2>; + bits = <6 5>; + }; + tsens_s2_p1: s2_p1@d3 { + reg = <0xd3 0x1>; + bits = <3 5>; + }; + tsens_s2_p2: s2_p2@d4 { + reg = <0xd4 0x1>; + bits = <0 5>; + }; + tsens_s3_p1: s3_p1@d4 { + reg = <0xd4 0x2>; + bits = <5 5>; + }; + tsens_s3_p2: s3_p2@d5 { + reg = <0xd5 0x1>; + bits = <2 5>; + }; + tsens_s4_p1: s4_p1@d5 { + reg = <0xd5 0x2>; + bits = <7 5>; + }; + tsens_s4_p2: s4_p2@d6 { + reg = <0xd6 0x2>; + bits = <4 5>; + }; + tsens_base2: base2@d7 { + reg = <0xd7 0x1>; + bits = <1 7>; + }; + tsens_mode: mode@ec { + reg = <0xef 0x1>; + bits = <5 3>; }; }; @@ -473,8 +519,20 @@ tsens: thermal-sensor@4a9000 { compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; reg = <0x004a9000 0x1000>, /* TM */ <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; - nvmem-cell-names = "calib", "calib_sel"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2"; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id e13-20020a05651236cd00b004b5a85e369asm1274866lfs.252.2022.12.19.18.47.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Dec 2022 18:47:34 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 13/15] arm64: dts: qcom: qcs404: specify per-sensor calibration cells Date: Tue, 20 Dec 2022 04:47:19 +0200 Message-Id: <20221220024721.947147-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> References: <20221220024721.947147-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 121 +++++++++++++++++++++++++-- 1 file changed, 116 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index a5324eecb50a..362764347006 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -366,13 +366,102 @@ qfprom: qfprom@a4000 { reg = <0x000a4000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0x1f8 0x14>; - }; cpr_efuse_speedbin: speedbin@13c { reg = <0x13c 0x4>; bits = <2 3>; }; + tsens_s0_p1: s0_p1@1f8 { + reg = <0x1f8 0x1>; + bits = <0 6>; + }; + tsens_s0_p2: s0_p2@1f8 { + reg = <0x1f8 0x2>; + bits = <6 6>; + }; + tsens_s1_p1: s1_p1@1f9 { + reg = <0x1f9 0x2>; + bits = <4 6>; + }; + tsens_s1_p2: s1_p2@1fa { + reg = <0x1fa 0x1>; + bits = <2 6>; + }; + tsens_s2_p1: s2_p1@1fb { + reg = <0x1fb 0x1>; + bits = <0 6>; + }; + tsens_s2_p2: s2_p2@1fb { + reg = <0x1fb 0x2>; + bits = <6 6>; + }; + tsens_s3_p1: s3_p1@1fc { + reg = <0x1fc 0x2>; + bits = <4 6>; + }; + tsens_s3_p2: s3_p2@1fd { + reg = <0x1fd 0x1>; + bits = <2 6>; + }; + tsens_s4_p1: s4_p1@1fe { + reg = <0x1fe 0x1>; + bits = <0 6>; + }; + tsens_s4_p2: s4_p2@1fe { + reg = <0x1fe 0x2>; + bits = <6 6>; + }; + tsens_s5_p1: s5_p1@200 { + reg = <0x200 0x1>; + bits = <0 6>; + }; + tsens_s5_p2: s5_p2@200 { + reg = <0x200 0x2>; + bits = <6 6>; + }; + tsens_s6_p1: s6_p1@201 { + reg = <0x201 0x2>; + bits = <4 6>; + }; + tsens_s6_p2: s6_p2@202 { + reg = <0x202 0x1>; + bits = <2 6>; + }; + tsens_s7_p1: s7_p1@203 { + reg = <0x203 0x1>; + bits = <0 6>; + }; + tsens_s7_p2: s7_p2@203 { + reg = <0x203 0x2>; + bits = <6 6>; + }; + tsens_s8_p1: s8_p1@204 { + reg = <0x204 0x2>; + bits = <4 6>; + }; + tsens_s8_p2: s8_p2@205 { + reg = <0x205 0x1>; + bits = <2 6>; + }; + tsens_s9_p1: s9_p1@206 { + reg = <0x206 0x1>; + bits = <0 6>; + }; + tsens_s9_p2: s9_p2@206 { + reg = <0x206 0x2>; + bits = <6 6>; + }; + tsens_mode: mode@208 { + reg = <0x208 1>; + bits = <0 3>; + }; + tsens_base1: base1@208 { + reg = <0x208 2>; + bits = <3 8>; + }; + tsens_base2: base2@208 { + reg = <0x209 2>; + bits = <3 8>; + }; cpr_efuse_quot_offset1: qoffset1@231 { reg = <0x231 0x4>; bits = <4 7>; @@ -447,8 +536,30 @@ tsens: thermal-sensor@4a9000 { compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; reg = <0x004a9000 0x1000>, /* TM */ <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>; - nvmem-cell-names = "calib"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2"; #qcom,sensors = <10>; interrupts = ; interrupt-names = "uplow";