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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:21 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v4 01/20] dt-bindings: thermal: tsens: add msm8956 compat Date: Wed, 21 Dec 2022 04:05:01 +0200 Message-Id: <20221221020520.1326964-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org When adding support for msm8976 it was thought that msm8956 would reuse the same compat. However checking the vendor kernel revealed that these two platforms use different slope values for calculating the calibration data. Add new compatible for the tsens on msm8956 SoC. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 0231f187b097..f3660af0b3bf 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -37,6 +37,7 @@ properties: - description: v1 of TSENS items: - enum: + - qcom,msm8956-tsens - qcom,msm8976-tsens - qcom,qcs404-tsens - const: qcom,tsens-v1 From patchwork Wed Dec 21 02:05:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635686 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4001AC46467 for ; Wed, 21 Dec 2022 02:05:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234349AbiLUCF2 (ORCPT ); Tue, 20 Dec 2022 21:05:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234326AbiLUCFZ (ORCPT ); Tue, 20 Dec 2022 21:05:25 -0500 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B687D1FCD9 for ; Tue, 20 Dec 2022 18:05:24 -0800 (PST) Received: by mail-lf1-x136.google.com with SMTP id j4so21443747lfk.0 for ; Tue, 20 Dec 2022 18:05:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FjTuXszLa3PpvcC6GObAES0NeWmHYF7aB2zTBhEiXEk=; b=kHY1rWgQvT3q1BXkZe6BfIfA66EHDVKvVf1mRcgeZn9BgHXLfWva6LX6dZF/v/OMcB kEyHm+rsWw45ZUIsPfwzvrUrUxkJmbhEM0B1H5hAozYUYDzlP27R0IZaTJCL63TTX7kr bzQsGygNgcbmxBO8++oQOQevdlTys5fabf9udD8DT5RSqNJrUX/q7mSG2AuuCB7n3aPZ yhnasyQDy0mxu1zhQLLh5NtF0soRd+IEnzFZr77TNTj2DRi/3RZ7pt9391Bj2ev72+VT ODt61FvEcS0Z2KCVSvg9RmRri3HsXe3azYE1ahvgV74EbN07GiQwiWwDyHC5JGmW0Iz1 kCsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FjTuXszLa3PpvcC6GObAES0NeWmHYF7aB2zTBhEiXEk=; b=zCzB81z0jxmIXMVQjdfNZ2UKHBrCvQMlTPkFCa+eKyMMWvw7B6uZKL4auyN/reziHN SZSY0UUsY689w4GeragGr6eHTl1dWCqCqNIkGNzOtMddfi9Rs9Yx308jUir+y6SNqcJw dwF+UvdIRi5JsDOUT/CdVk4Vnxie04CK7NHI0yx6u13gz+a38+6ShgeUZd5OfJZofcSr ZVRWcIxQq5tfvqa0K1TcVqwV8jfMcTmlBPMeTZeF1DWPhY4muCLUAbvB+/gropm7i1vI YH9Ok7Yt5zvz6yXRi7yNyJTzwzj8YZt4MB1gMeSD+VBV3K9p8fwZX2NxjpXynrPNA354 0IVA== X-Gm-Message-State: AFqh2ko/B5XOwtUi05lAE+D5YLZGtQ3DdWFSWky/yYb+d5mdbNYGxiCa v0+McdHDgeE+BeDG2VbSplQi3w== X-Google-Smtp-Source: AMrXdXvmgjP300KGyPQq4HaUcs3TrwwMxxnY7uxBSzKdLnoSskCL4/KjkKEpX+AgAzkTnGp6KhZIKQ== X-Received: by 2002:a05:6512:c04:b0:4ad:6f9b:d683 with SMTP id z4-20020a0565120c0400b004ad6f9bd683mr1773083lfu.1.1671588323106; Tue, 20 Dec 2022 18:05:23 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:22 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v4 02/20] dt-bindings: thermal: tsens: support per-sensor calibration cells Date: Wed, 21 Dec 2022 04:05:02 +0200 Message-Id: <20221221020520.1326964-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Allow specifying the exact calibration mode and calibration data as nvmem cells, rather than specifying just a single calibration data blob. Acked-by: Krzysztof Kozlowski Reviewed-by: Amit Kucheria Signed-off-by: Dmitry Baryshkov --- .../bindings/thermal/qcom-tsens.yaml | 64 ++++++++++++++++--- 1 file changed, 54 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index f3660af0b3bf..da7b5bd4abd5 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -81,18 +81,62 @@ properties: maxItems: 2 nvmem-cells: - minItems: 1 - maxItems: 2 - description: - Reference to an nvmem node for the calibration data + oneOf: + - minItems: 1 + maxItems: 2 + description: + Reference to an nvmem node for the calibration data + - minItems: 5 + maxItems: 35 + description: | + Reference to nvmem cells for the calibration mode, two calibration + bases and two cells per each sensor nvmem-cell-names: - minItems: 1 - items: - - const: calib - - enum: - - calib_backup - - calib_sel + oneOf: + - minItems: 1 + items: + - const: calib + - enum: + - calib_backup + - calib_sel + - minItems: 5 + items: + - const: mode + - const: base1 + - const: base2 + - const: s0_p1 + - const: s0_p2 + - const: s1_p1 + - const: s1_p2 + - const: s2_p1 + - const: s2_p2 + - const: s3_p1 + - const: s3_p2 + - const: s4_p1 + - const: s4_p2 + - const: s5_p1 + - const: s5_p2 + - const: s6_p1 + - const: s6_p2 + - const: s7_p1 + - const: s7_p2 + - const: s8_p1 + - const: s8_p2 + - const: s9_p1 + - const: s9_p2 + - const: s10_p1 + - const: s10_p2 + - const: s11_p1 + - const: s11_p2 + - const: s12_p1 + - const: s12_p2 + - const: s13_p1 + - const: s13_p2 + - const: s14_p1 + - const: s14_p2 + - const: s15_p1 + - const: s15_p2 "#qcom,sensors": description: From patchwork Wed Dec 21 02:05:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635685 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E6C7C4708E for ; Wed, 21 Dec 2022 02:05:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230026AbiLUCFa (ORCPT ); Tue, 20 Dec 2022 21:05:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234223AbiLUCF0 (ORCPT ); Tue, 20 Dec 2022 21:05:26 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 944341F9F6 for ; Tue, 20 Dec 2022 18:05:25 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id z26so21349074lfu.8 for ; Tue, 20 Dec 2022 18:05:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fvuwLhbvCBU1vTHX00Mr3U7sB++VpvhJ7GWo/kANsp8=; b=ys8NuEmamhHWTgJXz6E/sUh8zBu0Mi9FWtLR+rm2TpsnuLhMFzPJRTuqcQtIBKtbfD CGLj0B2In4zNFXcLcDR41SjJWyQUZKQtEKFFraLNHd6znBCONeJZ5ThKz4xIH3XWAzpr spe6JkptMLX+9lqQJgZCg+jvTwnXG8xQN+CtvUMxNPdVeKMnIB6kXGc1EvkprskrscyH tsATEpbZb++LM0Pe61H5V9HeE0tnvsgmUEnIdKqJ2BjCYEhUjXB+1wY6lYTN13Bn3hTA f79/NeS/5IQ1iZJY5AyDR4SPUu67haCsoyqS/lRTRqRoHLkOhrFFiwC9JIkjugOTF8xH KvvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fvuwLhbvCBU1vTHX00Mr3U7sB++VpvhJ7GWo/kANsp8=; b=ntMV4fD9MKUxK/TspTSvTt8HFBEFejqj6qZcoVOVmlFa3RTI6rgwrwAEWDgIO70RAz WxOgoyLXScxKNchImrfr5Ff7J3fgwLQ9fAUpnJmiptZgTXb9lWoPmgWeARpiaTbiO51F 62ykkJDkXIp9cPI6Zhwuls16zer8sihmYjA+9vGaNAeMFZFUJZ3Fd5g1TGpjF9D3BG8w KYSPgKskza1nZ+tCCRTozEFIW+lnNbJ4Fejaa7IfgBTeYcSTeEEJCUai9dp0VOVCEzaN tabrSUDWTJs3t8eV7nWVJOd3XgEINPRNGVdPQnf5rPeKPx4f0f4dB6mgKItqRLB89DTO ghZA== X-Gm-Message-State: AFqh2kox+/o5fEYoQ81DVILoIdUPuH5zfVCjtpTfqsleuMHS6cGJpqO6 Yd3HlROruBRevRHDfr5EtEc7tw== X-Google-Smtp-Source: AMrXdXtt2jHcaBqkiRPXkRZqZX66xbNDlWNGwtuo5/JsPQq1R/r6laM0lToByew5x1NaRX4clS0PWw== X-Received: by 2002:ac2:5589:0:b0:4b5:8237:5c12 with SMTP id v9-20020ac25589000000b004b582375c12mr92337lfg.15.1671588324033; Tue, 20 Dec 2022 18:05:24 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:23 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v4 03/20] dt-bindings: thermal: tsens: add per-sensor cells for msm8974 Date: Wed, 21 Dec 2022 04:05:03 +0200 Message-Id: <20221221020520.1326964-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The msm8974 platform uses two sets of calibration data, add a special case to handle both of them. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../bindings/thermal/qcom-tsens.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index da7b5bd4abd5..3e6ba0509bd0 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -91,6 +91,11 @@ properties: description: | Reference to nvmem cells for the calibration mode, two calibration bases and two cells per each sensor + # special case for msm8974 / apq8084 + - maxItems: 51 + description: | + Reference to nvmem cells for the calibration mode, two calibration + bases and two cells per each sensor, main and backup copies, plus use_backup cell nvmem-cell-names: oneOf: @@ -137,6 +142,59 @@ properties: - const: s14_p2 - const: s15_p1 - const: s15_p2 + # special case for msm8974 / apq8084 + - items: + - const: mode + - const: base1 + - const: base2 + - const: s0_p1 + - const: s0_p2 + - const: s1_p1 + - const: s1_p2 + - const: s2_p1 + - const: s2_p2 + - const: s3_p1 + - const: s3_p2 + - const: s4_p1 + - const: s4_p2 + - const: s5_p1 + - const: s5_p2 + - const: s6_p1 + - const: s6_p2 + - const: s7_p1 + - const: s7_p2 + - const: s8_p1 + - const: s8_p2 + - const: s9_p1 + - const: s9_p2 + - const: s10_p1 + - const: s10_p2 + - const: use_backup + - const: mode_backup + - const: base1_backup + - const: base2_backup + - const: s0_p1_backup + - const: s0_p2_backup + - const: s1_p1_backup + - const: s1_p2_backup + - const: s2_p1_backup + - const: s2_p2_backup + - const: s3_p1_backup + - const: s3_p2_backup + - const: s4_p1_backup + - const: s4_p2_backup + - const: s5_p1_backup + - const: s5_p2_backup + - const: s6_p1_backup + - const: s6_p2_backup + - const: s7_p1_backup + - const: s7_p2_backup + - const: s8_p1_backup + - const: s8_p2_backup + - const: s9_p1_backup + - const: s9_p2_backup + - const: s10_p1_backup + - const: s10_p2_backup "#qcom,sensors": description: From patchwork Wed Dec 21 02:05:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 636061 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26724C4167B for ; Wed, 21 Dec 2022 02:05:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234357AbiLUCF3 (ORCPT ); Tue, 20 Dec 2022 21:05:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234172AbiLUCF0 (ORCPT ); Tue, 20 Dec 2022 21:05:26 -0500 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43BE91F9F9 for ; Tue, 20 Dec 2022 18:05:25 -0800 (PST) Received: by mail-lf1-x129.google.com with SMTP id y25so21336885lfa.9 for ; Tue, 20 Dec 2022 18:05:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5BDbnJ/AZBuA08A97uDDUpTRd6b7HncteZoPe22xbWk=; b=ZdTi0XhuCiiXAgq6dHlIWCmu1AoS9qcUq0MNJ418/Sr1cafTa6j0/n0glctSoz7LYq TYkboYI/kCl5PnKdi5la8pFB8/dYlGucIXx94J1ShzuCkbklIwvTPWT6p569geWmTaTT b6FPI95GdQGxRWPOSJPkXqO8Zh/WhI7yymOwdym3K84Gxq0P5S1Johax1Jp9RDh0hXtx ic2+Zd9o/wyENgfkPB6HIQImfEX9/wA6l03176JsVAzg+NGgJxy7uoDeLc5UMaeO2VVy KgPkS8ohTky/fT1VeNEHuJIMK/qwjDzSuxTmZHHlFEl4s/nqHbs5uYsG2k6Ep5BVnRGy VEag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5BDbnJ/AZBuA08A97uDDUpTRd6b7HncteZoPe22xbWk=; b=sQohTQeI9qpxmp0OgBYqg0ECfAtCz0cdvwIm+rgVUu/HK3/2XLkMD9AcGmJ4vPlKUJ bHc8yj68a1dnKBCp2ElaORW4RjMM4Ahe1rzQFXRIRbFohDaljiAZziccH3JBHKgDZ9e0 R4KmThEE+CdHquSKFfUpBuoTksoci8wKIxLkSIJMOH4gHn5xiyYpvDPW80ZRBkicxC+Z MrijAiTwheV50xD5vTA7NekjN+ayc68Ykj+VcA7ROMUmCZzpnn9sXw+JUCHnj8qYjsi3 hAjbHRnWsEi78U3GdYmvJqLP5FcKX4+PsQQvVsvxjncG6W4TucxeM/m01exZRRY5s8LQ pd3w== X-Gm-Message-State: AFqh2kqtUfVSPzgNP7mEC1YVr7ZgBAP1a40FS0bVtByenYZA7xX0zFvO 3ws02Hn9JODn+xrPfHG1PkjReg== X-Google-Smtp-Source: AMrXdXvt3hfDIJwKmRU97dWmM3fPc6GmAA6jUbygzBLsqEWTIi8KOyIulOt/ObfTB7MGsy5rFDyaWw== X-Received: by 2002:a05:6512:3e18:b0:4b5:5ceb:3caa with SMTP id i24-20020a0565123e1800b004b55ceb3caamr90348lfv.19.1671588324854; Tue, 20 Dec 2022 18:05:24 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:24 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 04/20] thermal/drivers/tsens: Drop unnecessary hw_ids Date: Wed, 21 Dec 2022 04:05:04 +0200 Message-Id: <20221221020520.1326964-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The tsens driver defaults to using hw_id equal to the index of the sensor. Thus it is superfluous to declare such hw_id arrays. Drop such arrays from mdm9607 and msm8976 data. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 1 - drivers/thermal/qcom/tsens-v1.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 04d012e4f728..0bc4e5cec184 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -635,7 +635,6 @@ static const struct tsens_ops ops_9607 = { struct tsens_plat_data data_9607 = { .num_sensors = 5, .ops = &ops_9607, - .hw_ids = (unsigned int []){ 0, 1, 2, 3, 4 }, .feat = &tsens_v0_1_feat, .fields = tsens_v0_1_regfields, }; diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 1d7f8a80bd13..96ef12d47bff 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -387,7 +387,6 @@ static const struct tsens_ops ops_8976 = { struct tsens_plat_data data_8976 = { .num_sensors = 11, .ops = &ops_8976, - .hw_ids = (unsigned int[]){0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10}, .feat = &tsens_v1_feat, .fields = tsens_v1_regfields, }; From patchwork Wed Dec 21 02:05:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 636060 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69415C3DA7C for ; Wed, 21 Dec 2022 02:05:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234366AbiLUCFb (ORCPT ); Tue, 20 Dec 2022 21:05:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234339AbiLUCF2 (ORCPT ); Tue, 20 Dec 2022 21:05:28 -0500 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64DC81FCDC for ; Tue, 20 Dec 2022 18:05:27 -0800 (PST) Received: by mail-lf1-x132.google.com with SMTP id cf42so21395117lfb.1 for ; Tue, 20 Dec 2022 18:05:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b1LIXR7d86uJ/gnCpxil12fsOW7FOzRsHJjZeJ/HkoI=; b=HclVv+REr5NwIaoMuw1d8bLAAnbTRhDeUjQ0HE26weyUXPjJVl2hOpUO5nOiichZAX DqB/t/nobzJhVUx36dAqpF6Wa7Jg8e0VYqcOV//56o6+5S5XXKLZMi+vCroW30harIkr Lq3INCadKctkV8UaSWzAyTbO+T4POeXuwUX5f2A9c9TmLEi7uvXIT3sov1ADpFd7HgSe lTHK6ywPzm2o50B4+qwVReuTTwCwY/pSHNQ5rrEBBj/9MD9AhBlcADEboMnaj0KKnM0W FIDLAr8wd+BLXtCBs49o4FFruN0GREMMIKjrWy1VXksDUtkxpUfOioktTDGJA6/MsSHA kotQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b1LIXR7d86uJ/gnCpxil12fsOW7FOzRsHJjZeJ/HkoI=; b=OxkzU6Aeg76BGFZ5rVIdmsbu6OWGD3ryoM3JlVrYnoKvxciSULny5ys1R3Z+/U2weD vPEJey0GfH1QvTKvR/tn3lF/DY+gJ3uO9Yb1RX+avtRV78xFqj+IFJkOIWh2gdbSZzkx pk1wTxUDRSlEOpt2ul3o1F4rm52Yfg+ALelU7FLKzEST+RMaG9XrB+50Aoogs2IgO8GY xTdeOEhMlBZ7HsZU49gU2BkN8U0dGtZMJkO5LZlBVIvkhFi/h9IgCVckoNzXu0k2ItrW n90/vGfhNdzVdxkvXguplaZGWj9ru4ESv8+mkG34sRJSm6s8PibdnMf4Izv1W9rkLMVE 7CGA== X-Gm-Message-State: AFqh2kooA+WpT9L72UdV4T4fmGaFDfsDs/OAaPTapqBg7JFPE79TANOr iFanf0Rgwx3SbocTPds+RcgKZQ== X-Google-Smtp-Source: AMrXdXvHLDrGA5CuxP2uiBuwfcBRcNhtNAs4l/Dkbyb5wqobzQz8lLk3UhliocDMNtevVFZGKP5TnQ== X-Received: by 2002:a19:6b08:0:b0:4b6:edef:183b with SMTP id d8-20020a196b08000000b004b6edef183bmr44599lfa.11.1671588325794; Tue, 20 Dec 2022 18:05:25 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:25 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v4 05/20] thermal/drivers/tsens: Drop msm8976-specific defines Date: Wed, 21 Dec 2022 04:05:05 +0200 Message-Id: <20221221020520.1326964-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop msm8976-specific defines, which duplicate generic ones. Fixes: 0e580290170d ("thermal: qcom: tsens-v1: Add support for MSM8956 and MSM8976") Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v1.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 96ef12d47bff..a7f53966156b 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -78,11 +78,6 @@ #define MSM8976_CAL_SEL_MASK 0x3 -#define MSM8976_CAL_DEGC_PT1 30 -#define MSM8976_CAL_DEGC_PT2 120 -#define MSM8976_SLOPE_FACTOR 1000 -#define MSM8976_SLOPE_DEFAULT 3200 - /* eeprom layout data for qcs404/405 (v1) */ #define BASE0_MASK 0x000007f8 #define BASE1_MASK 0x0007f800 @@ -160,8 +155,8 @@ static void compute_intercept_slope_8976(struct tsens_priv *priv, priv->sensor[10].slope = 3286; for (i = 0; i < priv->num_sensors; i++) { - priv->sensor[i].offset = (p1[i] * MSM8976_SLOPE_FACTOR) - - (MSM8976_CAL_DEGC_PT1 * + priv->sensor[i].offset = (p1[i] * SLOPE_FACTOR) - + (CAL_DEGC_PT1 * priv->sensor[i].slope); } } From patchwork Wed Dec 21 02:05:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 636059 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 89538C3DA6E for ; Wed, 21 Dec 2022 02:05:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234341AbiLUCFe (ORCPT ); Tue, 20 Dec 2022 21:05:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53208 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234287AbiLUCF3 (ORCPT ); Tue, 20 Dec 2022 21:05:29 -0500 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48CA51FCE4 for ; Tue, 20 Dec 2022 18:05:28 -0800 (PST) Received: by mail-lf1-x132.google.com with SMTP id b13so21392017lfo.3 for ; Tue, 20 Dec 2022 18:05:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gtXRNHCMI1NKd22lvW2lXUeMdturnrIWgar6jd83vM8=; b=aQyTyiecUCCC+GVhXRC/CaERtdQjblQQ/hGKbRF1t2KNS6QleCUBYszphZXx/S/8ef MANGexr5t7rUdm9B73TodbDK4miJjDywGxE/ggjoYLRWqjRJhWCZzYsMKG2zCN5i91uy gBNE4guhypMkImg0pzaWJTm5TsBeNNbBJKvS5cFS/zcvLyCnN7qBzaShEnnVW0rRnK3P J0JdMWiKiRMEjS/Iwy3UDBpRQNxXcv4VLEF2aI9eN2+EcW9SPC+Jki+FVjvOVJ7dRePr HTTFWu+KyoOwTdxkxnTVFe+yKjoqhFirzLtB7VRiX8NpZZl95BENI21sYmghYa2g7BLS Ud8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gtXRNHCMI1NKd22lvW2lXUeMdturnrIWgar6jd83vM8=; b=BdMsQXyUmmhNPAQxCEKIt0hfdU7X2BYtPsvH9DlnM0GC8e54JHoxeNnt57p+b1x5yz C1+0+Nach+BuS4qW2gSoA+pUPbc1MJDYrZZ44dl5JN3WgjFFYKOa6z9aGFJCHgdUCjfY 8hLDlwi+zadQO/gmw7d0QwRlHRCJTRv5n0xj3dbBOgM8F23njnOXOypRGhcFxxq8Lm7E 742bUp8OmsiPqY47B4GR2WtAAZvhTIh5egp78lAacqRYysbXg+bDk304yJDOcBOwqTW6 h4kZRngScM8C52+uSlqkaZSMvcdsVWo7UWZN9hi+Rrl99sKvLn3RFL4Ag8zR75tqpPUE JK1g== X-Gm-Message-State: AFqh2kooY2m9SR53Lc/6I78qoigeMHhuAawv5yLmA+DCbxCZ5KZOpvF3 dDx3NYAGSErovMwYR0nb9yROmQ== X-Google-Smtp-Source: AMrXdXusbDfgyfeLs6Nr4JrqT2xW5qmw+//3Nm5Fft8y2hKoohrQ1mFVfLXg15YxYY9gSRo6SGDT6w== X-Received: by 2002:ac2:4468:0:b0:4b5:8502:efb6 with SMTP id y8-20020ac24468000000b004b58502efb6mr58800lfl.40.1671588326578; Tue, 20 Dec 2022 18:05:26 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:26 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v4 06/20] thermal/drivers/tsens: Sort out msm8976 vs msm8956 data Date: Wed, 21 Dec 2022 04:05:06 +0200 Message-Id: <20221221020520.1326964-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Tsens driver mentions that msm8976 data should be used for both msm8976 and msm8956 SoCs. This is not quite correct, as according to the vendor kernels, msm8976 should use standard slope values (3200), while msm8956 really uses the slope values found in the driver. Add separate compatibility string for msm8956, move slope value overrides to the corresponding init function and use the standard compute_intercept_slope() function for both platforms. Fixes: 0e580290170d ("thermal: qcom: tsens-v1: Add support for MSM8956 and MSM8976") Cc: AngeloGioacchino Del Regno Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v1.c | 56 ++++++++++++++++++--------------- drivers/thermal/qcom/tsens.c | 3 ++ drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 34 insertions(+), 27 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index a7f53966156b..83c2853546d0 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -137,30 +137,6 @@ #define CAL_SEL_MASK 7 #define CAL_SEL_SHIFT 0 -static void compute_intercept_slope_8976(struct tsens_priv *priv, - u32 *p1, u32 *p2, u32 mode) -{ - int i; - - priv->sensor[0].slope = 3313; - priv->sensor[1].slope = 3275; - priv->sensor[2].slope = 3320; - priv->sensor[3].slope = 3246; - priv->sensor[4].slope = 3279; - priv->sensor[5].slope = 3257; - priv->sensor[6].slope = 3234; - priv->sensor[7].slope = 3269; - priv->sensor[8].slope = 3255; - priv->sensor[9].slope = 3239; - priv->sensor[10].slope = 3286; - - for (i = 0; i < priv->num_sensors; i++) { - priv->sensor[i].offset = (p1[i] * SLOPE_FACTOR) - - (CAL_DEGC_PT1 * - priv->sensor[i].slope); - } -} - static int calibrate_v1(struct tsens_priv *priv) { u32 base0 = 0, base1 = 0; @@ -286,7 +262,7 @@ static int calibrate_8976(struct tsens_priv *priv) break; } - compute_intercept_slope_8976(priv, p1, p2, mode); + compute_intercept_slope(priv, p1, p2, mode); kfree(qfprom_cdata); return 0; @@ -360,6 +336,22 @@ static const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0), }; +static int __init init_8956(struct tsens_priv *priv) { + priv->sensor[0].slope = 3313; + priv->sensor[1].slope = 3275; + priv->sensor[2].slope = 3320; + priv->sensor[3].slope = 3246; + priv->sensor[4].slope = 3279; + priv->sensor[5].slope = 3257; + priv->sensor[6].slope = 3234; + priv->sensor[7].slope = 3269; + priv->sensor[8].slope = 3255; + priv->sensor[9].slope = 3239; + priv->sensor[10].slope = 3286; + + return init_common(priv); +} + static const struct tsens_ops ops_generic_v1 = { .init = init_common, .calibrate = calibrate_v1, @@ -372,13 +364,25 @@ struct tsens_plat_data data_tsens_v1 = { .fields = tsens_v1_regfields, }; +static const struct tsens_ops ops_8956 = { + .init = init_8956, + .calibrate = calibrate_8976, + .get_temp = get_temp_tsens_valid, +}; + +struct tsens_plat_data data_8956 = { + .num_sensors = 11, + .ops = &ops_8956, + .feat = &tsens_v1_feat, + .fields = tsens_v1_regfields, +}; + static const struct tsens_ops ops_8976 = { .init = init_common, .calibrate = calibrate_8976, .get_temp = get_temp_tsens_valid, }; -/* Valid for both MSM8956 and MSM8976. */ struct tsens_plat_data data_8976 = { .num_sensors = 11, .ops = &ops_8976, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index b5b136ff323f..b191e19df93d 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -983,6 +983,9 @@ static const struct of_device_id tsens_table[] = { }, { .compatible = "qcom,msm8939-tsens", .data = &data_8939, + }, { + .compatible = "qcom,msm8956-tsens", + .data = &data_8956, }, { .compatible = "qcom,msm8960-tsens", .data = &data_8960, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 899af128855f..7dd5fc246894 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -594,7 +594,7 @@ extern struct tsens_plat_data data_8960; extern struct tsens_plat_data data_8916, data_8939, data_8974, data_9607; /* TSENS v1 targets */ -extern struct tsens_plat_data data_tsens_v1, data_8976; +extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956; /* TSENS v2 targets */ extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; From patchwork Wed Dec 21 02:05:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635684 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84431C4332F for ; Wed, 21 Dec 2022 02:05:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234020AbiLUCFc (ORCPT ); Tue, 20 Dec 2022 21:05:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234340AbiLUCF2 (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:26 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 07/20] thermal/drivers/tsens: limit num_sensors to 9 Date: Wed, 21 Dec 2022 04:05:07 +0200 Message-Id: <20221221020520.1326964-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org According to the vendor kernels (msm-3.10, 3.14 and 3.18), msm8939 supports only 9 sensors. Remove the rogue sensor's hw_id. Fixes: 332bc8ebab2c ("thermal: qcom: tsens-v0_1: Add support for MSM8939") Cc: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 0bc4e5cec184..57ac23f9d9b7 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -605,9 +605,9 @@ static const struct tsens_ops ops_8939 = { }; struct tsens_plat_data data_8939 = { - .num_sensors = 10, + .num_sensors = 9, .ops = &ops_8939, - .hw_ids = (unsigned int []){ 0, 1, 2, 3, 5, 6, 7, 8, 9, 10 }, + .hw_ids = (unsigned int []){ 0, 1, 2, 3, 5, 6, 7, 8, 9 }, .feat = &tsens_v0_1_feat, .fields = tsens_v0_1_regfields, From patchwork Wed Dec 21 02:05:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 636058 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A800C4332F for ; Wed, 21 Dec 2022 02:05:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234274AbiLUCFj (ORCPT ); Tue, 20 Dec 2022 21:05:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234295AbiLUCFb (ORCPT ); Tue, 20 Dec 2022 21:05:31 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B04431FCF4 for ; Tue, 20 Dec 2022 18:05:29 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id b3so21417474lfv.2 for ; Tue, 20 Dec 2022 18:05:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x8V/Buc6oo2svqQs4bKfvvLZCMHlCzEmULQ8sDxAW8g=; b=WBrsrnQGNMU70Bch/jsQeIvUfBeODew72Zw+gWa5YHlNg86oslkeBj2FOGFSmvo7Yj Rkb86rD+qWIU1gOSQzE93nihA6kF/RLW3l+rbV9zNPbm58j6/md+3i99fOeVscVLaBNY m+3slxRk8yQKpl5T7OeQ0dFOyQDuB4UsyTpY45amHkNNBeZdNdWtR2yf5r7RnNLrEiCt Wb2RWJ+LgYFYBtQ4TS3LaMfQXMv5WbqwB81Ngi98AmZNGhXZFjSLj9PtKk4BFJ7G/Q3p QDIdeqxF0IMos8HhF1NjGmP2oskcgZWQfVKlYV4qUUl3pD+IpZ1akBwBKZOuNGxgUAd0 Tm9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x8V/Buc6oo2svqQs4bKfvvLZCMHlCzEmULQ8sDxAW8g=; b=TLSbfJZ5+geHj8BLJUjrEnJsCpot146SbNm2HBNvSJnzRu2htGja8GzCyp+wvi1hgp 8cpf1Z45SykLp/pNI6MnFNbB/fdDi2aG37n8ay8HpqbgbTPW6/ePCd0Jcplj3Ypi1fn1 6ewqhh1h3Sz1WCNk0etx97t467y7VJwCBzspLb59vK0AQcvzh21mjZA3r9bR5+lRn37j tWgdESA3LLB6wY+Z77JhxqajYQvT59vQvO/11XRWN3Z4i8Lec//4cqL7tsiEXKp6gRoU bBTXcEIIH5xZZCmI4pBk9Un6mnKEpv25/TsOcwvS/GTl69lCEekAdau8bMmDOnErFLaH q+Xw== X-Gm-Message-State: AFqh2kogmP5HjoW6uqsc7ofe05k77IuKywevSDMTFV4DvOK/8knA/FGz 8rdsFdVJ9uyplYscrC7hxppXew== X-Google-Smtp-Source: AMrXdXvEUY39j5qaHX11vhY3UPeRstTWDj7AelJ2YuHu1KWVWuWHIs+HF9FQyfrSNTFCDAFjowgxlw== X-Received: by 2002:ac2:4c8e:0:b0:4b6:ee97:36d2 with SMTP id d14-20020ac24c8e000000b004b6ee9736d2mr1138468lfl.40.1671588328108; Tue, 20 Dec 2022 18:05:28 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:27 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 08/20] thermal/drivers/tsens: fix slope values for msm8939 Date: Wed, 21 Dec 2022 04:05:08 +0200 Message-Id: <20221221020520.1326964-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org According to the vendor kernels (msm-3.10, 3.14 and 3.18), msm8939 uses non-standard slope values for calibrating the sensors. Fill them accordingly. Fixes: 332bc8ebab2c ("thermal: qcom: tsens-v0_1: Add support for MSM8939") Cc: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 57ac23f9d9b7..be173220a939 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -534,6 +534,20 @@ static int calibrate_9607(struct tsens_priv *priv) return 0; } +static int __init init_8939(struct tsens_priv *priv) { + priv->sensor[0].slope = 2911; + priv->sensor[1].slope = 2789; + priv->sensor[2].slope = 2906; + priv->sensor[3].slope = 2763; + priv->sensor[4].slope = 2922; + priv->sensor[5].slope = 2867; + priv->sensor[6].slope = 2833; + priv->sensor[7].slope = 2838; + priv->sensor[8].slope = 2840; + + return init_common(priv); +} + /* v0.1: 8916, 8939, 8974, 9607 */ static struct tsens_features tsens_v0_1_feat = { @@ -599,7 +613,7 @@ struct tsens_plat_data data_8916 = { }; static const struct tsens_ops ops_8939 = { - .init = init_common, + .init = init_8939, .calibrate = calibrate_8939, .get_temp = get_temp_common, }; From patchwork Wed Dec 21 02:05:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635683 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BD20C4332F for ; Wed, 21 Dec 2022 02:05:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234383AbiLUCFh (ORCPT ); Tue, 20 Dec 2022 21:05:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234172AbiLUCFa (ORCPT ); Tue, 20 Dec 2022 21:05:30 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 789151FCD8 for ; Tue, 20 Dec 2022 18:05:29 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id z26so21349278lfu.8 for ; Tue, 20 Dec 2022 18:05:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2/BQD6ictCOHwYbYSVlKt0RDdfL96pWl64Rc+vqBnZ0=; b=SDhBvHxXCZHOnBZwi3r5ApQ4BrL82hXiiHBnb2v9OVkwCic02ReNona3SU9DDgVlUs XCVVnvSCdTWDIrsOpQ02braBfRUjidrPXreSKrymbIaxN7NiSIQluPj2zVi0bjHdU88Y zls2Xq6IAPS5NFtc0/Q3fI6iXe6Zc4ML5B5X4UaM5XDxCLee79PuZ1dZ8qlQjEBZD6/5 XI/7ZVnY8UxfKR4zAnXThY4fSuq8sS49HYxdblOABJ2D2ivEInLjfe2awKoOsozbIfIw XZ9L+G2tuIRLojb2znPW5A3ppgT5DH+uYKPm4nBfFf1vfrUZwiyQFx34Hg+NCOiT8znu 10RQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2/BQD6ictCOHwYbYSVlKt0RDdfL96pWl64Rc+vqBnZ0=; b=zEj9vX29Bt6GxTg+d3NvuQcPHLpZO48rGpGxeepxG3iRiQJHPrFFWhI3uNj30CaImz mfRnNleDjpDUQr6FD0anNCbTB1xNX0BncvQSN75d+Re+/d4KDSBkmKkOWVkGgM/nXW2j 3xQrSZacLrWuxgboL4H/M0TG5A5H20enCRf9GxO6HujbtiddEVItnRQr+fHEy2BTMyhW 28BXmLpYr/Ws4Ue3PxPhQH1sujiNjfj4oFitdDmTSn7Pe7NMg9RTfmZx4IBJi2x0JTDy WYP/eL212MyrurLmWWM63d7Y4/0Lig2+iTUAsWy1tGJEML8RNS+A+bUXdXpoIWDXT2wl GdJw== X-Gm-Message-State: AFqh2kp+mZpTvto/4qZ4bhXgcDKZeAr3kZVbgEoeOlX1++FqurRmyMAA ph7xPysTaS8N6sZUgmw31NyA8A== X-Google-Smtp-Source: AMrXdXuWq4+asHwqXIEf9RR1V6cAU+mXYZ2Rue0kNdN7pH9Hxp7AZFEpjORh2tgXNqmWDIQ0QGfI4Q== X-Received: by 2002:a19:5005:0:b0:4a4:68b8:c2dd with SMTP id e5-20020a195005000000b004a468b8c2ddmr1303434lfb.52.1671588329037; Tue, 20 Dec 2022 18:05:29 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:28 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 09/20] thermal/drivers/tsens: Support using nvmem cells for calibration data Date: Wed, 21 Dec 2022 04:05:09 +0200 Message-Id: <20221221020520.1326964-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a unified function using nvmem cells for parsing the calibration data rather than parsing the calibration blob manually. Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 15 ++++++ drivers/thermal/qcom/tsens-v1.c | 11 ++++- drivers/thermal/qcom/tsens.c | 76 +++++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.h | 5 ++ 4 files changed, 106 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index be173220a939..a6c2b2b76264 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -229,6 +229,11 @@ static int calibrate_8916(struct tsens_priv *priv) u32 p1[5], p2[5]; int mode = 0; u32 *qfprom_cdata, *qfprom_csel; + int ret; + + ret = tsens_calibrate_nvmem(priv, 3); + if (!ret) + return 0; qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); if (IS_ERR(qfprom_cdata)) @@ -286,6 +291,11 @@ static int calibrate_8939(struct tsens_priv *priv) int mode = 0; u32 *qfprom_cdata; u32 cdata[6]; + int ret; + + ret = tsens_calibrate_common(priv); + if (!ret) + return 0; qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); if (IS_ERR(qfprom_cdata)) @@ -491,6 +501,11 @@ static int calibrate_9607(struct tsens_priv *priv) u32 p1[5], p2[5]; int mode = 0; u32 *qfprom_cdata; + int ret; + + ret = tsens_calibrate_common(priv); + if (!ret) + return 0; qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); if (IS_ERR(qfprom_cdata)) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 83c2853546d0..5bba75a845c5 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -143,7 +143,11 @@ static int calibrate_v1(struct tsens_priv *priv) u32 p1[10], p2[10]; u32 mode = 0, lsb = 0, msb = 0; u32 *qfprom_cdata; - int i; + int i, ret; + + ret = tsens_calibrate_common(priv); + if (!ret) + return 0; qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); if (IS_ERR(qfprom_cdata)) @@ -209,6 +213,11 @@ static int calibrate_8976(struct tsens_priv *priv) u32 p1[11], p2[11]; int mode = 0, tmp = 0; u32 *qfprom_cdata; + int ret; + + ret = tsens_calibrate_common(priv); + if (!ret) + return 0; qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); if (IS_ERR(qfprom_cdata)) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index b191e19df93d..68aef0ed6182 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -70,6 +70,82 @@ char *qfprom_read(struct device *dev, const char *cname) return ret; } +int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift) +{ + u32 mode; + u32 base1, base2; + u32 p1[MAX_SENSORS], p2[MAX_SENSORS]; + char name[] = "sXX_pY"; /* s10_p1 */ + int i, ret; + + if (priv->num_sensors > MAX_SENSORS) + return -EINVAL; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "mode", &mode); + if (ret == -ENOENT) + dev_warn(priv->dev, "Please migrate to separate nvmem cells for calibration data\n"); + if (ret < 0) + return ret; + + dev_dbg(priv->dev, "calibration mode is %d\n", mode); + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "base1", &base1); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "base2", &base2); + if (ret < 0) + return ret; + + for (i = 0; i < priv->num_sensors; i++) { + ret = snprintf(name, sizeof(name), "s%d_p1", i); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &p1[i]); + if (ret) + return ret; + + ret = snprintf(name, sizeof(name), "s%d_p2", i); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &p2[i]); + if (ret) + return ret; + } + + switch (mode) { + case ONE_PT_CALIB: + for (i = 0; i < priv->num_sensors; i++) + p1[i] = p1[i] + (base1 << shift); + break; + case TWO_PT_CALIB: + for (i = 0; i < priv->num_sensors; i++) + p2[i] = (p2[i] + base2) << shift; + fallthrough; + case ONE_PT_CALIB2: + for (i = 0; i < priv->num_sensors; i++) + p1[i] = (p1[i] + base1) << shift; + break; + default: + dev_dbg(priv->dev, "calibrationless mode\n"); + for (i = 0; i < priv->num_sensors; i++) { + p1[i] = 500; + p2[i] = 780; + } + } + + compute_intercept_slope(priv, p1, p2, mode); + + return 0; +} + +int tsens_calibrate_common(struct tsens_priv *priv) +{ + return tsens_calibrate_nvmem(priv, 2); +} + /* * Use this function on devices where slope and offset calculations * depend on calibration data read from qfprom. On others the slope diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 7dd5fc246894..645ae02438fa 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -6,6 +6,7 @@ #ifndef __QCOM_TSENS_H__ #define __QCOM_TSENS_H__ +#define NO_PT_CALIB 0x0 #define ONE_PT_CALIB 0x1 #define ONE_PT_CALIB2 0x2 #define TWO_PT_CALIB 0x3 @@ -17,6 +18,8 @@ #define THRESHOLD_MAX_ADC_CODE 0x3ff #define THRESHOLD_MIN_ADC_CODE 0x0 +#define MAX_SENSORS 16 + #include #include #include @@ -582,6 +585,8 @@ struct tsens_priv { }; char *qfprom_read(struct device *dev, const char *cname); +int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift); +int tsens_calibrate_common(struct tsens_priv *priv); void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode); int init_common(struct tsens_priv *priv); int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp); From patchwork Wed Dec 21 02:05:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635682 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96CF6C4167B for ; Wed, 21 Dec 2022 02:05:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234335AbiLUCFl (ORCPT ); Tue, 20 Dec 2022 21:05:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53330 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234372AbiLUCFc (ORCPT ); Tue, 20 Dec 2022 21:05:32 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6FBE01FCE1 for ; Tue, 20 Dec 2022 18:05:30 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id y25so21337086lfa.9 for ; Tue, 20 Dec 2022 18:05:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1Z/T/h1X9J//bIOmS0oUJh7T3j6BIBrKh1OEuGetHB8=; b=XvLc5SXYOW4p60XB55nOihQ2Q9Q4zkrmyoqN2oK77QbnRp16V8yoFAnr9sD51JC2C+ pX0qoDNWQBTDGX4KNEgse+FHrCTEh7JbuNSnzgnfVpLd1SwZgvPwg7PHagn0HD6RKiSf hgBaNqwvnREmPYz2t8PwiIiviLfUkjpKjWIOPwAo4H3xoON2u4r6PmWKvnx2gGrICXER NzJRKqd1PwtRvNIxLDJ+Swb1FC9SpeCGMQTqJ9LRX+LHQG+osDEh3mOIY03Z/83X27KM k8c/lIzHBYyM3KcRMp7AnsUjeGKIHLTCo7ORRJYhc9CSBlxhiqTqtccSZKJtIE31/7O9 pC0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1Z/T/h1X9J//bIOmS0oUJh7T3j6BIBrKh1OEuGetHB8=; b=QPrcwvNxQCCg2wNzxMppOpSn663WZ1is4yivGXnoP95D14dDJ/R13BzGDAVS7zh4Yx xZ8bTK5w8bTHRm6JAVDac8PgQCA/bhSGB/AGQMEuBnUAaVfQavRRi4KFjZ+YgQ0CcatQ RzERN4wtuiTXTbtfP1VXsBSWeaq5me56jWhyRMcPWdpGmDnX/J09b7yXHUX0pw9D7zuD gsu+K5OmYfMfTpgUrRjMsc0lDwyPxqz/Tm56+2tAoyqrFMMrZqen9yJOphxctiLT+Kp2 GX0Iqghziv1au5v/fXsxX0YsZEV/oDpISvRwZBGE887IPPeqo3jjwRPk/m7tJ2ozSSYD YXDw== X-Gm-Message-State: AFqh2kqXuQ5CONE1+zcp+k6dzuHplW0ZlueWgDHRDRgeDmpJbfHh+aQR /ZIsZVdXIHymf6lGsGQIEKSPRA== X-Google-Smtp-Source: AMrXdXuRMviGs1p935z4r1ByadYZGxUif1+QK9/LqBRocDr3Md7KblpwL3IVAHYyMQWZti22AqPreA== X-Received: by 2002:a05:6512:400d:b0:4b5:1b4a:efb7 with SMTP id br13-20020a056512400d00b004b51b4aefb7mr94291lfb.61.1671588329985; Tue, 20 Dec 2022 18:05:29 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:29 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 10/20] thermal/drivers/tsens: Support using nvmem cells for msm8974 calibration Date: Wed, 21 Dec 2022 04:05:10 +0200 Message-Id: <20221221020520.1326964-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org MSM8974 has two sets of calibration data: main one and backup. Add support for parsing both sets of calibration data from nvmem cells. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 50 +++++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 39 +++++++++++++++++++----- drivers/thermal/qcom/tsens.h | 1 + 3 files changed, 82 insertions(+), 8 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index a6c2b2b76264..41b061c0bdd1 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -3,6 +3,7 @@ * Copyright (c) 2015, The Linux Foundation. All rights reserved. */ +#include #include #include "tsens.h" @@ -359,6 +360,50 @@ static int calibrate_8939(struct tsens_priv *priv) return 0; } +static int calibrate_8974_nvmem(struct tsens_priv *priv) +{ + int i, ret, mode; + u32 p1[11], p2[11]; + u32 backup; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "use_backup", &backup); + if (ret == -ENOENT) + dev_warn(priv->dev, "Please migrate to separate nvmem cells for calibration data\n"); + if (ret < 0) + return ret; + + mode = tsens_read_calibration(priv, 2, p1, p2, backup == BKP_SEL); + if (mode < 0) + return mode; + + if (mode == NO_PT_CALIB) { + p1[0] += 2; + p1[1] += 9; + p1[2] += 3; + p1[3] += 9; + p1[4] += 5; + p1[5] += 9; + p1[6] += 7; + p1[7] += 10; + p1[8] += 8; + p1[9] += 9; + p1[10] += 8; + } else { + for (i = 0; i < priv->num_sensors; i++) { + /* + * ONE_PT_CALIB requires using addition here instead of + * using OR operation. + */ + p1[i] += BIT_APPEND; + p2[i] += BIT_APPEND; + } + } + + compute_intercept_slope(priv, p1, p2, mode); + + return 0; +} + static int calibrate_8974(struct tsens_priv *priv) { int base1 = 0, base2 = 0, i; @@ -366,6 +411,11 @@ static int calibrate_8974(struct tsens_priv *priv) int mode = 0; u32 *calib, *bkp; u32 calib_redun_sel; + int ret; + + ret = calibrate_8974_nvmem(priv); + if (ret == 0) + return 0; calib = (u32 *)qfprom_read(priv->dev, "calib"); if (IS_ERR(calib)) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 68aef0ed6182..83bf60fa9008 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -70,18 +70,21 @@ char *qfprom_read(struct device *dev, const char *cname) return ret; } -int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift) +int tsens_read_calibration(struct tsens_priv *priv, int shift, u32 *p1, u32 *p2, bool backup) { u32 mode; u32 base1, base2; - u32 p1[MAX_SENSORS], p2[MAX_SENSORS]; - char name[] = "sXX_pY"; /* s10_p1 */ + char name[] = "sXX_pY_backup"; /* s10_p1_backup */ int i, ret; if (priv->num_sensors > MAX_SENSORS) return -EINVAL; - ret = nvmem_cell_read_variable_le_u32(priv->dev, "mode", &mode); + ret = snprintf(name, sizeof(name), "mode%s", backup ? "_backup" : ""); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &mode); if (ret == -ENOENT) dev_warn(priv->dev, "Please migrate to separate nvmem cells for calibration data\n"); if (ret < 0) @@ -89,16 +92,24 @@ int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift) dev_dbg(priv->dev, "calibration mode is %d\n", mode); - ret = nvmem_cell_read_variable_le_u32(priv->dev, "base1", &base1); + ret = snprintf(name, sizeof(name), "base1%s", backup ? "_backup" : ""); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &base1); + if (ret < 0) + return ret; + + ret = snprintf(name, sizeof(name), "base2%s", backup ? "_backup" : ""); if (ret < 0) return ret; - ret = nvmem_cell_read_variable_le_u32(priv->dev, "base2", &base2); + ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &base2); if (ret < 0) return ret; for (i = 0; i < priv->num_sensors; i++) { - ret = snprintf(name, sizeof(name), "s%d_p1", i); + ret = snprintf(name, sizeof(name), "s%d_p1%s", i, backup ? "_backup" : ""); if (ret < 0) return ret; @@ -106,7 +117,7 @@ int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift) if (ret) return ret; - ret = snprintf(name, sizeof(name), "s%d_p2", i); + ret = snprintf(name, sizeof(name), "s%d_p2%s", i, backup ? "_backup" : ""); if (ret < 0) return ret; @@ -136,6 +147,18 @@ int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift) } } + return mode; +} + +int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift) +{ + u32 p1[MAX_SENSORS], p2[MAX_SENSORS]; + int mode; + + mode = tsens_read_calibration(priv, shift, p1, p2, false); + if (mode < 0) + return mode; + compute_intercept_slope(priv, p1, p2, mode); return 0; diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 645ae02438fa..a9ae8df9f810 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -585,6 +585,7 @@ struct tsens_priv { }; char *qfprom_read(struct device *dev, const char *cname); +int tsens_read_calibration(struct tsens_priv *priv, int shift, u32 *p1, u32 *p2, bool backup); int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift); int tsens_calibrate_common(struct tsens_priv *priv); void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode); From patchwork Wed Dec 21 02:05:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635681 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 128B9C3DA6E for ; Wed, 21 Dec 2022 02:05:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233921AbiLUCFq (ORCPT ); Tue, 20 Dec 2022 21:05:46 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234292AbiLUCFg (ORCPT ); Tue, 20 Dec 2022 21:05:36 -0500 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1AEC1FCFE for ; Tue, 20 Dec 2022 18:05:31 -0800 (PST) Received: by mail-lf1-x133.google.com with SMTP id f34so6161573lfv.10 for ; Tue, 20 Dec 2022 18:05:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vyXTopi5EUP3pGLq3uGSSKnmhYF//O6TOVVELemZdsw=; b=BOqhGpbNrWyeXfH5eguynT7lI3OIaZux3VF9noHQMZFN/fibSjXOXGXEke7drJ03HJ oExtE+TDoxOR3zb3IgjYAU2AX4chgJMxPB1MRsyYH/SvfQtRBPB8Ih637W9n5RsDFGE1 Ip+luo9cReMyJpfjwxyj4yYMFxv/sR9zOtVrEp+z/Kq2eEtdXn81rhmhAS9RThCYx0+A EQ/lbvVeiKutdHHz1aZ+GW3Zegv1wboJ+60H1ZOcEFhu5cyuP8qbvhC33rsZPmxi3PBw FZl8UeLp+YCzdjzmxJd4zEjhH2a5g+gRvl0HMwrYPkp+uLlD0dGA3IYfjE1R0/RfwxEf 4xiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vyXTopi5EUP3pGLq3uGSSKnmhYF//O6TOVVELemZdsw=; b=seMg6pc2NAOp4gg2wSgNb4hSHckyFu04laFKQIC+yfUNlbNt4mBn9YD3DjsM6rTrar tsayXmN0mnum7n0MrTL6lltH1u4vMKgRu1GHgFuLU7Hx6pJqk3GFEb8XF8vKQTpX6YTb lcsdb/Wwh2aGR38FNQ/EYFaIPrguc59CLHAnEQQmOAjBTxPtm+aKh1iDf8heZRrKuggi HffFbmOkmqVvd/Uv5tvf9QjdJ2Yatli70nNPBqRvqLoFgWnP4OWvW9IpI/SKiA3fn26G Ft8+wwo8HaH1xNJn/vn6vjR2WGoYKREVv7Et53V9WLbD7NzoUC4JzyntKRWeYdoPgJfy +ISQ== X-Gm-Message-State: AFqh2krTaBBio1blqCW9Z1O9WEAfHPiZpAkvZeT5mmU7BElMx+PkcNBO OYrO11ZMWXUJMMnaCDQT7bihdg== X-Google-Smtp-Source: AMrXdXu0VxLzWycMSu6a4fQHsUZtqIC0qPH5JxFvqrcStUKfTr1PzyRJ3DYvzwMDVC/xL1C8vm7SHA== X-Received: by 2002:ac2:46e8:0:b0:4bc:bdf5:f161 with SMTP id q8-20020ac246e8000000b004bcbdf5f161mr1269475lfo.49.1671588330787; Tue, 20 Dec 2022 18:05:30 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:30 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 11/20] thermal/drivers/tsens: Rework legacy calibration data parsers Date: Wed, 21 Dec 2022 04:05:11 +0200 Message-Id: <20221221020520.1326964-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rework existing calibration parsing code to use simple data structure describing data layout. This allows us to drop all the mask & shift values, replacing them with data tables. The code for msm8974 is not reworked, as it has separate calibration and backup data. Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 595 +++++++----------------------- drivers/thermal/qcom/tsens-v1.c | 266 +++---------- drivers/thermal/qcom/tsens.c | 64 ++++ drivers/thermal/qcom/tsens.h | 38 ++ 4 files changed, 296 insertions(+), 667 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 41b061c0bdd1..6b8f7cb7ab9d 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -16,221 +16,113 @@ #define TM_Sn_STATUS_OFF 0x0030 #define TM_TRDY_OFF 0x005c -/* eeprom layout data for 8916 */ -#define MSM8916_BASE0_MASK 0x0000007f -#define MSM8916_BASE1_MASK 0xfe000000 -#define MSM8916_BASE0_SHIFT 0 -#define MSM8916_BASE1_SHIFT 25 - -#define MSM8916_S0_P1_MASK 0x00000f80 -#define MSM8916_S1_P1_MASK 0x003e0000 -#define MSM8916_S2_P1_MASK 0xf8000000 -#define MSM8916_S3_P1_MASK 0x000003e0 -#define MSM8916_S4_P1_MASK 0x000f8000 - -#define MSM8916_S0_P2_MASK 0x0001f000 -#define MSM8916_S1_P2_MASK 0x07c00000 -#define MSM8916_S2_P2_MASK 0x0000001f -#define MSM8916_S3_P2_MASK 0x00007c00 -#define MSM8916_S4_P2_MASK 0x01f00000 - -#define MSM8916_S0_P1_SHIFT 7 -#define MSM8916_S1_P1_SHIFT 17 -#define MSM8916_S2_P1_SHIFT 27 -#define MSM8916_S3_P1_SHIFT 5 -#define MSM8916_S4_P1_SHIFT 15 - -#define MSM8916_S0_P2_SHIFT 12 -#define MSM8916_S1_P2_SHIFT 22 -#define MSM8916_S2_P2_SHIFT 0 -#define MSM8916_S3_P2_SHIFT 10 -#define MSM8916_S4_P2_SHIFT 20 - -#define MSM8916_CAL_SEL_MASK 0xe0000000 -#define MSM8916_CAL_SEL_SHIFT 29 - -/* eeprom layout data for 8939 */ -#define MSM8939_BASE0_MASK 0x000000ff -#define MSM8939_BASE1_MASK 0xff000000 -#define MSM8939_BASE0_SHIFT 0 -#define MSM8939_BASE1_SHIFT 24 - -#define MSM8939_S0_P1_MASK 0x000001f8 -#define MSM8939_S1_P1_MASK 0x001f8000 -#define MSM8939_S2_P1_MASK_0_4 0xf8000000 -#define MSM8939_S2_P1_MASK_5 0x00000001 -#define MSM8939_S3_P1_MASK 0x00001f80 -#define MSM8939_S4_P1_MASK 0x01f80000 -#define MSM8939_S5_P1_MASK 0x00003f00 -#define MSM8939_S6_P1_MASK 0x03f00000 -#define MSM8939_S7_P1_MASK 0x0000003f -#define MSM8939_S8_P1_MASK 0x0003f000 -#define MSM8939_S9_P1_MASK 0x07e00000 - -#define MSM8939_S0_P2_MASK 0x00007e00 -#define MSM8939_S1_P2_MASK 0x07e00000 -#define MSM8939_S2_P2_MASK 0x0000007e -#define MSM8939_S3_P2_MASK 0x0007e000 -#define MSM8939_S4_P2_MASK 0x7e000000 -#define MSM8939_S5_P2_MASK 0x000fc000 -#define MSM8939_S6_P2_MASK 0xfc000000 -#define MSM8939_S7_P2_MASK 0x00000fc0 -#define MSM8939_S8_P2_MASK 0x00fc0000 -#define MSM8939_S9_P2_MASK_0_4 0xf8000000 -#define MSM8939_S9_P2_MASK_5 0x00002000 - -#define MSM8939_S0_P1_SHIFT 3 -#define MSM8939_S1_P1_SHIFT 15 -#define MSM8939_S2_P1_SHIFT_0_4 27 -#define MSM8939_S2_P1_SHIFT_5 0 -#define MSM8939_S3_P1_SHIFT 7 -#define MSM8939_S4_P1_SHIFT 19 -#define MSM8939_S5_P1_SHIFT 8 -#define MSM8939_S6_P1_SHIFT 20 -#define MSM8939_S7_P1_SHIFT 0 -#define MSM8939_S8_P1_SHIFT 12 -#define MSM8939_S9_P1_SHIFT 21 - -#define MSM8939_S0_P2_SHIFT 9 -#define MSM8939_S1_P2_SHIFT 21 -#define MSM8939_S2_P2_SHIFT 1 -#define MSM8939_S3_P2_SHIFT 13 -#define MSM8939_S4_P2_SHIFT 25 -#define MSM8939_S5_P2_SHIFT 14 -#define MSM8939_S6_P2_SHIFT 26 -#define MSM8939_S7_P2_SHIFT 6 -#define MSM8939_S8_P2_SHIFT 18 -#define MSM8939_S9_P2_SHIFT_0_4 27 -#define MSM8939_S9_P2_SHIFT_5 13 - -#define MSM8939_CAL_SEL_MASK 0x7 -#define MSM8939_CAL_SEL_SHIFT 0 - -/* eeprom layout data for 8974 */ -#define BASE1_MASK 0xff -#define S0_P1_MASK 0x3f00 -#define S1_P1_MASK 0xfc000 -#define S2_P1_MASK 0x3f00000 -#define S3_P1_MASK 0xfc000000 -#define S4_P1_MASK 0x3f -#define S5_P1_MASK 0xfc0 -#define S6_P1_MASK 0x3f000 -#define S7_P1_MASK 0xfc0000 -#define S8_P1_MASK 0x3f000000 -#define S8_P1_MASK_BKP 0x3f -#define S9_P1_MASK 0x3f -#define S9_P1_MASK_BKP 0xfc0 -#define S10_P1_MASK 0xfc0 -#define S10_P1_MASK_BKP 0x3f000 -#define CAL_SEL_0_1 0xc0000000 -#define CAL_SEL_2 0x40000000 -#define CAL_SEL_SHIFT 30 -#define CAL_SEL_SHIFT_2 28 - -#define S0_P1_SHIFT 8 -#define S1_P1_SHIFT 14 -#define S2_P1_SHIFT 20 -#define S3_P1_SHIFT 26 -#define S5_P1_SHIFT 6 -#define S6_P1_SHIFT 12 -#define S7_P1_SHIFT 18 -#define S8_P1_SHIFT 24 -#define S9_P1_BKP_SHIFT 6 -#define S10_P1_SHIFT 6 -#define S10_P1_BKP_SHIFT 12 - -#define BASE2_SHIFT 12 -#define BASE2_BKP_SHIFT 18 -#define S0_P2_SHIFT 20 -#define S0_P2_BKP_SHIFT 26 -#define S1_P2_SHIFT 26 -#define S2_P2_BKP_SHIFT 6 -#define S3_P2_SHIFT 6 -#define S3_P2_BKP_SHIFT 12 -#define S4_P2_SHIFT 12 -#define S4_P2_BKP_SHIFT 18 -#define S5_P2_SHIFT 18 -#define S5_P2_BKP_SHIFT 24 -#define S6_P2_SHIFT 24 -#define S7_P2_BKP_SHIFT 6 -#define S8_P2_SHIFT 6 -#define S8_P2_BKP_SHIFT 12 -#define S9_P2_SHIFT 12 -#define S9_P2_BKP_SHIFT 18 -#define S10_P2_SHIFT 18 -#define S10_P2_BKP_SHIFT 24 - -#define BASE2_MASK 0xff000 -#define BASE2_BKP_MASK 0xfc0000 -#define S0_P2_MASK 0x3f00000 -#define S0_P2_BKP_MASK 0xfc000000 -#define S1_P2_MASK 0xfc000000 -#define S1_P2_BKP_MASK 0x3f -#define S2_P2_MASK 0x3f -#define S2_P2_BKP_MASK 0xfc0 -#define S3_P2_MASK 0xfc0 -#define S3_P2_BKP_MASK 0x3f000 -#define S4_P2_MASK 0x3f000 -#define S4_P2_BKP_MASK 0xfc0000 -#define S5_P2_MASK 0xfc0000 -#define S5_P2_BKP_MASK 0x3f000000 -#define S6_P2_MASK 0x3f000000 -#define S6_P2_BKP_MASK 0x3f -#define S7_P2_MASK 0x3f -#define S7_P2_BKP_MASK 0xfc0 -#define S8_P2_MASK 0xfc0 -#define S8_P2_BKP_MASK 0x3f000 -#define S9_P2_MASK 0x3f000 -#define S9_P2_BKP_MASK 0xfc0000 -#define S10_P2_MASK 0xfc0000 -#define S10_P2_BKP_MASK 0x3f000000 - +/* extra data for 8974 */ #define BKP_SEL 0x3 #define BKP_REDUN_SEL 0xe0000000 -#define BKP_REDUN_SHIFT 29 #define BIT_APPEND 0x3 -/* eeprom layout data for mdm9607 */ -#define MDM9607_BASE0_MASK 0x000000ff -#define MDM9607_BASE1_MASK 0x000ff000 -#define MDM9607_BASE0_SHIFT 0 -#define MDM9607_BASE1_SHIFT 12 - -#define MDM9607_S0_P1_MASK 0x00003f00 -#define MDM9607_S1_P1_MASK 0x03f00000 -#define MDM9607_S2_P1_MASK 0x0000003f -#define MDM9607_S3_P1_MASK 0x0003f000 -#define MDM9607_S4_P1_MASK 0x0000003f - -#define MDM9607_S0_P2_MASK 0x000fc000 -#define MDM9607_S1_P2_MASK 0xfc000000 -#define MDM9607_S2_P2_MASK 0x00000fc0 -#define MDM9607_S3_P2_MASK 0x00fc0000 -#define MDM9607_S4_P2_MASK 0x00000fc0 - -#define MDM9607_S0_P1_SHIFT 8 -#define MDM9607_S1_P1_SHIFT 20 -#define MDM9607_S2_P1_SHIFT 0 -#define MDM9607_S3_P1_SHIFT 12 -#define MDM9607_S4_P1_SHIFT 0 - -#define MDM9607_S0_P2_SHIFT 14 -#define MDM9607_S1_P2_SHIFT 26 -#define MDM9607_S2_P2_SHIFT 6 -#define MDM9607_S3_P2_SHIFT 18 -#define MDM9607_S4_P2_SHIFT 6 - -#define MDM9607_CAL_SEL_MASK 0x00700000 -#define MDM9607_CAL_SEL_SHIFT 20 +struct tsens_legacy_calibration_format tsens_8916_nvmem = { + .base_len = 7, + .base_shift = 3, + .sp_len = 5, + .mode = { 0, 29, 1 }, + .invalid = { 0, 31, 1 }, + .base = { { 0, 0 }, { 1, 25 } }, + .sp = { + { { 0, 7 }, { 0, 12 } }, + { { 0, 17 }, { 0, 22 } }, + { { 0, 27 }, { 1, 0 } }, + { { 1, 5 }, { 1, 10 } }, + { { 1, 15 }, { 1, 20 } }, + }, +}; + +struct tsens_legacy_calibration_format tsens_8939_nvmem = { + .base_len = 8, + .base_shift = 2, + .sp_len = 6, + .mode = { 12, 0 }, + .invalid = { 12, 2 }, + .base = { { 0, 0 }, { 1, 24 } }, + .sp = { + { { 12, 3 }, { 12, 9 } }, + { { 12, 15 }, { 12, 21 } }, + { { 12, 27 }, { 13, 1 } }, + { { 13, 7 }, { 13, 13 } }, + { { 13, 19 }, { 13, 25 } }, + { { 0, 8 }, { 0, 14 } }, + { { 0, 20 }, { 0, 26 } }, + { { 1, 0 }, { 1, 6 } }, + { { 1, 12 }, { 1, 18 } }, + }, +}; + +struct tsens_legacy_calibration_format tsens_8974_nvmem = { + .base_len = 8, + .base_shift = 2, + .sp_len = 6, + .mode = { 1, 30 }, + .invalid = { 3, 30 }, + .base = { { 0, 0 }, { 2, 12 } }, + .sp = { + { { 0, 8 }, { 2, 20 } }, + { { 0, 14 }, { 2, 26 } }, + { { 0, 20 }, { 3, 0 } }, + { { 0, 26 }, { 3, 6 } }, + { { 1, 0 }, { 3, 12 } }, + { { 1, 6 }, { 3, 18 } }, + { { 1, 12 }, { 3, 24 } }, + { { 1, 18 }, { 4, 0 } }, + { { 1, 24 }, { 4, 6 } }, + { { 2, 0 }, { 4, 12 } }, + { { 2, 6 }, { 4, 18 } }, + }, +}; + +struct tsens_legacy_calibration_format tsens_8974_backup_nvmem = { + .base_len = 8, + .base_shift = 2, + .sp_len = 6, + .mode = { 4, 30, 1 }, + .invalid = { 5, 30, 1 }, + .base = { { 0, 0 }, { 2, 18 } }, + .sp = { + { { 0, 8 }, { 2, 26 } }, + { { 0, 14 }, { 3, 0 } }, + { { 0, 20 }, { 3, 6 } }, + { { 0, 26 }, { 3, 12 } }, + { { 1, 0 }, { 3, 18 } }, + { { 1, 6 }, { 3, 24, 1 } }, + { { 1, 12 }, { 4, 0, 1 } }, + { { 1, 18 }, { 4, 6, 1 } }, + { { 2, 0 }, { 4, 12, 1 } }, + { { 2, 6 }, { 4, 18, 1 } }, + { { 2, 12 }, { 4, 24, 1 } }, + }, +}; + +struct tsens_legacy_calibration_format tsens_9607_nvmem = { + .base_len = 8, + .base_shift = 2, + .sp_len = 6, + .mode = { 2, 20 }, + .invalid = { 2, 22 }, + .base = { { 0, 0 }, { 2, 12 } }, + .sp = { + { { 0, 8 }, { 0, 14 } }, + { { 0, 20 }, { 0, 26 } }, + { { 1, 0 }, { 1, 6 } }, + { { 1, 12 }, { 1, 18 } }, + { { 2, 0 }, { 2, 6 } }, + }, +}; static int calibrate_8916(struct tsens_priv *priv) { - int base0 = 0, base1 = 0, i; u32 p1[5], p2[5]; - int mode = 0; u32 *qfprom_cdata, *qfprom_csel; - int ret; + int mode, ret; ret = tsens_calibrate_nvmem(priv, 3); if (!ret) @@ -246,37 +138,9 @@ static int calibrate_8916(struct tsens_priv *priv) return PTR_ERR(qfprom_csel); } - mode = (qfprom_csel[0] & MSM8916_CAL_SEL_MASK) >> MSM8916_CAL_SEL_SHIFT; - dev_dbg(priv->dev, "calibration mode is %d\n", mode); - - switch (mode) { - case TWO_PT_CALIB: - base1 = (qfprom_cdata[1] & MSM8916_BASE1_MASK) >> MSM8916_BASE1_SHIFT; - p2[0] = (qfprom_cdata[0] & MSM8916_S0_P2_MASK) >> MSM8916_S0_P2_SHIFT; - p2[1] = (qfprom_cdata[0] & MSM8916_S1_P2_MASK) >> MSM8916_S1_P2_SHIFT; - p2[2] = (qfprom_cdata[1] & MSM8916_S2_P2_MASK) >> MSM8916_S2_P2_SHIFT; - p2[3] = (qfprom_cdata[1] & MSM8916_S3_P2_MASK) >> MSM8916_S3_P2_SHIFT; - p2[4] = (qfprom_cdata[1] & MSM8916_S4_P2_MASK) >> MSM8916_S4_P2_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p2[i] = ((base1 + p2[i]) << 3); - fallthrough; - case ONE_PT_CALIB2: - base0 = (qfprom_cdata[0] & MSM8916_BASE0_MASK); - p1[0] = (qfprom_cdata[0] & MSM8916_S0_P1_MASK) >> MSM8916_S0_P1_SHIFT; - p1[1] = (qfprom_cdata[0] & MSM8916_S1_P1_MASK) >> MSM8916_S1_P1_SHIFT; - p1[2] = (qfprom_cdata[0] & MSM8916_S2_P1_MASK) >> MSM8916_S2_P1_SHIFT; - p1[3] = (qfprom_cdata[1] & MSM8916_S3_P1_MASK) >> MSM8916_S3_P1_SHIFT; - p1[4] = (qfprom_cdata[1] & MSM8916_S4_P1_MASK) >> MSM8916_S4_P1_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p1[i] = (((base0) + p1[i]) << 3); - break; - default: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] = 500; - p2[i] = 780; - } - break; - } + mode = tsens_read_calibration_legacy(priv, &tsens_8916_nvmem, + p1, p2, + qfprom_cdata, qfprom_csel); compute_intercept_slope(priv, p1, p2, mode); kfree(qfprom_cdata); @@ -287,12 +151,9 @@ static int calibrate_8916(struct tsens_priv *priv) static int calibrate_8939(struct tsens_priv *priv) { - int base0 = 0, base1 = 0, i; u32 p1[10], p2[10]; - int mode = 0; u32 *qfprom_cdata; - u32 cdata[6]; - int ret; + int mode, ret; ret = tsens_calibrate_common(priv); if (!ret) @@ -302,57 +163,9 @@ static int calibrate_8939(struct tsens_priv *priv) if (IS_ERR(qfprom_cdata)) return PTR_ERR(qfprom_cdata); - /* Mapping between qfprom nvmem and calibration data */ - cdata[0] = qfprom_cdata[12]; - cdata[1] = qfprom_cdata[13]; - cdata[2] = qfprom_cdata[0]; - cdata[3] = qfprom_cdata[1]; - cdata[4] = qfprom_cdata[22]; - cdata[5] = qfprom_cdata[21]; - - mode = (cdata[0] & MSM8939_CAL_SEL_MASK) >> MSM8939_CAL_SEL_SHIFT; - dev_dbg(priv->dev, "calibration mode is %d\n", mode); - - switch (mode) { - case TWO_PT_CALIB: - base1 = (cdata[3] & MSM8939_BASE1_MASK) >> MSM8939_BASE1_SHIFT; - p2[0] = (cdata[0] & MSM8939_S0_P2_MASK) >> MSM8939_S0_P2_SHIFT; - p2[1] = (cdata[0] & MSM8939_S1_P2_MASK) >> MSM8939_S1_P2_SHIFT; - p2[2] = (cdata[1] & MSM8939_S2_P2_MASK) >> MSM8939_S2_P2_SHIFT; - p2[3] = (cdata[1] & MSM8939_S3_P2_MASK) >> MSM8939_S3_P2_SHIFT; - p2[4] = (cdata[1] & MSM8939_S4_P2_MASK) >> MSM8939_S4_P2_SHIFT; - p2[5] = (cdata[2] & MSM8939_S5_P2_MASK) >> MSM8939_S5_P2_SHIFT; - p2[6] = (cdata[2] & MSM8939_S6_P2_MASK) >> MSM8939_S6_P2_SHIFT; - p2[7] = (cdata[3] & MSM8939_S7_P2_MASK) >> MSM8939_S7_P2_SHIFT; - p2[8] = (cdata[3] & MSM8939_S8_P2_MASK) >> MSM8939_S8_P2_SHIFT; - p2[9] = (cdata[4] & MSM8939_S9_P2_MASK_0_4) >> MSM8939_S9_P2_SHIFT_0_4; - p2[9] |= ((cdata[5] & MSM8939_S9_P2_MASK_5) >> MSM8939_S9_P2_SHIFT_5) << 5; - for (i = 0; i < priv->num_sensors; i++) - p2[i] = (base1 + p2[i]) << 2; - fallthrough; - case ONE_PT_CALIB2: - base0 = (cdata[2] & MSM8939_BASE0_MASK) >> MSM8939_BASE0_SHIFT; - p1[0] = (cdata[0] & MSM8939_S0_P1_MASK) >> MSM8939_S0_P1_SHIFT; - p1[1] = (cdata[0] & MSM8939_S1_P1_MASK) >> MSM8939_S1_P1_SHIFT; - p1[2] = (cdata[0] & MSM8939_S2_P1_MASK_0_4) >> MSM8939_S2_P1_SHIFT_0_4; - p1[2] |= ((cdata[1] & MSM8939_S2_P1_MASK_5) >> MSM8939_S2_P1_SHIFT_5) << 5; - p1[3] = (cdata[1] & MSM8939_S3_P1_MASK) >> MSM8939_S3_P1_SHIFT; - p1[4] = (cdata[1] & MSM8939_S4_P1_MASK) >> MSM8939_S4_P1_SHIFT; - p1[5] = (cdata[2] & MSM8939_S5_P1_MASK) >> MSM8939_S5_P1_SHIFT; - p1[6] = (cdata[2] & MSM8939_S6_P1_MASK) >> MSM8939_S6_P1_SHIFT; - p1[7] = (cdata[3] & MSM8939_S7_P1_MASK) >> MSM8939_S7_P1_SHIFT; - p1[8] = (cdata[3] & MSM8939_S8_P1_MASK) >> MSM8939_S8_P1_SHIFT; - p1[9] = (cdata[4] & MSM8939_S9_P1_MASK) >> MSM8939_S9_P1_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p1[i] = ((base0) + p1[i]) << 2; - break; - default: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] = 500; - p2[i] = 780; - } - break; - } + mode = tsens_read_calibration_legacy(priv, &tsens_8939_nvmem, + p1, p2, + qfprom_cdata, NULL); compute_intercept_slope(priv, p1, p2, mode); kfree(qfprom_cdata); @@ -360,21 +173,9 @@ static int calibrate_8939(struct tsens_priv *priv) return 0; } -static int calibrate_8974_nvmem(struct tsens_priv *priv) +static void fixup_8974_points(int mode, u32 *p1, u32 *p2) { - int i, ret, mode; - u32 p1[11], p2[11]; - u32 backup; - - ret = nvmem_cell_read_variable_le_u32(priv->dev, "use_backup", &backup); - if (ret == -ENOENT) - dev_warn(priv->dev, "Please migrate to separate nvmem cells for calibration data\n"); - if (ret < 0) - return ret; - - mode = tsens_read_calibration(priv, 2, p1, p2, backup == BKP_SEL); - if (mode < 0) - return mode; + int i; if (mode == NO_PT_CALIB) { p1[0] += 2; @@ -389,7 +190,7 @@ static int calibrate_8974_nvmem(struct tsens_priv *priv) p1[9] += 9; p1[10] += 8; } else { - for (i = 0; i < priv->num_sensors; i++) { + for (i = 0; i < 11; i++) { /* * ONE_PT_CALIB requires using addition here instead of * using OR operation. @@ -399,6 +200,26 @@ static int calibrate_8974_nvmem(struct tsens_priv *priv) } } +} + +static int calibrate_8974_nvmem(struct tsens_priv *priv) +{ + u32 p1[11], p2[11]; + u32 backup; + int ret, mode; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "use_backup", &backup); + if (ret == -ENOENT) + dev_warn(priv->dev, "Please migrate to separate nvmem cells for calibration data\n"); + if (ret < 0) + return ret; + + mode = tsens_read_calibration(priv, 2, p1, p2, backup == BKP_SEL); + if (mode < 0) + return mode; + + fixup_8974_points(mode, p1, p2); + compute_intercept_slope(priv, p1, p2, mode); return 0; @@ -406,12 +227,10 @@ static int calibrate_8974_nvmem(struct tsens_priv *priv) static int calibrate_8974(struct tsens_priv *priv) { - int base1 = 0, base2 = 0, i; u32 p1[11], p2[11]; - int mode = 0; u32 *calib, *bkp; u32 calib_redun_sel; - int ret; + int mode, ret; ret = calibrate_8974_nvmem(priv); if (ret == 0) @@ -427,116 +246,18 @@ static int calibrate_8974(struct tsens_priv *priv) return PTR_ERR(bkp); } - calib_redun_sel = bkp[1] & BKP_REDUN_SEL; - calib_redun_sel >>= BKP_REDUN_SHIFT; - - if (calib_redun_sel == BKP_SEL) { - mode = (calib[4] & CAL_SEL_0_1) >> CAL_SEL_SHIFT; - mode |= (calib[5] & CAL_SEL_2) >> CAL_SEL_SHIFT_2; - - switch (mode) { - case TWO_PT_CALIB: - base2 = (bkp[2] & BASE2_BKP_MASK) >> BASE2_BKP_SHIFT; - p2[0] = (bkp[2] & S0_P2_BKP_MASK) >> S0_P2_BKP_SHIFT; - p2[1] = (bkp[3] & S1_P2_BKP_MASK); - p2[2] = (bkp[3] & S2_P2_BKP_MASK) >> S2_P2_BKP_SHIFT; - p2[3] = (bkp[3] & S3_P2_BKP_MASK) >> S3_P2_BKP_SHIFT; - p2[4] = (bkp[3] & S4_P2_BKP_MASK) >> S4_P2_BKP_SHIFT; - p2[5] = (calib[4] & S5_P2_BKP_MASK) >> S5_P2_BKP_SHIFT; - p2[6] = (calib[5] & S6_P2_BKP_MASK); - p2[7] = (calib[5] & S7_P2_BKP_MASK) >> S7_P2_BKP_SHIFT; - p2[8] = (calib[5] & S8_P2_BKP_MASK) >> S8_P2_BKP_SHIFT; - p2[9] = (calib[5] & S9_P2_BKP_MASK) >> S9_P2_BKP_SHIFT; - p2[10] = (calib[5] & S10_P2_BKP_MASK) >> S10_P2_BKP_SHIFT; - fallthrough; - case ONE_PT_CALIB: - case ONE_PT_CALIB2: - base1 = bkp[0] & BASE1_MASK; - p1[0] = (bkp[0] & S0_P1_MASK) >> S0_P1_SHIFT; - p1[1] = (bkp[0] & S1_P1_MASK) >> S1_P1_SHIFT; - p1[2] = (bkp[0] & S2_P1_MASK) >> S2_P1_SHIFT; - p1[3] = (bkp[0] & S3_P1_MASK) >> S3_P1_SHIFT; - p1[4] = (bkp[1] & S4_P1_MASK); - p1[5] = (bkp[1] & S5_P1_MASK) >> S5_P1_SHIFT; - p1[6] = (bkp[1] & S6_P1_MASK) >> S6_P1_SHIFT; - p1[7] = (bkp[1] & S7_P1_MASK) >> S7_P1_SHIFT; - p1[8] = (bkp[2] & S8_P1_MASK_BKP) >> S8_P1_SHIFT; - p1[9] = (bkp[2] & S9_P1_MASK_BKP) >> S9_P1_BKP_SHIFT; - p1[10] = (bkp[2] & S10_P1_MASK_BKP) >> S10_P1_BKP_SHIFT; - break; - } - } else { - mode = (calib[1] & CAL_SEL_0_1) >> CAL_SEL_SHIFT; - mode |= (calib[3] & CAL_SEL_2) >> CAL_SEL_SHIFT_2; - - switch (mode) { - case TWO_PT_CALIB: - base2 = (calib[2] & BASE2_MASK) >> BASE2_SHIFT; - p2[0] = (calib[2] & S0_P2_MASK) >> S0_P2_SHIFT; - p2[1] = (calib[2] & S1_P2_MASK) >> S1_P2_SHIFT; - p2[2] = (calib[3] & S2_P2_MASK); - p2[3] = (calib[3] & S3_P2_MASK) >> S3_P2_SHIFT; - p2[4] = (calib[3] & S4_P2_MASK) >> S4_P2_SHIFT; - p2[5] = (calib[3] & S5_P2_MASK) >> S5_P2_SHIFT; - p2[6] = (calib[3] & S6_P2_MASK) >> S6_P2_SHIFT; - p2[7] = (calib[4] & S7_P2_MASK); - p2[8] = (calib[4] & S8_P2_MASK) >> S8_P2_SHIFT; - p2[9] = (calib[4] & S9_P2_MASK) >> S9_P2_SHIFT; - p2[10] = (calib[4] & S10_P2_MASK) >> S10_P2_SHIFT; - fallthrough; - case ONE_PT_CALIB: - case ONE_PT_CALIB2: - base1 = calib[0] & BASE1_MASK; - p1[0] = (calib[0] & S0_P1_MASK) >> S0_P1_SHIFT; - p1[1] = (calib[0] & S1_P1_MASK) >> S1_P1_SHIFT; - p1[2] = (calib[0] & S2_P1_MASK) >> S2_P1_SHIFT; - p1[3] = (calib[0] & S3_P1_MASK) >> S3_P1_SHIFT; - p1[4] = (calib[1] & S4_P1_MASK); - p1[5] = (calib[1] & S5_P1_MASK) >> S5_P1_SHIFT; - p1[6] = (calib[1] & S6_P1_MASK) >> S6_P1_SHIFT; - p1[7] = (calib[1] & S7_P1_MASK) >> S7_P1_SHIFT; - p1[8] = (calib[1] & S8_P1_MASK) >> S8_P1_SHIFT; - p1[9] = (calib[2] & S9_P1_MASK); - p1[10] = (calib[2] & S10_P1_MASK) >> S10_P1_SHIFT; - break; - } - } + calib_redun_sel = FIELD_GET(BKP_REDUN_SEL, bkp[1]); - switch (mode) { - case ONE_PT_CALIB: - for (i = 0; i < priv->num_sensors; i++) - p1[i] += (base1 << 2) | BIT_APPEND; - break; - case TWO_PT_CALIB: - for (i = 0; i < priv->num_sensors; i++) { - p2[i] += base2; - p2[i] <<= 2; - p2[i] |= BIT_APPEND; - } - fallthrough; - case ONE_PT_CALIB2: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] += base1; - p1[i] <<= 2; - p1[i] |= BIT_APPEND; - } - break; - default: - for (i = 0; i < priv->num_sensors; i++) - p2[i] = 780; - p1[0] = 502; - p1[1] = 509; - p1[2] = 503; - p1[3] = 509; - p1[4] = 505; - p1[5] = 509; - p1[6] = 507; - p1[7] = 510; - p1[8] = 508; - p1[9] = 509; - p1[10] = 508; - break; - } + if (calib_redun_sel == BKP_SEL) + mode = tsens_read_calibration_legacy(priv, &tsens_8974_backup_nvmem, + p1, p2, + bkp, calib); + else + mode = tsens_read_calibration_legacy(priv, &tsens_8974_nvmem, + p1, p2, + calib, NULL); + + fixup_8974_points(mode, p1, p2); compute_intercept_slope(priv, p1, p2, mode); kfree(calib); @@ -547,11 +268,9 @@ static int calibrate_8974(struct tsens_priv *priv) static int calibrate_9607(struct tsens_priv *priv) { - int base, i; u32 p1[5], p2[5]; - int mode = 0; u32 *qfprom_cdata; - int ret; + int mode, ret; ret = tsens_calibrate_common(priv); if (!ret) @@ -561,37 +280,9 @@ static int calibrate_9607(struct tsens_priv *priv) if (IS_ERR(qfprom_cdata)) return PTR_ERR(qfprom_cdata); - mode = (qfprom_cdata[2] & MDM9607_CAL_SEL_MASK) >> MDM9607_CAL_SEL_SHIFT; - dev_dbg(priv->dev, "calibration mode is %d\n", mode); - - switch (mode) { - case TWO_PT_CALIB: - base = (qfprom_cdata[2] & MDM9607_BASE1_MASK) >> MDM9607_BASE1_SHIFT; - p2[0] = (qfprom_cdata[0] & MDM9607_S0_P2_MASK) >> MDM9607_S0_P2_SHIFT; - p2[1] = (qfprom_cdata[0] & MDM9607_S1_P2_MASK) >> MDM9607_S1_P2_SHIFT; - p2[2] = (qfprom_cdata[1] & MDM9607_S2_P2_MASK) >> MDM9607_S2_P2_SHIFT; - p2[3] = (qfprom_cdata[1] & MDM9607_S3_P2_MASK) >> MDM9607_S3_P2_SHIFT; - p2[4] = (qfprom_cdata[2] & MDM9607_S4_P2_MASK) >> MDM9607_S4_P2_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p2[i] = ((base + p2[i]) << 2); - fallthrough; - case ONE_PT_CALIB2: - base = (qfprom_cdata[0] & MDM9607_BASE0_MASK); - p1[0] = (qfprom_cdata[0] & MDM9607_S0_P1_MASK) >> MDM9607_S0_P1_SHIFT; - p1[1] = (qfprom_cdata[0] & MDM9607_S1_P1_MASK) >> MDM9607_S1_P1_SHIFT; - p1[2] = (qfprom_cdata[1] & MDM9607_S2_P1_MASK) >> MDM9607_S2_P1_SHIFT; - p1[3] = (qfprom_cdata[1] & MDM9607_S3_P1_MASK) >> MDM9607_S3_P1_SHIFT; - p1[4] = (qfprom_cdata[2] & MDM9607_S4_P1_MASK) >> MDM9607_S4_P1_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p1[i] = ((base + p1[i]) << 2); - break; - default: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] = 500; - p2[i] = 780; - } - break; - } + mode = tsens_read_calibration_legacy(priv, &tsens_9607_nvmem, + p1, p2, + qfprom_cdata, NULL); compute_intercept_slope(priv, p1, p2, mode); kfree(qfprom_cdata); diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 5bba75a845c5..6d1ea430f90b 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -21,129 +21,54 @@ #define TM_HIGH_LOW_INT_STATUS_OFF 0x0088 #define TM_HIGH_LOW_Sn_INT_THRESHOLD_OFF 0x0090 -/* eeprom layout data for msm8956/76 (v1) */ -#define MSM8976_BASE0_MASK 0xff -#define MSM8976_BASE1_MASK 0xff -#define MSM8976_BASE1_SHIFT 8 - -#define MSM8976_S0_P1_MASK 0x3f00 -#define MSM8976_S1_P1_MASK 0x3f00000 -#define MSM8976_S2_P1_MASK 0x3f -#define MSM8976_S3_P1_MASK 0x3f000 -#define MSM8976_S4_P1_MASK 0x3f00 -#define MSM8976_S5_P1_MASK 0x3f00000 -#define MSM8976_S6_P1_MASK 0x3f -#define MSM8976_S7_P1_MASK 0x3f000 -#define MSM8976_S8_P1_MASK 0x1f8 -#define MSM8976_S9_P1_MASK 0x1f8000 -#define MSM8976_S10_P1_MASK 0xf8000000 -#define MSM8976_S10_P1_MASK_1 0x1 - -#define MSM8976_S0_P2_MASK 0xfc000 -#define MSM8976_S1_P2_MASK 0xfc000000 -#define MSM8976_S2_P2_MASK 0xfc0 -#define MSM8976_S3_P2_MASK 0xfc0000 -#define MSM8976_S4_P2_MASK 0xfc000 -#define MSM8976_S5_P2_MASK 0xfc000000 -#define MSM8976_S6_P2_MASK 0xfc0 -#define MSM8976_S7_P2_MASK 0xfc0000 -#define MSM8976_S8_P2_MASK 0x7e00 -#define MSM8976_S9_P2_MASK 0x7e00000 -#define MSM8976_S10_P2_MASK 0x7e - -#define MSM8976_S0_P1_SHIFT 8 -#define MSM8976_S1_P1_SHIFT 20 -#define MSM8976_S2_P1_SHIFT 0 -#define MSM8976_S3_P1_SHIFT 12 -#define MSM8976_S4_P1_SHIFT 8 -#define MSM8976_S5_P1_SHIFT 20 -#define MSM8976_S6_P1_SHIFT 0 -#define MSM8976_S7_P1_SHIFT 12 -#define MSM8976_S8_P1_SHIFT 3 -#define MSM8976_S9_P1_SHIFT 15 -#define MSM8976_S10_P1_SHIFT 27 -#define MSM8976_S10_P1_SHIFT_1 0 - -#define MSM8976_S0_P2_SHIFT 14 -#define MSM8976_S1_P2_SHIFT 26 -#define MSM8976_S2_P2_SHIFT 6 -#define MSM8976_S3_P2_SHIFT 18 -#define MSM8976_S4_P2_SHIFT 14 -#define MSM8976_S5_P2_SHIFT 26 -#define MSM8976_S6_P2_SHIFT 6 -#define MSM8976_S7_P2_SHIFT 18 -#define MSM8976_S8_P2_SHIFT 9 -#define MSM8976_S9_P2_SHIFT 21 -#define MSM8976_S10_P2_SHIFT 1 - -#define MSM8976_CAL_SEL_MASK 0x3 - -/* eeprom layout data for qcs404/405 (v1) */ -#define BASE0_MASK 0x000007f8 -#define BASE1_MASK 0x0007f800 -#define BASE0_SHIFT 3 -#define BASE1_SHIFT 11 - -#define S0_P1_MASK 0x0000003f -#define S1_P1_MASK 0x0003f000 -#define S2_P1_MASK 0x3f000000 -#define S3_P1_MASK 0x000003f0 -#define S4_P1_MASK 0x003f0000 -#define S5_P1_MASK 0x0000003f -#define S6_P1_MASK 0x0003f000 -#define S7_P1_MASK 0x3f000000 -#define S8_P1_MASK 0x000003f0 -#define S9_P1_MASK 0x003f0000 - -#define S0_P2_MASK 0x00000fc0 -#define S1_P2_MASK 0x00fc0000 -#define S2_P2_MASK_1_0 0xc0000000 -#define S2_P2_MASK_5_2 0x0000000f -#define S3_P2_MASK 0x0000fc00 -#define S4_P2_MASK 0x0fc00000 -#define S5_P2_MASK 0x00000fc0 -#define S6_P2_MASK 0x00fc0000 -#define S7_P2_MASK_1_0 0xc0000000 -#define S7_P2_MASK_5_2 0x0000000f -#define S8_P2_MASK 0x0000fc00 -#define S9_P2_MASK 0x0fc00000 - -#define S0_P1_SHIFT 0 -#define S0_P2_SHIFT 6 -#define S1_P1_SHIFT 12 -#define S1_P2_SHIFT 18 -#define S2_P1_SHIFT 24 -#define S2_P2_SHIFT_1_0 30 - -#define S2_P2_SHIFT_5_2 0 -#define S3_P1_SHIFT 4 -#define S3_P2_SHIFT 10 -#define S4_P1_SHIFT 16 -#define S4_P2_SHIFT 22 - -#define S5_P1_SHIFT 0 -#define S5_P2_SHIFT 6 -#define S6_P1_SHIFT 12 -#define S6_P2_SHIFT 18 -#define S7_P1_SHIFT 24 -#define S7_P2_SHIFT_1_0 30 - -#define S7_P2_SHIFT_5_2 0 -#define S8_P1_SHIFT 4 -#define S8_P2_SHIFT 10 -#define S9_P1_SHIFT 16 -#define S9_P2_SHIFT 22 - -#define CAL_SEL_MASK 7 -#define CAL_SEL_SHIFT 0 +struct tsens_legacy_calibration_format tsens_qcs404_nvmem = { + .base_len = 8, + .base_shift = 2, + .sp_len = 6, + .mode = { 4, 0 }, + .invalid = { 4, 2 }, + .base = { { 4, 3 }, { 4, 11 } }, + .sp = { + { { 0, 0 }, { 0, 6 } }, + { { 0, 12 }, { 0, 18 } }, + { { 0, 24 }, { 0, 30 } }, + { { 1, 4 }, { 1, 10 } }, + { { 1, 16 }, { 1, 22 } }, + { { 2, 0 }, { 2, 6 } }, + { { 2, 12 }, { 2, 18 } }, + { { 2, 24 }, { 2, 30 } }, + { { 3, 4 }, { 3, 10 } }, + { { 3, 16 }, { 3, 22 } }, + }, +}; + +struct tsens_legacy_calibration_format tsens_8976_nvmem = { + .base_len = 8, + .base_shift = 2, + .sp_len = 6, + .mode = { 4, 0 }, + .invalid = { 4, 2 }, + .base = { { 0, 0 }, { 2, 8 } }, + .sp = { + { { 0, 8 }, { 0, 14 } }, + { { 0, 20 }, { 0, 26 } }, + { { 1, 0 }, { 1, 6 } }, + { { 1, 12 }, { 1, 18 } }, + { { 2, 8 }, { 2, 14 } }, + { { 2, 20 }, { 2, 26 } }, + { { 3, 0 }, { 3, 6 } }, + { { 3, 12 }, { 3, 18 } }, + { { 4, 2 }, { 4, 9 } }, + { { 4, 14 }, { 4, 21 } }, + { { 4, 26 }, { 5, 1 } }, + }, +}; static int calibrate_v1(struct tsens_priv *priv) { - u32 base0 = 0, base1 = 0; u32 p1[10], p2[10]; - u32 mode = 0, lsb = 0, msb = 0; u32 *qfprom_cdata; - int i, ret; + int mode, ret; ret = tsens_calibrate_common(priv); if (!ret) @@ -153,53 +78,9 @@ static int calibrate_v1(struct tsens_priv *priv) if (IS_ERR(qfprom_cdata)) return PTR_ERR(qfprom_cdata); - mode = (qfprom_cdata[4] & CAL_SEL_MASK) >> CAL_SEL_SHIFT; - dev_dbg(priv->dev, "calibration mode is %d\n", mode); - - switch (mode) { - case TWO_PT_CALIB: - base1 = (qfprom_cdata[4] & BASE1_MASK) >> BASE1_SHIFT; - p2[0] = (qfprom_cdata[0] & S0_P2_MASK) >> S0_P2_SHIFT; - p2[1] = (qfprom_cdata[0] & S1_P2_MASK) >> S1_P2_SHIFT; - /* This value is split over two registers, 2 bits and 4 bits */ - lsb = (qfprom_cdata[0] & S2_P2_MASK_1_0) >> S2_P2_SHIFT_1_0; - msb = (qfprom_cdata[1] & S2_P2_MASK_5_2) >> S2_P2_SHIFT_5_2; - p2[2] = msb << 2 | lsb; - p2[3] = (qfprom_cdata[1] & S3_P2_MASK) >> S3_P2_SHIFT; - p2[4] = (qfprom_cdata[1] & S4_P2_MASK) >> S4_P2_SHIFT; - p2[5] = (qfprom_cdata[2] & S5_P2_MASK) >> S5_P2_SHIFT; - p2[6] = (qfprom_cdata[2] & S6_P2_MASK) >> S6_P2_SHIFT; - /* This value is split over two registers, 2 bits and 4 bits */ - lsb = (qfprom_cdata[2] & S7_P2_MASK_1_0) >> S7_P2_SHIFT_1_0; - msb = (qfprom_cdata[3] & S7_P2_MASK_5_2) >> S7_P2_SHIFT_5_2; - p2[7] = msb << 2 | lsb; - p2[8] = (qfprom_cdata[3] & S8_P2_MASK) >> S8_P2_SHIFT; - p2[9] = (qfprom_cdata[3] & S9_P2_MASK) >> S9_P2_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p2[i] = ((base1 + p2[i]) << 2); - fallthrough; - case ONE_PT_CALIB2: - base0 = (qfprom_cdata[4] & BASE0_MASK) >> BASE0_SHIFT; - p1[0] = (qfprom_cdata[0] & S0_P1_MASK) >> S0_P1_SHIFT; - p1[1] = (qfprom_cdata[0] & S1_P1_MASK) >> S1_P1_SHIFT; - p1[2] = (qfprom_cdata[0] & S2_P1_MASK) >> S2_P1_SHIFT; - p1[3] = (qfprom_cdata[1] & S3_P1_MASK) >> S3_P1_SHIFT; - p1[4] = (qfprom_cdata[1] & S4_P1_MASK) >> S4_P1_SHIFT; - p1[5] = (qfprom_cdata[2] & S5_P1_MASK) >> S5_P1_SHIFT; - p1[6] = (qfprom_cdata[2] & S6_P1_MASK) >> S6_P1_SHIFT; - p1[7] = (qfprom_cdata[2] & S7_P1_MASK) >> S7_P1_SHIFT; - p1[8] = (qfprom_cdata[3] & S8_P1_MASK) >> S8_P1_SHIFT; - p1[9] = (qfprom_cdata[3] & S9_P1_MASK) >> S9_P1_SHIFT; - for (i = 0; i < priv->num_sensors; i++) - p1[i] = (((base0) + p1[i]) << 2); - break; - default: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] = 500; - p2[i] = 780; - } - break; - } + mode = tsens_read_calibration_legacy(priv, &tsens_qcs404_nvmem, + p1, p2, + qfprom_cdata, NULL); compute_intercept_slope(priv, p1, p2, mode); kfree(qfprom_cdata); @@ -209,11 +90,9 @@ static int calibrate_v1(struct tsens_priv *priv) static int calibrate_8976(struct tsens_priv *priv) { - int base0 = 0, base1 = 0, i; u32 p1[11], p2[11]; - int mode = 0, tmp = 0; u32 *qfprom_cdata; - int ret; + int mode, ret; ret = tsens_calibrate_common(priv); if (!ret) @@ -223,53 +102,10 @@ static int calibrate_8976(struct tsens_priv *priv) if (IS_ERR(qfprom_cdata)) return PTR_ERR(qfprom_cdata); - mode = (qfprom_cdata[4] & MSM8976_CAL_SEL_MASK); - dev_dbg(priv->dev, "calibration mode is %d\n", mode); - - switch (mode) { - case TWO_PT_CALIB: - base1 = (qfprom_cdata[2] & MSM8976_BASE1_MASK) >> MSM8976_BASE1_SHIFT; - p2[0] = (qfprom_cdata[0] & MSM8976_S0_P2_MASK) >> MSM8976_S0_P2_SHIFT; - p2[1] = (qfprom_cdata[0] & MSM8976_S1_P2_MASK) >> MSM8976_S1_P2_SHIFT; - p2[2] = (qfprom_cdata[1] & MSM8976_S2_P2_MASK) >> MSM8976_S2_P2_SHIFT; - p2[3] = (qfprom_cdata[1] & MSM8976_S3_P2_MASK) >> MSM8976_S3_P2_SHIFT; - p2[4] = (qfprom_cdata[2] & MSM8976_S4_P2_MASK) >> MSM8976_S4_P2_SHIFT; - p2[5] = (qfprom_cdata[2] & MSM8976_S5_P2_MASK) >> MSM8976_S5_P2_SHIFT; - p2[6] = (qfprom_cdata[3] & MSM8976_S6_P2_MASK) >> MSM8976_S6_P2_SHIFT; - p2[7] = (qfprom_cdata[3] & MSM8976_S7_P2_MASK) >> MSM8976_S7_P2_SHIFT; - p2[8] = (qfprom_cdata[4] & MSM8976_S8_P2_MASK) >> MSM8976_S8_P2_SHIFT; - p2[9] = (qfprom_cdata[4] & MSM8976_S9_P2_MASK) >> MSM8976_S9_P2_SHIFT; - p2[10] = (qfprom_cdata[5] & MSM8976_S10_P2_MASK) >> MSM8976_S10_P2_SHIFT; - - for (i = 0; i < priv->num_sensors; i++) - p2[i] = ((base1 + p2[i]) << 2); - fallthrough; - case ONE_PT_CALIB2: - base0 = qfprom_cdata[0] & MSM8976_BASE0_MASK; - p1[0] = (qfprom_cdata[0] & MSM8976_S0_P1_MASK) >> MSM8976_S0_P1_SHIFT; - p1[1] = (qfprom_cdata[0] & MSM8976_S1_P1_MASK) >> MSM8976_S1_P1_SHIFT; - p1[2] = (qfprom_cdata[1] & MSM8976_S2_P1_MASK) >> MSM8976_S2_P1_SHIFT; - p1[3] = (qfprom_cdata[1] & MSM8976_S3_P1_MASK) >> MSM8976_S3_P1_SHIFT; - p1[4] = (qfprom_cdata[2] & MSM8976_S4_P1_MASK) >> MSM8976_S4_P1_SHIFT; - p1[5] = (qfprom_cdata[2] & MSM8976_S5_P1_MASK) >> MSM8976_S5_P1_SHIFT; - p1[6] = (qfprom_cdata[3] & MSM8976_S6_P1_MASK) >> MSM8976_S6_P1_SHIFT; - p1[7] = (qfprom_cdata[3] & MSM8976_S7_P1_MASK) >> MSM8976_S7_P1_SHIFT; - p1[8] = (qfprom_cdata[4] & MSM8976_S8_P1_MASK) >> MSM8976_S8_P1_SHIFT; - p1[9] = (qfprom_cdata[4] & MSM8976_S9_P1_MASK) >> MSM8976_S9_P1_SHIFT; - p1[10] = (qfprom_cdata[4] & MSM8976_S10_P1_MASK) >> MSM8976_S10_P1_SHIFT; - tmp = (qfprom_cdata[5] & MSM8976_S10_P1_MASK_1) << MSM8976_S10_P1_SHIFT_1; - p1[10] |= tmp; - - for (i = 0; i < priv->num_sensors; i++) - p1[i] = (((base0) + p1[i]) << 2); - break; - default: - for (i = 0; i < priv->num_sensors; i++) { - p1[i] = 500; - p2[i] = 780; - } - break; - } + mode = tsens_read_calibration_legacy(priv, &tsens_8976_nvmem, + p1, p2, + qfprom_cdata, NULL); + compute_intercept_slope(priv, p1, p2, mode); kfree(qfprom_cdata); diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 83bf60fa9008..c59a2e742839 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -169,6 +169,70 @@ int tsens_calibrate_common(struct tsens_priv *priv) return tsens_calibrate_nvmem(priv, 2); } +static u32 tsens_read_cell(const struct tsens_single_value *cell, u8 len, u32 *data0, u32 *data1) +{ + u32 val; + u32 *data = cell->blob ? data1 : data0; + + if (cell->shift + len <= 32) { + val = data[cell->idx] >> cell->shift; + } else { + u8 part = 32 - cell->shift; + + val = data[cell->idx] >> cell->shift; + val |= data[cell->idx + 1] << part; + } + + return val & ((1 << len) - 1); +} + +int tsens_read_calibration_legacy(struct tsens_priv *priv, + const struct tsens_legacy_calibration_format *format, + u32 *p1, u32 *p2, + u32 *cdata0, u32 *cdata1) +{ + u32 mode, invalid; + u32 base1, base2; + int i; + + mode = tsens_read_cell(&format->mode, 2, cdata0, cdata1); + invalid = tsens_read_cell(&format->invalid, 1, cdata0, cdata1); + if (invalid) + mode = NO_PT_CALIB; + dev_dbg(priv->dev, "calibration mode is %d\n", mode); + + base1 = tsens_read_cell(&format->base[0], format->base_len, cdata0, cdata1); + base2 = tsens_read_cell(&format->base[1], format->base_len, cdata0, cdata1); + + for (i = 0; i < priv->num_sensors; i++) { + p1[i] = tsens_read_cell(&format->sp[i][0], format->sp_len, cdata0, cdata1); + p2[i] = tsens_read_cell(&format->sp[i][1], format->sp_len, cdata0, cdata1); + } + + switch (mode) { + case ONE_PT_CALIB: + for (i = 0; i < priv->num_sensors; i++) + p1[i] = p1[i] + (base1 << format->base_shift); + break; + case TWO_PT_CALIB: + for (i = 0; i < priv->num_sensors; i++) + p2[i] = (p2[i] + base2) << format->base_shift; + fallthrough; + case ONE_PT_CALIB2: + for (i = 0; i < priv->num_sensors; i++) + p1[i] = (p1[i] + base1) << format->base_shift; + break; + default: + dev_dbg(priv->dev, "calibrationless mode\n"); + for (i = 0; i < priv->num_sensors; i++) { + p1[i] = 500; + p2[i] = 780; + } + } + + return mode; +} + /* * Use this function on devices where slope and offset calculations * depend on calibration data read from qfprom. On others the slope diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index a9ae8df9f810..dba9cd38f637 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -584,7 +584,45 @@ struct tsens_priv { struct tsens_sensor sensor[]; }; +/** + * struct tsens_single_value - internal representation of a single field inside nvmem calibration data + * @idx: index into the u32 data array + * @shift: the shift of the first bit in the value + * @blob: index of the data blob to use for this cell + */ +struct tsens_single_value { + u8 idx; + u8 shift; + u8 blob; +}; + +/** + * struct tsens_legacy_calibration_format - description of calibration data used when parsing the legacy nvmem blob + * @base_len: the length of the base fields inside calibration data + * @base_shift: the shift to be applied to base data + * @sp_len: the length of the sN_pM fields inside calibration data + * @mode: descriptor of the calibration mode field + * @invalid: descriptor of the calibration mode invalid field + * @base: descriptors of the base0 and base1 fields + * @sp: descriptors of the sN_pM fields + */ +struct tsens_legacy_calibration_format { + unsigned int base_len; + unsigned int base_shift; + unsigned int sp_len; + /* just two bits */ + struct tsens_single_value mode; + /* on all platforms except 8974 invalid is the third bit of what downstream calls 'mode' */ + struct tsens_single_value invalid; + struct tsens_single_value base[2]; + struct tsens_single_value sp[][2]; +}; + char *qfprom_read(struct device *dev, const char *cname); +int tsens_read_calibration_legacy(struct tsens_priv *priv, + const struct tsens_legacy_calibration_format *format, + u32 *p1, u32 *p2, + u32 *cdata, u32 *csel); int tsens_read_calibration(struct tsens_priv *priv, int shift, u32 *p1, u32 *p2, bool backup); int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift); int tsens_calibrate_common(struct tsens_priv *priv); From patchwork Wed Dec 21 02:05:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 636057 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09BEEC3DA6E for ; Wed, 21 Dec 2022 02:05:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234419AbiLUCFm (ORCPT ); Tue, 20 Dec 2022 21:05:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234180AbiLUCFe (ORCPT ); Tue, 20 Dec 2022 21:05:34 -0500 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12DAC20192 for ; Tue, 20 Dec 2022 18:05:32 -0800 (PST) Received: by mail-lf1-x12f.google.com with SMTP id b13so21392220lfo.3 for ; Tue, 20 Dec 2022 18:05:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wbww+IqG9GctHbEU9KIuyB6Vi/2pULzTX7OLKgs1wwk=; b=crJzRtwgAE87DUY0ezKOhJ/YGD5rDb61yWuXNDjwJs7WGV0sZyex8ss9BVIU+IWHm6 vvjMaWB1aqkqqUeOJwPyEpPOBdq4Po8td6CWn0FEL41od/2yZV/UQxfeP06YGvzGEwti KZkPEzf9fetD0392Ge3QuNJ1vt0tRQnA2DpK5LeEmQT9g/lQYtxUC5BbHczBjLFs/hAa VbNOsUCgsRN5QekcJd6e8UyXg9TUWesZlFudj+abn75ckEkyt0rvtQTZ9iRYiGS95GVk S4wwEjkKLcK8Fkf3p8LO4AYnk7LUwzUN5e4ZiO+hW4pQenCrMbLdlBw8mIKUaDWV5s+1 8JCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wbww+IqG9GctHbEU9KIuyB6Vi/2pULzTX7OLKgs1wwk=; b=KaE2MAdkS97r37o/C9ajlUWe0+65cKE67ocajic6McH7V8iYw8z/JSBpYVpIRfaGdt zCt0+uh5nkVf0HPRYeoblVa99flHsWHGpA1ufOFJ5iSaw+6uubvHBun4SQ0vQWTIOfy4 vgpbm0z+xVikslmJwICC5Zj62r2cX9QSwbUHPAKOZT/6KImHLwVTs9XqeJh23IbEmWAa EAio+mMESqbIDPlxFSZ1Nsrvb8E/WUgknrc//475S4dxKmQCSCCP9gPkip8+535skwl6 njqpIwXnrEsxYTtX7D7zwVpXyXmtfhU/4iYbebztKMsokiW7wtLujZmW3SkDjiq4zlxw +ncA== X-Gm-Message-State: AFqh2kpD9boW91RD3Eh1fcIjnNu8JrYN6B2ZjgndAPcAuQwUD7m6zNMu iZeaItsaAgnGERk24nShoGc1gnSeCq7Tzd3KbXs= X-Google-Smtp-Source: AMrXdXtJiQEDtE5EIstQmwoZitxcGRBiWJfzn2dnViwsysUtefTWrMOqpaAjx/QaInD8cWcKocDabw== X-Received: by 2002:a05:6512:539:b0:4c5:64ed:df06 with SMTP id o25-20020a056512053900b004c564eddf06mr53711lfc.27.1671588331574; Tue, 20 Dec 2022 18:05:31 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:31 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 12/20] thermal/drivers/tsens: Drop single-cell code for mdm9607 Date: Wed, 21 Dec 2022 04:05:12 +0200 Message-Id: <20221221020520.1326964-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There is no dtsi file for mdm9607 in the kernel sources. Drop the compatibility with unofficial dtsi and remove support for handling the single-cell calibration data on mdm9607. Cc: Konrad Dybcio Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 38 ++++++------------------------- 1 file changed, 7 insertions(+), 31 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index 6b8f7cb7ab9d..d3f46f44c1e1 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -266,30 +266,6 @@ static int calibrate_8974(struct tsens_priv *priv) return 0; } -static int calibrate_9607(struct tsens_priv *priv) -{ - u32 p1[5], p2[5]; - u32 *qfprom_cdata; - int mode, ret; - - ret = tsens_calibrate_common(priv); - if (!ret) - return 0; - - qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); - if (IS_ERR(qfprom_cdata)) - return PTR_ERR(qfprom_cdata); - - mode = tsens_read_calibration_legacy(priv, &tsens_9607_nvmem, - p1, p2, - qfprom_cdata, NULL); - - compute_intercept_slope(priv, p1, p2, mode); - kfree(qfprom_cdata); - - return 0; -} - static int __init init_8939(struct tsens_priv *priv) { priv->sensor[0].slope = 2911; priv->sensor[1].slope = 2789; @@ -353,6 +329,12 @@ static const struct reg_field tsens_v0_1_regfields[MAX_REGFIELDS] = { [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0), }; +static const struct tsens_ops ops_v0_1 = { + .init = init_common, + .calibrate = tsens_calibrate_common, + .get_temp = get_temp_common, +}; + static const struct tsens_ops ops_8916 = { .init = init_common, .calibrate = calibrate_8916, @@ -396,15 +378,9 @@ struct tsens_plat_data data_8974 = { .fields = tsens_v0_1_regfields, }; -static const struct tsens_ops ops_9607 = { - .init = init_common, - .calibrate = calibrate_9607, - .get_temp = get_temp_common, -}; - struct tsens_plat_data data_9607 = { .num_sensors = 5, - .ops = &ops_9607, + .ops = &ops_v0_1, .feat = &tsens_v0_1_feat, .fields = tsens_v0_1_regfields, }; From patchwork Wed Dec 21 02:05:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 636056 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2092DC4167B for ; Wed, 21 Dec 2022 02:05:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234430AbiLUCFs (ORCPT ); Tue, 20 Dec 2022 21:05:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234385AbiLUCFh (ORCPT ); Tue, 20 Dec 2022 21:05:37 -0500 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0059120354 for ; Tue, 20 Dec 2022 18:05:33 -0800 (PST) Received: by mail-lf1-x131.google.com with SMTP id p36so21320771lfa.12 for ; Tue, 20 Dec 2022 18:05:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8esKx8S7sc+Ikm/lxRjH7mI5mO3ckUZswKh/6CRSk80=; b=RnxFcBdJCboA2a1MFYkKgygb0YchHL9pjxD3Kn8TPSwC8P3EFHw+ZquwgpSNT0ZE2Z KBUbVm1Bmh6nBHVbtqx7/WhVWLCx0YMYpennSWMn6ztgcX1yZD0uFgE9OxQJIk7OPSCA gT4yQPQUCRu9MPUoi7FJiS6iEUDxIJcFlUEp8fiwHBtO7ZZNnkXkF6boqlwnXP/2tyMF 4qY+h3dhczCRZ/aKohcheHoOIaNZn1LSoQUYH3uU2Ac3RTDcoS7GaF/28YwsYfHx7GgB k80w5+V/e1CJYoQOmNDzV682KgV+S6qQT3e7qClWHWIu7ocDzG6DCitMSbwcyY7kMp+H 6uxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8esKx8S7sc+Ikm/lxRjH7mI5mO3ckUZswKh/6CRSk80=; b=4MeUdgKR+ZrAfmHIAYr6tffzNTm40NrT7RHqFJrGHKVXj6Wo9IQ3s7BHEE6L5M9Lwd 9Taz1EGr24fwm0DFUw1eMpdupMRhVxI9DPR0vCX1boEkSFfisH2FE11alv/VxYz4hLlL 1vfq+63Tuii2gcSSKGdvDxB2pKoBYjdxBIwwirocTcMBckwndcUBZ6zukG5NBkZpjYnH 14lG+Gu/LQZR7EpzJTOuoAK/KX199gt7o9w3dqGFjlPdRm9ve4tyq2E0QqrQcY2O8xhU vNz4PzJoUKpYD7bQET9UK8RvEmYfcAYvISMhBJLEebUk5Nf1c3AUhNe8QZHUfDxyUPBH gTyg== X-Gm-Message-State: AFqh2kq/0IbZkqvrrcK6ORVrpK+aLq2HxeNV28R/Cd8IGVIlN02P+L3F sCgNytHDQWeMi6T6pyZF9nj3oA== X-Google-Smtp-Source: AMrXdXtYUgxdnROakETE2KiLSyHjaR1n8cZvC+Xr0AEkNsDD6Pz9yq8WCmDfQsNdaE4O0CNq3ZXtjw== X-Received: by 2002:a05:6512:3d2a:b0:4ae:7974:7d32 with SMTP id d42-20020a0565123d2a00b004ae79747d32mr1840575lfv.29.1671588332373; Tue, 20 Dec 2022 18:05:32 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:32 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Shawn Guo Subject: [PATCH v4 13/20] thermal/drivers/tsens: Drop single-cell code for msm8939 Date: Wed, 21 Dec 2022 04:05:13 +0200 Message-Id: <20221221020520.1326964-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There is no dtsi file for msm8939 in the kernel sources. Drop the compatibility with unofficial dtsi and remove support for handling the single-cell calibration data on msm8939. Cc: Shawn Guo Cc: Bryan O'Donoghue Reviewed-by: Bryan O'Donoghue Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 26 +------------------------- 1 file changed, 1 insertion(+), 25 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index d3f46f44c1e1..7ebf5a2ca452 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -149,30 +149,6 @@ static int calibrate_8916(struct tsens_priv *priv) return 0; } -static int calibrate_8939(struct tsens_priv *priv) -{ - u32 p1[10], p2[10]; - u32 *qfprom_cdata; - int mode, ret; - - ret = tsens_calibrate_common(priv); - if (!ret) - return 0; - - qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); - if (IS_ERR(qfprom_cdata)) - return PTR_ERR(qfprom_cdata); - - mode = tsens_read_calibration_legacy(priv, &tsens_8939_nvmem, - p1, p2, - qfprom_cdata, NULL); - - compute_intercept_slope(priv, p1, p2, mode); - kfree(qfprom_cdata); - - return 0; -} - static void fixup_8974_points(int mode, u32 *p1, u32 *p2) { int i; @@ -352,7 +328,7 @@ struct tsens_plat_data data_8916 = { static const struct tsens_ops ops_8939 = { .init = init_8939, - .calibrate = calibrate_8939, + .calibrate = tsens_calibrate_common, .get_temp = get_temp_common, }; From patchwork Wed Dec 21 02:05:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635680 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47B8EC4167B for ; Wed, 21 Dec 2022 02:05:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234344AbiLUCFv (ORCPT ); Tue, 20 Dec 2022 21:05:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53314 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234393AbiLUCFi (ORCPT ); Tue, 20 Dec 2022 21:05:38 -0500 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B87802035C for ; Tue, 20 Dec 2022 18:05:34 -0800 (PST) Received: by mail-lf1-x133.google.com with SMTP id p36so21320799lfa.12 for ; Tue, 20 Dec 2022 18:05:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r/9QwXldICsXiYuGReP63jHiFicVjmDMz2iVFLO9YmY=; b=ObfSQ1DImuLQ3sukd2nwJT0JJNhG2nGL7r/xloz6pTSQNkUyybCH2KJ8Qg/EZcXoEy 2v2CqMkCauVujs5qmi43UUwOpTki60l4Imd94ZuWHquHhZ/OOs6SFS9TokLTeg4zN4bF Zbt8WPU5LU9UL1qpPliq8f6b3qq5rzljxBBtJM4kIHv4VKyHGrBtd71y7r1vmzzCCy10 imujCdAw6Uo2BFGaAXBKzvR/aRtBAvlxgE1dGDS/B32n9P01nj01P5Xcohpi7mLNN3mI GDD0dE7JzVgYNOvIgA0sIB084vGD3TSm3UD+lxnxV9otvm/c2LToYwYGPTMEEkkAI4cT Djxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r/9QwXldICsXiYuGReP63jHiFicVjmDMz2iVFLO9YmY=; b=Cszb5WXBQdPEeCoped21Vap3XCh2g5JKqiSwLROUjqjhQsRZhHmV3WXHLLoA5IjJbl +QPT6fpCIYVICi8MGgpGfHxVLUmBqADT1q0X6uLjmKUlePIQ5ihpIxigbvhQOMio1MkZ RsMZa4V/mWCLcYyjpFrGP0p3XrOzjIqWuJywxsuJ+dFvEsIk52pwjvDqu/SOlr2cupJ7 0NAnWIxaKx5AO0Z1Spg5q6B8KeJK0kApat4D5Xj7OC4fASTFRgO2cl7xk0Dum9g3Xz1L OI4Z7Ek0EmFdu53+E05rP+HcQ5KYcvix0LuOe7RE9IwaZEm0lw40F32F5vOidX36MbsS pxCQ== X-Gm-Message-State: AFqh2ko2vETc4NKJc2R5WRWLUa9rTwuyCvqCFdIRyhovzbwWYIvY7mtb DKbvlqx+FDWdBXYdMt3W2q2CHg== X-Google-Smtp-Source: AMrXdXtfenCMHUw12ghDU67jIS7EmiiHA1JSZZL3oQOKOZfFhVRVQJoHBLHICOUvT19gwvOAqnee5g== X-Received: by 2002:a05:6512:139c:b0:4b5:6ca8:255e with SMTP id p28-20020a056512139c00b004b56ca8255emr126000lfa.34.1671588333153; Tue, 20 Dec 2022 18:05:33 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:32 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno Subject: [PATCH v4 14/20] thermal/drivers/tsens: Drop single-cell code for msm8976/msm8956 Date: Wed, 21 Dec 2022 04:05:14 +0200 Message-Id: <20221221020520.1326964-15-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org There is no dtsi file for msm8976 in the kernel sources. Drop the compatibility with unofficial dtsi and remove support for handling the single-cell calibration data on msm8976. Cc: AngeloGioacchino Del Regno Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v1.c | 29 ++--------------------------- 1 file changed, 2 insertions(+), 27 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 6d1ea430f90b..b822a426066d 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -88,31 +88,6 @@ static int calibrate_v1(struct tsens_priv *priv) return 0; } -static int calibrate_8976(struct tsens_priv *priv) -{ - u32 p1[11], p2[11]; - u32 *qfprom_cdata; - int mode, ret; - - ret = tsens_calibrate_common(priv); - if (!ret) - return 0; - - qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); - if (IS_ERR(qfprom_cdata)) - return PTR_ERR(qfprom_cdata); - - mode = tsens_read_calibration_legacy(priv, &tsens_8976_nvmem, - p1, p2, - qfprom_cdata, NULL); - - - compute_intercept_slope(priv, p1, p2, mode); - kfree(qfprom_cdata); - - return 0; -} - /* v1.x: msm8956,8976,qcs404,405 */ static struct tsens_features tsens_v1_feat = { @@ -211,7 +186,7 @@ struct tsens_plat_data data_tsens_v1 = { static const struct tsens_ops ops_8956 = { .init = init_8956, - .calibrate = calibrate_8976, + .calibrate = tsens_calibrate_common, .get_temp = get_temp_tsens_valid, }; @@ -224,7 +199,7 @@ struct tsens_plat_data data_8956 = { static const struct tsens_ops ops_8976 = { .init = init_common, - .calibrate = calibrate_8976, + .calibrate = tsens_calibrate_common, .get_temp = get_temp_tsens_valid, }; From patchwork Wed Dec 21 02:05:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 636054 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB86EC3DA79 for ; Wed, 21 Dec 2022 02:05:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234078AbiLUCF4 (ORCPT ); Tue, 20 Dec 2022 21:05:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234401AbiLUCFj (ORCPT ); Tue, 20 Dec 2022 21:05:39 -0500 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9887D20370 for ; Tue, 20 Dec 2022 18:05:35 -0800 (PST) Received: by mail-lf1-x129.google.com with SMTP id f34so6161721lfv.10 for ; Tue, 20 Dec 2022 18:05:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3zoaVmWyJl4WNoN6Z+gsogU9AbrAG75c6CnFCXvJAOg=; b=HNt79aGd8Ymyw+kN/PpyE4yEiT8O2z38v8wEhSFiEheFyvBXDJLVOpi3EKnDeRtkEb w9+kajSq/y/LsJSl6o10IoO7WOrd4rUWl4fkhskF06SLVhi9QrfLHn0E3OuuPQ0QwPvP i1IFHo+VkQDIHnlZR40I6t0ogqi0yDNqONsahNxZg39ZlcZwEc7h1RNlT9I8hsNY/TJp CA1FLQYi+oXr/ceSdOf8gcJpMrr85afcht9VdZq81gyMKe/r9HLsr1AixCitEJZiO9y8 4+bujynPQfH+rmr3b9ih59t2yKH5j8ETFhbBUVDEXAnTx+RfAcu36Dgh/DJZsNqd7W49 PCNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3zoaVmWyJl4WNoN6Z+gsogU9AbrAG75c6CnFCXvJAOg=; b=OrTwa4D112TrBalEp+QyZPmygZfDk8b/RfnciTUCf7+hnmizL64kbtlOejgaNvDQJm GJpXXrssrL7792GYVGHQy6/NBwyVDBRrxw8jo2c+9nDFEZyKQISSe08Ow9Nnl4ztosjq ee23Wy8iUrQklsa2pmuuc+clHdg0lRJ6g/iEAb3/XQdByvR0G8DMA659cjwxVVjYM5vp +7A9PRrzVdltnsOvR/pLkE7Jg0WlG8LAlQN84XuGCSFfL12k791Z3TkyO7TqRsZAZdiP DP39u3qDLEY3rX8zll7PU9qik3ggyeffGVmwb3bhzQLDf7jQPLZPr1BigrSbkvCde3Li osXw== X-Gm-Message-State: AFqh2krrlVp4f9LGV8XCoITrHSdMpRZ/zcEnrk6KW8vyE57tIMi2n15R BllILlxIULljbtAANXCYqPCb4Q== X-Google-Smtp-Source: AMrXdXsIVWTlS43pziKjFPuxpA1NWDbx5qXkuKg3QHWMvTlPmagRIKRyKtOU4sgpN689GL+ffkb6kA== X-Received: by 2002:ac2:58e1:0:b0:4b5:4606:7ad9 with SMTP id v1-20020ac258e1000000b004b546067ad9mr1110738lfo.39.1671588333965; Tue, 20 Dec 2022 18:05:33 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:33 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 15/20] arm64: dts: qcom: msm8956: use SoC-specific compat for tsens Date: Wed, 21 Dec 2022 04:05:15 +0200 Message-Id: <20221221020520.1326964-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The slope values used during tsens calibration differ between msm8976 and msm8956 SoCs. Use SoC-specific compat value for the msm8956 SoC. Fixes: 0484d3ce0902 ("arm64: dts: qcom: Add DTS for MSM8976 and MSM8956 SoCs") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8956.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8956.dtsi b/arch/arm64/boot/dts/qcom/msm8956.dtsi index e432512d8716..668e05185c21 100644 --- a/arch/arm64/boot/dts/qcom/msm8956.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8956.dtsi @@ -12,6 +12,10 @@ &pmu { interrupts = ; }; +&tsens { + compatible = "qcom,msm8956-tsens", "qcom,tsens-v1"; +}; + /* * You might be wondering.. why is it so empty out there? * Well, the SoCs are almost identical. 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:34 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 16/20] arm64: dts: qcom: msm8916: specify per-sensor calibration cells Date: Wed, 21 Dec 2022 04:05:16 +0200 Message-Id: <20221221020520.1326964-17-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 81 +++++++++++++++++++++++++-- 1 file changed, 75 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 2ca8e977fc2a..a1b36f95f587 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -442,11 +442,68 @@ qfprom: qfprom@5c000 { reg = <0x0005c000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0xd0 0x8>; + + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 7>; + }; + + tsens_s0_p1: s0-p1@d0 { + reg = <0xd0 0x2>; + bits = <7 5>; + }; + + tsens_s0_p2: s0-p2@d1 { + reg = <0xd1 0x2>; + bits = <4 5>; + }; + + tsens_s1_p1: s1-p1@d2 { + reg = <0xd2 0x1>; + bits = <1 5>; + }; + tsens_s1_p2: s1-p2@d2 { + reg = <0xd2 0x2>; + bits = <6 5>; + }; + tsens_s2_p1: s2-p1@d3 { + reg = <0xd3 0x1>; + bits = <3 5>; + }; + + tsens_s2_p2: s2-p2@d4 { + reg = <0xd4 0x1>; + bits = <0 5>; }; - tsens_calsel: calsel@ec { - reg = <0xec 0x4>; + + tsens_s3_p1: s3-p1@d4 { + reg = <0xd4 0x2>; + bits = <5 5>; + }; + + tsens_s3_p2: s3-p2@d5 { + reg = <0xd5 0x1>; + bits = <2 5>; + }; + + tsens_s4_p1: s4-p1@d5 { + reg = <0xd5 0x2>; + bits = <7 5>; + }; + + tsens_s4_p2: s4-p2@d6 { + reg = <0xd6 0x2>; + bits = <4 5>; + }; + + tsens_base2: base2@d7 { + reg = <0xd7 0x1>; + bits = <1 7>; + }; + + tsens_mode: mode@ec { + reg = <0xef 0x1>; + bits = <5 3>; }; }; @@ -473,8 +530,20 @@ tsens: thermal-sensor@4a9000 { compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; reg = <0x004a9000 0x1000>, /* TM */ <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; - nvmem-cell-names = "calib", "calib_sel"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2"; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:35 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 17/20] arm64: dts: qcom: msm8976: specify per-sensor calibration cells Date: Wed, 21 Dec 2022 04:05:17 +0200 Message-Id: <20221221020520.1326964-18-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8976.dtsi | 153 +++++++++++++++++++++++++- 1 file changed, 149 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8976.dtsi b/arch/arm64/boot/dts/qcom/msm8976.dtsi index 05dcb30b0779..2d360d05aa5e 100644 --- a/arch/arm64/boot/dts/qcom/msm8976.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8976.dtsi @@ -481,8 +481,129 @@ qfprom: qfprom@a4000 { #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@218 { - reg = <0x218 0x18>; + tsens_base1: base1@218 { + reg = <0x218 1>; + bits = <0 8>; + }; + + tsens_s0_p1: s0-p1@219 { + reg = <0x219 0x1>; + bits = <0 6>; + }; + + tsens_s0_p2: s0-p2@219 { + reg = <0x219 0x2>; + bits = <6 6>; + }; + + tsens_s1_p1: s1-p1@21a { + reg = <0x21a 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@21b { + reg = <0x21b 0x1>; + bits = <2 6>; + }; + + tsens_s2_p1: s2-p1@21c { + reg = <0x21c 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2: s2-p2@21c { + reg = <0x21c 0x2>; + bits = <6 6>; + }; + + tsens_s3_p1: s3-p1@21d { + reg = <0x21d 0x2>; + bits = <4 6>; + }; + + tsens_s3_p2: s3-p2@21e { + reg = <0x21e 0x1>; + bits = <2 6>; + }; + + tsens_base2: base2@220 { + reg = <0x220 1>; + bits = <0 8>; + }; + + tsens_s4_p1: s4-p1@221 { + reg = <0x221 0x1>; + bits = <0 6>; + }; + + tsens_s4_p2: s4-p2@221 { + reg = <0x221 0x2>; + bits = <6 6>; + }; + + tsens_s5_p1: s5-p1@222 { + reg = <0x222 0x2>; + bits = <4 6>; + }; + + tsens_s5_p2: s5-p2@223 { + reg = <0x224 0x1>; + bits = <2 6>; + }; + + tsens_s6_p1: s6-p1@224 { + reg = <0x224 0x1>; + bits = <0 6>; + }; + + tsens_s6_p2: s6-p2@224 { + reg = <0x224 0x2>; + bits = <6 6>; + }; + + tsens_s7_p1: s7-p1@225 { + reg = <0x225 0x2>; + bits = <4 6>; + }; + + tsens_s7_p2: s7-p2@226 { + reg = <0x226 0x2>; + bits = <2 6>; + }; + + tsens_mode: mode@228 { + reg = <0x228 1>; + bits = <0 3>; + }; + + tsens_s8_p1: s8-p1@228 { + reg = <0x228 0x2>; + bits = <3 6>; + }; + + tsens_s8_p2: s8-p2@229 { + reg = <0x229 0x1>; + bits = <1 6>; + }; + + tsens_s9_p1: s9-p1@229 { + reg = <0x229 0x2>; + bits = <7 6>; + }; + + tsens_s9_p2: s9-p2@22a { + reg = <0x22a 0x2>; + bits = <5 6>; + }; + + tsens_s10_p1: s10-p1@22b { + reg = <0x22b 0x2>; + bits = <3 6>; + }; + + tsens_s10_p2: s10-p2@22c { + reg = <0x22c 0x1>; + bits = <1 6>; }; }; @@ -492,8 +613,32 @@ tsens: thermal-sensor@4a9000 { <0x004a8000 0x1000>; /* SROT */ interrupts = ; interrupt-names = "uplow"; - nvmem-cells = <&tsens_caldata>; - nvmem-cell-names = "calib"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2"; #qcom,sensors = <11>; #thermal-sensor-cells = <1>; }; From patchwork Wed Dec 21 02:05:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635678 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AB71C3DA7C for ; Wed, 21 Dec 2022 02:06:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230130AbiLUCF5 (ORCPT ); Tue, 20 Dec 2022 21:05:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234412AbiLUCFk (ORCPT ); Tue, 20 Dec 2022 21:05:40 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0361C1F9F6 for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:36 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 18/20] arm64: dts: qcom: qcs404: specify per-sensor calibration cells Date: Wed, 21 Dec 2022 04:05:18 +0200 Message-Id: <20221221020520.1326964-19-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 145 ++++++++++++++++++++++++++- 1 file changed, 140 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index a5324eecb50a..84ff9df2b904 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -366,13 +366,126 @@ qfprom: qfprom@a4000 { reg = <0x000a4000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0x1f8 0x14>; - }; cpr_efuse_speedbin: speedbin@13c { reg = <0x13c 0x4>; bits = <2 3>; }; + + tsens_s0_p1: s0-p1@1f8 { + reg = <0x1f8 0x1>; + bits = <0 6>; + }; + + tsens_s0_p2: s0-p2@1f8 { + reg = <0x1f8 0x2>; + bits = <6 6>; + }; + + tsens_s1_p1: s1-p1@1f9 { + reg = <0x1f9 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@1fa { + reg = <0x1fa 0x1>; + bits = <2 6>; + }; + + tsens_s2_p1: s2-p1@1fb { + reg = <0x1fb 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2: s2-p2@1fb { + reg = <0x1fb 0x2>; + bits = <6 6>; + }; + + tsens_s3_p1: s3-p1@1fc { + reg = <0x1fc 0x2>; + bits = <4 6>; + }; + + tsens_s3_p2: s3-p2@1fd { + reg = <0x1fd 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1: s4-p1@1fe { + reg = <0x1fe 0x1>; + bits = <0 6>; + }; + + tsens_s4_p2: s4-p2@1fe { + reg = <0x1fe 0x2>; + bits = <6 6>; + }; + + tsens_s5_p1: s5-p1@200 { + reg = <0x200 0x1>; + bits = <0 6>; + }; + + tsens_s5_p2: s5-p2@200 { + reg = <0x200 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@201 { + reg = <0x201 0x2>; + bits = <4 6>; + }; + + tsens_s6_p2: s6-p2@202 { + reg = <0x202 0x1>; + bits = <2 6>; + }; + + tsens_s7_p1: s7-p1@203 { + reg = <0x203 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@203 { + reg = <0x203 0x2>; + bits = <6 6>; + }; + + tsens_s8_p1: s8-p1@204 { + reg = <0x204 0x2>; + bits = <4 6>; + }; + + tsens_s8_p2: s8-p2@205 { + reg = <0x205 0x1>; + bits = <2 6>; + }; + + tsens_s9_p1: s9-p1@206 { + reg = <0x206 0x1>; + bits = <0 6>; + }; + + tsens_s9_p2: s9-p2@206 { + reg = <0x206 0x2>; + bits = <6 6>; + }; + + tsens_mode: mode@208 { + reg = <0x208 1>; + bits = <0 3>; + }; + + tsens_base1: base1@208 { + reg = <0x208 2>; + bits = <3 8>; + }; + + tsens_base2: base2@208 { + reg = <0x209 2>; + bits = <3 8>; + }; + cpr_efuse_quot_offset1: qoffset1@231 { reg = <0x231 0x4>; bits = <4 7>; @@ -447,8 +560,30 @@ tsens: thermal-sensor@4a9000 { compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; reg = <0x004a9000 0x1000>, /* TM */ <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>; - nvmem-cell-names = "calib"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2"; #qcom,sensors = <10>; interrupts = ; interrupt-names = "uplow"; From patchwork Wed Dec 21 02:05:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 636053 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5452C4167B for ; Wed, 21 Dec 2022 02:06:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234323AbiLUCF7 (ORCPT ); Tue, 20 Dec 2022 21:05:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53416 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234416AbiLUCFm (ORCPT ); Tue, 20 Dec 2022 21:05:42 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 043D9205C3 for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:37 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 19/20] ARM: dts: qcom-msm8974: specify per-sensor calibration cells Date: Wed, 21 Dec 2022 04:05:19 +0200 Message-Id: <20221221020520.1326964-20-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-msm8974.dtsi | 313 +++++++++++++++++++++++++++- 1 file changed, 307 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 8d216a3c0851..4d3df70e6158 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1119,8 +1119,60 @@ tsens: thermal-sensor@fc4a9000 { compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; reg = <0xfc4a9000 0x1000>, /* TM */ <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>, + <&tsens_use_backup>, + <&tsens_mode_backup>, + <&tsens_base1_backup>, <&tsens_base2_backup>, + <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, + <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, + <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, + <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, + <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, + <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, + <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, + <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, + <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, + <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, + <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2", + "use_backup", + "mode_backup", + "base1_backup", "base2_backup", + "s0_p1_backup", "s0_p2_backup", + "s1_p1_backup", "s1_p2_backup", + "s2_p1_backup", "s2_p2_backup", + "s3_p1_backup", "s3_p2_backup", + "s4_p1_backup", "s4_p2_backup", + "s5_p1_backup", "s5_p2_backup", + "s6_p1_backup", "s6_p2_backup", + "s7_p1_backup", "s7_p2_backup", + "s8_p1_backup", "s8_p2_backup", + "s9_p1_backup", "s9_p2_backup", + "s10_p1_backup", "s10_p2_backup"; #qcom,sensors = <11>; interrupts = ; interrupt-names = "uplow"; @@ -1137,11 +1189,260 @@ qfprom: qfprom@fc4bc000 { reg = <0xfc4bc000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_calib: calib@d0 { - reg = <0xd0 0x18>; + + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1: s0-p1@d1 { + reg = <0xd1 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1: s1-p1@d2 { + reg = <0xd1 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1: s2-p1@d2 { + reg = <0xd2 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1: s3-p1@d3 { + reg = <0xd3 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1: s4-p1@d4 { + reg = <0xd4 0x1>; + bits = <0 6>; + }; + + tsens_s5_p1: s5-p1@d4 { + reg = <0xd4 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@d5 { + reg = <0xd5 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1: s7-p1@d6 { + reg = <0xd6 0x1>; + bits = <2 6>; + }; + + tsens_s8_p1: s8-p1@d7 { + reg = <0xd7 0x1>; + bits = <0 6>; + }; + + tsens_mode: mode@d7 { + reg = <0xd7 0x1>; + bits = <6 2>; + }; + + tsens_s9_p1: s9-p1@d8 { + reg = <0xd8 0x1>; + bits = <0 6>; + }; + + tsens_s10_p1: s10_p1@d8 { + reg = <0xd8 0x2>; + bits = <6 6>; + }; + + tsens_base2: base2@d9 { + reg = <0xd9 0x2>; + bits = <4 8>; + }; + + tsens_s0_p2: s0-p2@da { + reg = <0xda 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@db { + reg = <0xdb 0x1>; + bits = <2 6>; + }; + + tsens_s2_p2: s2-p2@dc { + reg = <0xdc 0x1>; + bits = <0 6>; + }; + + tsens_s3_p2: s3-p2@dc { + reg = <0xdc 0x2>; + bits = <6 6>; + }; + + tsens_s4_p2: s4-p2@dd { + reg = <0xdd 0x2>; + bits = <4 6>; + }; + + tsens_s5_p2: s5-p2@de { + reg = <0xde 0x2>; + bits = <2 6>; + }; + + tsens_s6_p2: s6-p2@df { + reg = <0xdf 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@e0 { + reg = <0xe0 0x1>; + bits = <0 6>; + }; + + tsens_s8_p2: s8-p2@e0 { + reg = <0xe0 0x2>; + bits = <6 6>; + }; + + tsens_s9_p2: s9-p2@e1 { + reg = <0xe1 0x2>; + bits = <4 6>; + }; + + tsens_s10_p2: s10_p2@e2 { + reg = <0xe2 0x2>; + bits = <2 6>; + }; + + tsens_s5_p2_backup: s5-p2_backup@e3 { + reg = <0xe3 0x2>; + bits = <0 6>; + }; + + tsens_mode_backup: mode_backup@e3 { + reg = <0xe3 0x1>; + bits = <6 2>; + }; + + tsens_s6_p2_backup: s6-p2_backup@e4 { + reg = <0xe4 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2_backup: s7-p2_backup@e4 { + reg = <0xe4 0x2>; + bits = <6 6>; + }; + + tsens_s8_p2_backup: s8-p2_backup@e5 { + reg = <0xe5 0x2>; + bits = <4 6>; + }; + + tsens_s9_p2_backup: s9-p2_backup@e6 { + reg = <0xe6 0x2>; + bits = <2 6>; + }; + + tsens_s10_p2_backup: s10_p2_backup@e7 { + reg = <0xe7 0x1>; + bits = <0 6>; + }; + + tsens_base1_backup: base1_backup@440 { + reg = <0x440 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1_backup: s0-p1_backup@441 { + reg = <0x441 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1_backup: s1-p1_backup@442 { + reg = <0x441 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1_backup: s2-p1_backup@442 { + reg = <0x442 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1_backup: s3-p1_backup@443 { + reg = <0x443 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1_backup: s4-p1_backup@444 { + reg = <0x444 0x1>; + bits = <0 6>; }; - tsens_backup: backup@440 { - reg = <0x440 0x10>; + + tsens_s5_p1_backup: s5-p1_backup@444 { + reg = <0x444 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1_backup: s6-p1_backup@445 { + reg = <0x445 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1_backup: s7-p1_backup@446 { + reg = <0x446 0x1>; + bits = <2 6>; + }; + + tsens_use_backup: use_backup@447 { + reg = <0x447 0x1>; + bits = <5 3>; + }; + + tsens_s8_p1_backup: s8-p1_backup@448 { + reg = <0x448 0x1>; + bits = <0 6>; + }; + + tsens_s9_p1_backup: s9-p1_backup@448 { + reg = <0x448 0x2>; + bits = <6 6>; + }; + + tsens_s10_p1_backup: s10_p1_backup@449 { + reg = <0x449 0x2>; + bits = <4 6>; + }; + + tsens_base2_backup: base2_backup@44a { + reg = <0x44a 0x2>; + bits = <2 8>; + }; + + tsens_s0_p2_backup: s0-p2_backup@44b { + reg = <0x44b 0x3>; + bits = <2 6>; + }; + + tsens_s1_p2_backup: s1-p2_backup@44c { + reg = <0x44c 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2_backup: s2-p2_backup@44c { + reg = <0x44c 0x2>; + bits = <6 6>; + }; + + tsens_s3_p2_backup: s3-p2_backup@44d { + reg = <0x44d 0x2>; + bits = <4 6>; + }; + + tsens_s4_p2_backup: s4-p2_backup@44e { + reg = <0x44e 0x1>; + bits = <2 6>; }; }; From patchwork Wed Dec 21 02:05:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1A5E5C4167B for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id q18-20020a056512211200b004b257fef958sm1673048lfr.94.2022.12.20.18.05.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Dec 2022 18:05:37 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: "Bryan O'Donoghue" , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v4 20/20] ARM: dts: qcom-apq8084: specify per-sensor calibration cells Date: Wed, 21 Dec 2022 04:05:20 +0200 Message-Id: <20221221020520.1326964-21-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> References: <20221221020520.1326964-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8084.dtsi | 313 +++++++++++++++++++++++++++- 1 file changed, 307 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index fe30abfff90a..22e56ee82a20 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -249,11 +249,260 @@ qfprom: qfprom@fc4bc000 { reg = <0xfc4bc000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_calib: calib@d0 { - reg = <0xd0 0x18>; + + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1: s0-p1@d1 { + reg = <0xd1 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1: s1-p1@d2 { + reg = <0xd1 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1: s2-p1@d2 { + reg = <0xd2 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1: s3-p1@d3 { + reg = <0xd3 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1: s4-p1@d4 { + reg = <0xd4 0x1>; + bits = <0 6>; + }; + + tsens_s5_p1: s5-p1@d4 { + reg = <0xd4 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@d5 { + reg = <0xd5 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1: s7-p1@d6 { + reg = <0xd6 0x1>; + bits = <2 6>; + }; + + tsens_s8_p1: s8-p1@d7 { + reg = <0xd7 0x1>; + bits = <0 6>; + }; + + tsens_mode: mode@d7 { + reg = <0xd7 0x1>; + bits = <6 2>; + }; + + tsens_s9_p1: s9-p1@d8 { + reg = <0xd8 0x1>; + bits = <0 6>; + }; + + tsens_s10_p1: s10_p1@d8 { + reg = <0xd8 0x2>; + bits = <6 6>; + }; + + tsens_base2: base2@d9 { + reg = <0xd9 0x2>; + bits = <4 8>; + }; + + tsens_s0_p2: s0-p2@da { + reg = <0xda 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@db { + reg = <0xdb 0x1>; + bits = <2 6>; + }; + + tsens_s2_p2: s2-p2@dc { + reg = <0xdc 0x1>; + bits = <0 6>; + }; + + tsens_s3_p2: s3-p2@dc { + reg = <0xdc 0x2>; + bits = <6 6>; + }; + + tsens_s4_p2: s4-p2@dd { + reg = <0xdd 0x2>; + bits = <4 6>; + }; + + tsens_s5_p2: s5-p2@de { + reg = <0xde 0x2>; + bits = <2 6>; + }; + + tsens_s6_p2: s6-p2@df { + reg = <0xdf 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@e0 { + reg = <0xe0 0x1>; + bits = <0 6>; + }; + + tsens_s8_p2: s8-p2@e0 { + reg = <0xe0 0x2>; + bits = <6 6>; + }; + + tsens_s9_p2: s9-p2@e1 { + reg = <0xe1 0x2>; + bits = <4 6>; + }; + + tsens_s10_p2: s10_p2@e2 { + reg = <0xe2 0x2>; + bits = <2 6>; + }; + + tsens_s5_p2_backup: s5-p2_backup@e3 { + reg = <0xe3 0x2>; + bits = <0 6>; + }; + + tsens_mode_backup: mode_backup@e3 { + reg = <0xe3 0x1>; + bits = <6 2>; + }; + + tsens_s6_p2_backup: s6-p2_backup@e4 { + reg = <0xe4 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2_backup: s7-p2_backup@e4 { + reg = <0xe4 0x2>; + bits = <6 6>; + }; + + tsens_s8_p2_backup: s8-p2_backup@e5 { + reg = <0xe5 0x2>; + bits = <4 6>; + }; + + tsens_s9_p2_backup: s9-p2_backup@e6 { + reg = <0xe6 0x2>; + bits = <2 6>; + }; + + tsens_s10_p2_backup: s10_p2_backup@e7 { + reg = <0xe7 0x1>; + bits = <0 6>; + }; + + tsens_base1_backup: base1_backup@440 { + reg = <0x440 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1_backup: s0-p1_backup@441 { + reg = <0x441 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1_backup: s1-p1_backup@442 { + reg = <0x441 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1_backup: s2-p1_backup@442 { + reg = <0x442 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1_backup: s3-p1_backup@443 { + reg = <0x443 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1_backup: s4-p1_backup@444 { + reg = <0x444 0x1>; + bits = <0 6>; }; - tsens_backup: backup@440 { - reg = <0x440 0x10>; + + tsens_s5_p1_backup: s5-p1_backup@444 { + reg = <0x444 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1_backup: s6-p1_backup@445 { + reg = <0x445 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1_backup: s7-p1_backup@446 { + reg = <0x446 0x1>; + bits = <2 6>; + }; + + tsens_use_backup: use_backup@447 { + reg = <0x447 0x1>; + bits = <5 3>; + }; + + tsens_s8_p1_backup: s8-p1_backup@448 { + reg = <0x448 0x1>; + bits = <0 6>; + }; + + tsens_s9_p1_backup: s9-p1_backup@448 { + reg = <0x448 0x2>; + bits = <6 6>; + }; + + tsens_s10_p1_backup: s10_p1_backup@449 { + reg = <0x449 0x2>; + bits = <4 6>; + }; + + tsens_base2_backup: base2_backup@44a { + reg = <0x44a 0x2>; + bits = <2 8>; + }; + + tsens_s0_p2_backup: s0-p2_backup@44b { + reg = <0x44b 0x3>; + bits = <2 6>; + }; + + tsens_s1_p2_backup: s1-p2_backup@44c { + reg = <0x44c 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2_backup: s2-p2_backup@44c { + reg = <0x44c 0x2>; + bits = <6 6>; + }; + + tsens_s3_p2_backup: s3-p2_backup@44d { + reg = <0x44d 0x2>; + bits = <4 6>; + }; + + tsens_s4_p2_backup: s4-p2_backup@44e { + reg = <0x44e 0x1>; + bits = <2 6>; }; }; @@ -261,8 +510,60 @@ tsens: thermal-sensor@fc4a8000 { compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; reg = <0xfc4a9000 0x1000>, /* TM */ <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>, + <&tsens_use_backup>, + <&tsens_mode_backup>, + <&tsens_base1_backup>, <&tsens_base2_backup>, + <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, + <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, + <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, + <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, + <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, + <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, + <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, + <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, + <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, + <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, + <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2", + "use_backup", + "mode_backup", + "base1_backup", "base2_backup", + "s0_p1_backup", "s0_p2_backup", + "s1_p1_backup", "s1_p2_backup", + "s2_p1_backup", "s2_p2_backup", + "s3_p1_backup", "s3_p2_backup", + "s4_p1_backup", "s4_p2_backup", + "s5_p1_backup", "s5_p2_backup", + "s6_p1_backup", "s6_p2_backup", + "s7_p1_backup", "s7_p2_backup", + "s8_p1_backup", "s8_p2_backup", + "s9_p1_backup", "s9_p2_backup", + "s10_p1_backup", "s10_p2_backup"; #qcom,sensors = <11>; interrupts = ; interrupt-names = "uplow";