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Wed, 21 Dec 2022 14:40:36 -0800 (PST) Received: from toolbox.alistair23.me (unknown [10.225.167.8]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4NcpLV6v6wz1RvTp; Wed, 21 Dec 2022 14:40:34 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , LIU Zhiwei , Alistair Francis Subject: [PULL v2 04/45] tcg/riscv: Fix range matched by TCG_CT_CONST_M12 Date: Thu, 22 Dec 2022 08:39:41 +1000 Message-Id: <20221221224022.425831-5-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221224022.425831-1-alistair.francis@opensource.wdc.com> References: <20221221224022.425831-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=3472792e2=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson We were matching a signed 13-bit range, not a 12-bit range. Expand the commentary within the function and be explicit about all of the ranges. Reported-by: LIU Zhiwei Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-Id: <20221022095821.2441874-1-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- tcg/riscv/tcg-target.c.inc | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 81a83e45b1..191197853f 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -154,13 +154,26 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct) if ((ct & TCG_CT_CONST_ZERO) && val == 0) { return 1; } - if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { + /* + * Sign extended from 12 bits: [-0x800, 0x7ff]. + * Used for most arithmetic, as this is the isa field. + */ + if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) { return 1; } - if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) { + /* + * Sign extended from 12 bits, negated: [-0x7ff, 0x800]. + * Used for subtraction, where a constant must be handled by ADDI. + */ + if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) { return 1; } - if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) { + /* + * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff]. + * Used by addsub2, which may need the negative operation, + * and requires the modified constant to be representable. + */ + if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) { return 1; } return 0; From patchwork Wed Dec 21 22:39:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 635644 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp3781343pvb; Wed, 21 Dec 2022 14:49:25 -0800 (PST) X-Google-Smtp-Source: AMrXdXvZOY6x7FBPJSIwu5OcmTDt/eOFCPvHf8o6z3UMEXLes6YXnu9X74ZBez87nBVlo7ElmDQI X-Received: by 2002:a05:6214:5490:b0:4c7:26a4:908e with SMTP id lg16-20020a056214549000b004c726a4908emr4634028qvb.47.1671662965833; Wed, 21 Dec 2022 14:49:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671662965; cv=none; d=google.com; s=arc-20160816; b=IENsj1Mw5W1LJZ83zqYPZYfA4EwMiYSEp/DeU12KY8mPteG2ANICcL4VV9+bl6krdn rqvBP5bpI72OaNiBLchX0umH0pCLgore7jGrCBvdL43TVueZuNnPeUOx/G7n996x54k3 iYHrQzjl0jrXFvxPnT8iUK8ap9dne5ggdvTaM/5xq95K3kKgCxlxpQEF1EU2kGPE9D78 lsHzHcgZEcCknAEGcP6jeJsn7ONJv9gzH71FvlT2SLSA1gUqyuRGpSJQPpT3RMmXItdA dn+cpYewQyAgHG7VZYrFRUJVfWwZw25K+l5mzalA7Cy3ZxUN4voVzfkFuw+9oX6kjecu 4Y7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:wdcironportexception:ironport-sdr:ironport-sdr :dkim-signature; bh=DId2IK/2+8BZnCTJYolomatmHCIWF7rnT1qVyL6Lehc=; b=vjkCn+/gfneZCAPaDczMsDpD/d7I2sT/4yc93FASJmoBA3eIn6/0tSws0c8mfm1wHw ReJv3A6DjvNOIHSqcMF7ziWzfB/0L27GoZQHrmaTukdbxUOxWOduOoruDjGCIh3YnXcU knifydUF7BJk2HvHhzQeqFoYKDgz+pt7tgH0Tn7U9pS+98zj+MBzDM6HqKx+X24f3FGv VNjLYp5FDo7fILJe9Ab0ETvsW3IxELvBXf9AWEEzb9BTSxwp2T/NRAaeIAknEBdzm88j lWKMdr30ptklpTwynDHndvEJsAvQnKcCfsblPMoOS96w6HGj1EGbbUiz7yJbQihwqPY9 bC6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=hxfiUtfp; dkim=pass header.i=@opensource.wdc.com header.s=dkim header.b=aoMbUVws; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Wed, 21 Dec 2022 14:40:39 -0800 (PST) Received: from toolbox.alistair23.me (unknown [10.225.167.8]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4NcpLY15CFz1Rwt8; Wed, 21 Dec 2022 14:40:36 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , LIU Zhiwei , Alistair Francis Subject: [PULL v2 05/45] tcg/riscv: Fix reg overlap case in tcg_out_addsub2 Date: Thu, 22 Dec 2022 08:39:42 +1000 Message-Id: <20221221224022.425831-6-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221224022.425831-1-alistair.francis@opensource.wdc.com> References: <20221221224022.425831-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=3472792e2=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson There was a typo using opc_addi instead of opc_add with the two registers. While we're at it, simplify the gating test to al == bl to improve dynamic scheduling even when the output register does not overlap the inputs. Reported-by: LIU Zhiwei Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20221020233836.2341671-1-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- tcg/riscv/tcg-target.c.inc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 191197853f..2a84c57bec 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -700,9 +700,15 @@ static void tcg_out_addsub2(TCGContext *s, if (cbl) { tcg_out_opc_imm(s, opc_addi, rl, al, bl); tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl); - } else if (rl == al && rl == bl) { + } else if (al == bl) { + /* + * If the input regs overlap, this is a simple doubling + * and carry-out is the input msb. This special case is + * required when the output reg overlaps the input, + * but we might as well use it always. + */ tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0); - tcg_out_opc_reg(s, opc_addi, rl, al, bl); + tcg_out_opc_reg(s, opc_add, rl, al, al); } else { tcg_out_opc_reg(s, opc_add, rl, al, bl); tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, From patchwork Wed Dec 21 22:39:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 635642 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp3778872pvb; Wed, 21 Dec 2022 14:41:57 -0800 (PST) X-Google-Smtp-Source: AMrXdXuCMqaZS+/TjObkT7JsktB9ZwKjEifMvappDU7nOeh+NpkXwan5iEq+5J6LVj/SeosSW3cm X-Received: by 2002:ad4:5589:0:b0:4c7:9e7d:83d8 with SMTP id f9-20020ad45589000000b004c79e7d83d8mr20403682qvx.1.1671662516993; Wed, 21 Dec 2022 14:41:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671662516; cv=none; d=google.com; s=arc-20160816; b=08MHrsoWV+mKV1ZgIBl42cItqvJVHazeBYW+vPpPHoaCmJmgMe9AEPf0loOTHKg+3/ HMb29+XgUijc00HYdfFJ/KcJzveKmBQTw2idz0Dd9sSSixDz+2BWIOgiSlR6zK6yc3J1 ivx+XAUBKHqLhI/wLapK6KQYqNJ59Huzwxf0Cz2wTgMmuUwbjC4MrBuGq0Ok5fFg//3p uZbNDTox9TCgqGeY+IkdC3RUOwIoOC3M5ZB6HSgFFVs4xXCQLKiux4T5W9ezeZXPJnGJ 7aB3p4pWNWwaExcd+w6sLdUU629wKAQFec5/iNxjjTHl8IeDxMfWjvMUxVmpkWDyftdH w+tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:wdcironportexception:ironport-sdr:ironport-sdr :dkim-signature; bh=D5RY5Kk/nceV1oQAkjPdC/yhgl/phDrK6jPMk3pLOYI=; b=VpDIMCJs2L5lBKpVxyB4Njv34qPIuHNMLj6MDH5b+D0zbknu+Doq8bijgCVZzkSGik h+2BIPSTL8252U+l0WqIpQm2iw0DbCRV5Xb5YF9ao9f1U5WVqGzWLPpYM8NOkzzc0f9U SE1rVPcKE2PyTXwsv0s/m67BYOcypZFZVhnP4V3JlcxPjfss12nfRORumliT4crpIenZ auoao2nBlfAP5xoO9eulLWZP0YaZ2ALEq3W9AWjl59jWPgTjKyWQVtQpdEv+DvDDbLtr ZKbP31XXOur1BdahkI01Sw9y3G5SJ1uOZL+TgKqJFp15IZwZXSnHfNHQnO0ozbuRy+C5 d/0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=F8EXDoUf; dkim=pass header.i=@opensource.wdc.com header.s=dkim header.b="TqcX/z1w"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Wed, 21 Dec 2022 14:40:41 -0800 (PST) Received: from toolbox.alistair23.me (unknown [10.225.167.8]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4NcpLb3MF3z1Rwrq; Wed, 21 Dec 2022 14:40:39 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , LIU Zhiwei , Alistair Francis Subject: [PULL v2 06/45] tcg/riscv: Fix base register for user-only qemu_ld/st Date: Thu, 22 Dec 2022 08:39:43 +1000 Message-Id: <20221221224022.425831-7-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221224022.425831-1-alistair.francis@opensource.wdc.com> References: <20221221224022.425831-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=3472792e2=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson When guest_base != 0, we were not coordinating the usage of TCG_REG_TMP0 as base properly, leading to a previous zero-extend of the input address being discarded. Shuffle the alignment check to the front, because that does not depend on the zero-extend, and it keeps the register usage clear. Set base after each step of the address arithmetic instead of before. Return the base register used from tcg_out_tlb_load, so as to keep that register choice localized to that function. Reported-by: LIU Zhiwei Signed-off-by: Richard Henderson Reviewed-by: LIU Zhiwei Reviewed-by: Alistair Francis Message-Id: <20221023233337.2846860-1-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- tcg/riscv/tcg-target.c.inc | 39 +++++++++++++++++++++----------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 2a84c57bec..e3b608034f 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -923,9 +923,9 @@ static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) tcg_debug_assert(ok); } -static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, - TCGReg addrh, MemOpIdx oi, - tcg_insn_unit **label_ptr, bool is_load) +static TCGReg tcg_out_tlb_load(TCGContext *s, TCGReg addrl, + TCGReg addrh, MemOpIdx oi, + tcg_insn_unit **label_ptr, bool is_load) { MemOp opc = get_memop(oi); unsigned s_bits = opc & MO_SIZE; @@ -975,6 +975,7 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, addrl = TCG_REG_TMP0; } tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); + return TCG_REG_TMP0; } static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, @@ -1177,7 +1178,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) #else unsigned a_bits; #endif - TCGReg base = TCG_REG_TMP0; + TCGReg base; data_regl = *args++; data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); @@ -1187,23 +1188,25 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); + base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); add_qemu_ldst_label(s, 1, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl = base; - } a_bits = get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, true, addr_regl, a_bits); } + base = addr_regl; + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP0, base); + base = TCG_REG_TMP0; + } if (guest_base != 0) { - tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base); + base = TCG_REG_TMP0; } tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); #endif @@ -1249,7 +1252,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) #else unsigned a_bits; #endif - TCGReg base = TCG_REG_TMP0; + TCGReg base; data_regl = *args++; data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); @@ -1259,23 +1262,25 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) opc = get_memop(oi); #if defined(CONFIG_SOFTMMU) - tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); + base = tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); add_qemu_ldst_label(s, 0, oi, (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addr_regl); - addr_regl = base; - } a_bits = get_alignment_bits(opc); if (a_bits) { tcg_out_test_alignment(s, false, addr_regl, a_bits); } + base = addr_regl; + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP0, base); + base = TCG_REG_TMP0; + } if (guest_base != 0) { - tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_GUEST_BASE_REG, base); + base = TCG_REG_TMP0; } tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); #endif From patchwork Wed Dec 21 22:40:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 635645 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp3783867pvb; Wed, 21 Dec 2022 14:57:44 -0800 (PST) X-Google-Smtp-Source: AMrXdXvPohETc0ONlcwlw/r63rl6yYJCUKzxqrDMoOUvrlfxrtgKIsznzdKgUsO5/4lgtFYnmO1I X-Received: by 2002:a0c:fb51:0:b0:4c7:76ab:fbea with SMTP id b17-20020a0cfb51000000b004c776abfbeamr5027452qvq.29.1671663464275; Wed, 21 Dec 2022 14:57:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671663464; cv=none; d=google.com; s=arc-20160816; b=jLvwCCj6z0unBBOtNk7aCYwYFnFuu7j9P8g87UtfCoMZDV4Uubtzmmsa0rp3t6vhq/ 2HxtzDQmM+CohuFUFV2E7NgS5ofQTs9xzdg5r82alDyBdlgBccW32orvUcjbjKe1BaOa wlzd2OUgMu5uP1+Z5BLRJjJol90i8FI/5iDLtdg8GuCJgfBE9iMzPVxLz6c+FtzMjmb0 pCcs+9NUD44VqMusHbn1eOInapEANNz3wOMHChBTOCACy5t24EwUXwvTagBEf7jBErK8 JTGONp/gH2N9i3vzyorYiK6ZZ0Qq6Yqh3ccaWTCyXite7UtLCoKwCnaMsaa6cpvjSKu2 V5qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:wdcironportexception:ironport-sdr:ironport-sdr :dkim-signature; bh=vCP+5n6RNzgYDDT+HIzNLFYMHJyEXrbn+ZdZfZ9KKjo=; b=XtDrgTP/BdwAQEb2/sRKfA8Sg/uPil4pPSoy8q8RxlZ3SMMjFEkMmvRBCcHZncSVDM hnSXSNKkXK+hwns6dA9kFbVK/2gUC5eBqHgDLFcM7BBipdsJqHXmUt3HZcf/TCtE1dU7 8LmQfak9I64DV0HtWEA2CeLEZRCgjtgbfaGSFVnQDNkxTGHzZk1vgGuTvU8QMpbU8sMC oFnHlPQ0EdfRTu/MDNTecqLcxx+pAlG+zR1WeiRLzcF+//GUscfkh7ZboSvqU6HKL7O3 NyZ8ydKnaWaWmF66Y8pxKYZtqSr2UN4LjDNm4KKygMrt16qdZOeoKs+HwqfqOOzBFzg+ NPKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@wdc.com header.s=dkim.wdc.com header.b=cWRgrhM+; dkim=pass header.i=@opensource.wdc.com header.s=dkim header.b=YxrwVgXC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Wed, 21 Dec 2022 14:41:23 -0800 (PST) Received: from toolbox.alistair23.me (unknown [10.225.167.8]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4NcpMP2vCRz1RvLy; Wed, 21 Dec 2022 14:41:21 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , qemu-stable@nongnu.org, Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL v2 26/45] target/riscv: Set pc_succ_insn for !rvc illegal insn Date: Thu, 22 Dec 2022 08:40:03 +1000 Message-Id: <20221221224022.425831-27-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221221224022.425831-1-alistair.francis@opensource.wdc.com> References: <20221221224022.425831-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=3472792e2=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Failure to set pc_succ_insn may result in a TB covering zero bytes, which triggers an assert within the code generator. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1224 Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20221203175744.151365-1-richard.henderson@linaro.org> [ Changes by AF: - Add missing run-plugin-test-noc-% line ] Signed-off-by: Alistair Francis --- target/riscv/translate.c | 12 ++++-------- tests/tcg/Makefile.target | 2 ++ tests/tcg/riscv64/Makefile.target | 6 ++++++ tests/tcg/riscv64/test-noc.S | 32 +++++++++++++++++++++++++++++++ 4 files changed, 44 insertions(+), 8 deletions(-) create mode 100644 tests/tcg/riscv64/test-noc.S diff --git a/target/riscv/translate.c b/target/riscv/translate.c index cd5eb25ee8..160aefc3df 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1096,14 +1096,10 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) ctx->virt_inst_excp = false; /* Check for compressed insn */ if (insn_len(opcode) == 2) { - if (!has_ext(ctx, RVC)) { - gen_exception_illegal(ctx); - } else { - ctx->opcode = opcode; - ctx->pc_succ_insn = ctx->base.pc_next + 2; - if (decode_insn16(ctx, opcode)) { - return; - } + ctx->opcode = opcode; + ctx->pc_succ_insn = ctx->base.pc_next + 2; + if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) { + return; } } else { uint32_t opcode32 = opcode; diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target index 75257f2b29..14bc013181 100644 --- a/tests/tcg/Makefile.target +++ b/tests/tcg/Makefile.target @@ -117,6 +117,8 @@ endif %: %.c $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) +%: %.S + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) else # For softmmu targets we include a different Makefile fragement as the # build options for bare programs are usually pretty different. They diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target index b5b89dfb0e..cc3ed65ffd 100644 --- a/tests/tcg/riscv64/Makefile.target +++ b/tests/tcg/riscv64/Makefile.target @@ -4,3 +4,9 @@ VPATH += $(SRC_PATH)/tests/tcg/riscv64 TESTS += test-div TESTS += noexec + +# Disable compressed instructions for test-noc +TESTS += test-noc +test-noc: LDFLAGS = -nostdlib -static +run-test-noc: QEMU_OPTS += -cpu rv64,c=false +run-plugin-test-noc-%: QEMU_OPTS += -cpu rv64,c=false diff --git a/tests/tcg/riscv64/test-noc.S b/tests/tcg/riscv64/test-noc.S new file mode 100644 index 0000000000..e29d60c8b3 --- /dev/null +++ b/tests/tcg/riscv64/test-noc.S @@ -0,0 +1,32 @@ +#include + + .text + .globl _start +_start: + .option norvc + li a0, 4 /* SIGILL */ + la a1, sa + li a2, 0 + li a3, 8 + li a7, __NR_rt_sigaction + scall + + .option rvc + li a0, 1 + j exit + .option norvc + +pass: + li a0, 0 +exit: + li a7, __NR_exit + scall + + .data + /* struct kernel_sigaction sa = { .sa_handler = pass }; */ + .type sa, @object + .size sa, 32 +sa: + .dword pass + .zero 24 +