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[92.224.51.61]) by smtp.gmail.com with ESMTPSA id n14-20020aa7db4e000000b0047466e46662sm7204019edt.39.2022.12.21.09.00.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 09:00:45 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Richard Henderson , Igor Mammedov , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , qemu-block@nongnu.org, =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Jiaxun Yang , Ani Sinha , John Snow , Gerd Hoffmann , "Michael S. Tsirkin" , Eduardo Habkost , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Marcel Apfelbaum Subject: [PATCH v4 01/30] hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition Date: Wed, 21 Dec 2022 17:59:34 +0100 Message-Id: <20221221170003.2929-2-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221221170003.2929-1-shentey@gmail.com> References: <20221221170003.2929-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=shentey@gmail.com; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé The PIIX4 PCI-ISA bridge function is always located at 10:0. Since we want to re-use its address, add the PIIX4_PCI_DEVFN definition. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221027204720.33611-2-philmd@linaro.org> --- hw/mips/malta.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index e435f80973..2e175741ff 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -72,6 +72,8 @@ #define FLASH_SIZE 0x400000 +#define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0) + typedef struct { MemoryRegion iomem; MemoryRegion iomem_lo; /* 0 - 0x900 */ @@ -1427,7 +1429,7 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); /* Southbridge */ - piix4 = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true, + piix4 = pci_create_simple_multifunction(pci_bus, PIIX4_PCI_DEVFN, true, TYPE_PIIX4_PCI_DEVICE); isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0")); From patchwork Wed Dec 21 16:59:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 635639 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp3640051pvb; Wed, 21 Dec 2022 09:22:47 -0800 (PST) X-Google-Smtp-Source: AMrXdXssp7kEYIvpNzqVBn3TrH7kuTaKEyoH33UggL4NV6tNGTnk7CTtkCixr5JWsEL76UW8e8mY X-Received: by 2002:ac8:7598:0:b0:3a5:63ef:cf4e with SMTP id s24-20020ac87598000000b003a563efcf4emr3398490qtq.16.1671643367290; Wed, 21 Dec 2022 09:22:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671643367; cv=none; d=google.com; s=arc-20160816; b=iMckT5/9FjnUz9tdIyMcljhKmJ2xVlhI/PYR7JmUv2nB+15pKuUrFWxR8krZWFwAFK uhXYQrwMzdjfYK0glNVxKXSLUornJlBNcLXj444d5edCj5Yj2tryauZkdSCHPLFKfm3k eCu0gLSTKIk15SUlWl/36dawpO3Y8nuCgQx5hWiQMnn4oODDnZwN/f16Vm3asOf5gLx5 dW5gbOsbjQEd7GjuhAFJbi8PFaJtJHyv+2YvurxSrYOH6pxwQF/lzCr0yBqWTj7Ics41 SGGRRNT85fWKmq1rF3TMU/yb8EUQ82WrwhXh0CtHKf1Zngt3kQLdRKvIRBAAh7c8V4L4 W+qQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ncw5nnPVK/uF8+rX+LoiYH3+/VQ+iJInXM5uQBXVtuY=; b=ZpR7An/+yNuGg2pK1JYuOSCRmngTqW0jw6vhmPSSAplx/NI1sVyfUlBmnjxB1HlXi1 ekZHPCTRDzNPHOaie0k4xXY7pxonwkKSuYOpzoz3gPvTvKkNUNSuykbBlpME1StBh4Cb RbPwtC6DN/ZiTnchu3Tvhh3lpMoXmxr/sOn2D3PeScani8Cu6o+LW/LaZjUOLlLSPWl0 Qoe4TKgqrh+irXkz4xwx4S/xvzie2HrMMdeJoYltaamfLUIp9WyfdJ1X+3FJTHqNhnve Pu+7m43wCxM5bvrFcoqWobF7kPJK3FCOzSEYObuBFW4vSIG++zjofBS7f5lkGP9TKXHN YNLQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=WDLsRrkF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[92.224.51.61]) by smtp.gmail.com with ESMTPSA id n14-20020aa7db4e000000b0047466e46662sm7204019edt.39.2022.12.21.09.00.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 09:00:47 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Richard Henderson , Igor Mammedov , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , qemu-block@nongnu.org, =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Jiaxun Yang , Ani Sinha , John Snow , Gerd Hoffmann , "Michael S. Tsirkin" , Eduardo Habkost , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Marcel Apfelbaum Subject: [PATCH v4 02/30] hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader Date: Wed, 21 Dec 2022 17:59:35 +0100 Message-Id: <20221221170003.2929-3-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221221170003.2929-1-shentey@gmail.com> References: <20221221170003.2929-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=shentey@gmail.com; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Linux kernel expects the northbridge & southbridge chipsets configured by the BIOS firmware. We emulate that by writing a tiny bootloader code in write_bootloader(). Upon introduction in commit 5c2b87e34d ("PIIX4 support"), the PIIX4 configuration space included values specific to the Malta board. Set the Malta-specific IRQ routing values in the embedded bootloader, so the next commit can remove the Malta specific bits from the PIIX4 PCI-ISA bridge and make it generic (matching the real hardware). Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221027204720.33611-3-philmd@linaro.org> --- hw/mips/malta.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 2e175741ff..ef3e10dc4d 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -804,6 +804,8 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, stw_p(p++, 0x8422); stw_p(p++, 0x9088); /* sw t0, 0x88(t1) */ + /* TODO set PIIX IRQC[A:D] routing values! */ + stw_p(p++, 0xe320 | NM_HI1(kernel_entry)); stw_p(p++, NM_HI2(kernel_entry)); @@ -841,6 +843,9 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, static void write_bootloader(uint8_t *base, uint64_t run_addr, uint64_t kernel_entry) { + const char pci_pins_cfg[PCI_NUM_PINS] = { + 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ + }; uint32_t *p; /* Small bootloader */ @@ -915,6 +920,20 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, #undef cpu_to_gt32 + /* + * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0. + * Load the PIIX IRQC[A:D] routing config address, then + * write routing configuration to the config data register. + */ + bl_gen_write_u32(&p, /* GT_PCI0_CFGADDR */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8), + tswap32((1 << 31) /* ConfigEn */ + | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8 + | PIIX_PIRQCA)); + bl_gen_write_u32(&p, /* GT_PCI0_CFGDATA */ + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc), + tswap32(ldl_be_p(pci_pins_cfg))); + bl_gen_jump_kernel(&p, true, ENVP_VADDR - 64, /* From patchwork Wed Dec 21 16:59:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 635638 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp3627286pvb; Wed, 21 Dec 2022 09:02:09 -0800 (PST) X-Google-Smtp-Source: AMrXdXu1eYgBGYaA+1whVc3/2X3rk5vXJyUZhZz+qCqsfXUjEM8rTpb2nJx0bMz2+mmLCYxrucLh X-Received: by 2002:a05:6870:468b:b0:148:6257:ca1b with SMTP id a11-20020a056870468b00b001486257ca1bmr1556832oap.14.1671642129124; Wed, 21 Dec 2022 09:02:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1671642129; cv=none; d=google.com; s=arc-20160816; b=eq/QjtAi6a3PRH/S5wvtohcqVJ86YrNfs0EaH4fPLcrsNIj10E4vgi3zP5aaPHdQOM 511pGiSdeX0MK8Xwlhjd6YHds7ZJ+KyX5Kbzxc9i4XyimZ352OqLjTQuI+6ntDa6QH8O dRlWljweNyo6qXAhCQAful/wg9omJfIxGZjpUk2rMdHzrvEUVBk4CAt4WiwyRx12Seeb uP0M+zJeaV8ANJxtmXjq8Xr7KZqaw5vywa/YufXwYbV11PDmoOJWHHy3de80FqK1MEvG bPgsPNkmn+hNABeZtKSxnyKdv9VfzyvSSqQlocVy3IzPPKGY9zFAFMtGPbBWpgyr+/ua qWOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YHtHVYo4NVUXU56/alQ0bH+UtHEiwYpVK/P9pel6Axs=; b=jK1cbN4HKZm++Y5gjhMbENTTl16tODGS2hbiIknNh+ot/zP3OttsM+nLoDXlYjTt7e 6O51AJuSV2LnUJlMNcT8q+rATdl7rU83zCHfitcwbR/9usnvAdcqIwpMEzRKdic78TlY XK0ggKMBn9HFQ5FNCd0TRafsC1rcyFuNABAYE6mp4V4oEtPRKrm6nBnQ7iuRKewxeAUB FwsZ6appahi8tFxyY4MpXm3zTaDNg6shkvICp2Fts1O6rxDs3QebqTPQ7HZ1KGLAlYvz P9VIsijtCEV7BMacq0PxMes1qICRINhXG630sLk43UB5KCrxe0Uk2CeMw4j4fuLhTsTo Yu6w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=A7mlrkZ+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[92.224.51.61]) by smtp.gmail.com with ESMTPSA id n14-20020aa7db4e000000b0047466e46662sm7204019edt.39.2022.12.21.09.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Dec 2022 09:00:48 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Richard Henderson , Igor Mammedov , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Paolo Bonzini , qemu-block@nongnu.org, =?utf-8?q?Herv?= =?utf-8?q?=C3=A9_Poussineau?= , Jiaxun Yang , Ani Sinha , John Snow , Gerd Hoffmann , "Michael S. Tsirkin" , Eduardo Habkost , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Marcel Apfelbaum Subject: [PATCH v4 03/30] hw/isa/piix4: Correct IRQRC[A:D] reset values Date: Wed, 21 Dec 2022 17:59:36 +0100 Message-Id: <20221221170003.2929-4-shentey@gmail.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20221221170003.2929-1-shentey@gmail.com> References: <20221221170003.2929-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=shentey@gmail.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé IRQRC[A:D] registers reset value is 0x80. We were forcing the MIPS Malta machine routing to be able to boot a Linux kernel without any bootloader. We now have these registers initialized in the Malta machine write_bootloader(), so we can use the correct reset values. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20221027204720.33611-4-philmd@linaro.org> --- hw/isa/piix4.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index eca96fb8f0..6e9434129d 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -91,10 +91,10 @@ static void piix4_isa_reset(DeviceState *dev) pci_conf[0x4c] = 0x4d; pci_conf[0x4e] = 0x03; pci_conf[0x4f] = 0x00; - pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10 - pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10 - pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11 - pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11 + pci_conf[0x60] = 0x80; + pci_conf[0x61] = 0x80; + pci_conf[0x62] = 0x80; + pci_conf[0x63] = 0x80; pci_conf[0x69] = 0x02; pci_conf[0x70] = 0x80; pci_conf[0x76] = 0x0c;