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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:33 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 03/15] dt-bindings: clock: qcom: gcc-qcs404: define clocks/clock-names for QCS404 Date: Sat, 17 Dec 2022 02:17:18 +0200 Message-Id: <20221217001730.540502-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define clock/clock-names properties of the GCC device node to be used on QCS404 platform. Signed-off-by: Dmitry Baryshkov --- .../bindings/clock/qcom,gcc-qcs404.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml index b70901e0d5cf..b2256f81b265 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml @@ -20,6 +20,24 @@ properties: compatible: const: qcom,gcc-qcs404 + clocks: + items: + - description: XO source + - description: Sleep clock source + - description: PCIe 0 PIPE clock (optional) + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: HDMI phy PLL clock + + clock-names: + items: + - const: cxo + - const: sleep_clk + - const: pcie_0_pipe_clk_src + - const: dsi0pll + - const: dsi0pllbyte + - const: hdmi_pll + required: - compatible From patchwork Sat Dec 17 00:17:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635043 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 389CEC3DA7D for ; Sat, 17 Dec 2022 00:24:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230153AbiLQAYF (ORCPT ); Fri, 16 Dec 2022 19:24:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229743AbiLQAXJ (ORCPT ); Fri, 16 Dec 2022 19:23:09 -0500 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7163B7E28D for ; Fri, 16 Dec 2022 16:17:36 -0800 (PST) Received: by mail-lf1-x135.google.com with SMTP id p36so5843924lfa.12 for ; Fri, 16 Dec 2022 16:17:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pNEPONWFMBruQnee+APHuJo/Zl1rzM8Br1Tby3omEos=; b=nWWsRzcRq8/Vx8+74jS/tvFmTyutpKQGriHhBJDwdFj9HvW4FrriSOVEoe8zEOFl0N emOF4ThnyyiexO02fnU/5eECh+yhKLaw1kMS6edNbkEAxTHg9sfs/25TzlBFRGZoO3Vy jLWMC94k1GU2iRRXQzCV7o/TMdN/zp+PzjjQyMzgMMZNvXkk1ihDv3Tf6hc6Xx7jmhDe aBbLjqb9AVuM6Fw11THXJZdC4auBQEGvECz3DPK5yx2mMhgG99dtMsu6Xelk0L9tRyhD klbeDbe5VzxD8As+yLTfR/uR9fJ3MbUl/6h92OfqNi5mbB0YU4CKTS0kVanjqlpldDCR kDBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pNEPONWFMBruQnee+APHuJo/Zl1rzM8Br1Tby3omEos=; b=AAfx08BSXa6wTfX+wgeXiGlg4eGUYd15o27t1bF1SMseGmRH4ulhTwBRUgnMqgpKPH vbbUiL5o5GsjLIZjrqrKyx09efqxR+HD9DJleRhFYm05eud69/hX0oBkVS4nI+hN/xiZ gRI/oWmlMg076syPHw3i/m2CWbluNRP2CsVcAbgn5FOtA8oISji2B0fGO4ECHb+wUmrz IHwzP1X7GoLoubDYqp1tYXn38wMT9n81pMqt4j0quZncVitkELUcYWUebV/PrRrOqY0P xUL4pReQWf1tvvRvdht1qR/1uFDDGeajqgV7Mvdd7PrK0G933o9M2KnEu2Nyv4OcXyd4 JZJg== X-Gm-Message-State: ANoB5pmFtcIxPY1/ylhk/+w90/lmdBuhT4iTebbzMgPwsu1yTsUe0RYY YYPxgRM23tq1Bp9lrCYyyuaSBA== X-Google-Smtp-Source: AA0mqf6V1Ya+qRbNkEL4R+4qw4T1RzZGjMvOBDn3H0uwg2LyeB+2u0X56U6FrtVe0C4fILlUg1/T1g== X-Received: by 2002:a05:6512:282b:b0:4b6:fdbe:773d with SMTP id cf43-20020a056512282b00b004b6fdbe773dmr6458550lfb.43.1671236254753; Fri, 16 Dec 2022 16:17:34 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:34 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 04/15] clk: qcom: gcc-qcs404: use ARRAY_SIZE instead of specifying num_parents Date: Sat, 17 Dec 2022 02:17:19 +0200 Message-Id: <20221217001730.540502-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data/names/hws easy and errorproof. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 86 +++++++++++++++++------------------ 1 file changed, 43 insertions(+), 43 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 46d314d69250..f60a0ab42da1 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -440,7 +440,7 @@ static struct clk_rcg2 apss_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "apss_ahb_clk_src", .parent_names = gcc_parent_names_ao_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_ao_0), .flags = CLK_IS_CRITICAL, .ops = &clk_rcg2_ops, }, @@ -461,7 +461,7 @@ static struct clk_rcg2 blsp1_qup0_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup0_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -486,7 +486,7 @@ static struct clk_rcg2 blsp1_qup0_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup0_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -500,7 +500,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -525,7 +525,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -539,7 +539,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -565,7 +565,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -579,7 +579,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -593,7 +593,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -607,7 +607,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -621,7 +621,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -655,7 +655,7 @@ static struct clk_rcg2 blsp1_uart0_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart0_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -669,7 +669,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart1_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -683,7 +683,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart2_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -698,7 +698,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart3_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -712,7 +712,7 @@ static struct clk_rcg2 blsp2_qup0_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup0_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -726,7 +726,7 @@ static struct clk_rcg2 blsp2_qup0_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup0_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -740,7 +740,7 @@ static struct clk_rcg2 blsp2_uart0_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart0_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -753,7 +753,7 @@ static struct clk_rcg2 byte0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "byte0_clk_src", .parent_names = gcc_parent_names_5, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_5), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -776,7 +776,7 @@ static struct clk_rcg2 emac_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "emac_clk_src", .parent_names = gcc_parent_names_4, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_4), .ops = &clk_rcg2_ops, }, }; @@ -797,7 +797,7 @@ static struct clk_rcg2 emac_ptp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "emac_ptp_clk_src", .parent_names = gcc_parent_names_4, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_4), .ops = &clk_rcg2_ops, }, }; @@ -816,7 +816,7 @@ static struct clk_rcg2 esc0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "esc0_clk_src", .parent_names = gcc_parent_names_6, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_6), .ops = &clk_rcg2_ops, }, }; @@ -850,7 +850,7 @@ static struct clk_rcg2 gfx3d_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gfx3d_clk_src", .parent_names = gcc_parent_names_7, - .num_parents = 6, + .num_parents = ARRAY_SIZE(gcc_parent_names_7), .ops = &clk_rcg2_ops, }, }; @@ -871,7 +871,7 @@ static struct clk_rcg2 gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp1_clk_src", .parent_names = gcc_parent_names_2, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_2), .ops = &clk_rcg2_ops, }, }; @@ -885,7 +885,7 @@ static struct clk_rcg2 gp2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp2_clk_src", .parent_names = gcc_parent_names_2, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_2), .ops = &clk_rcg2_ops, }, }; @@ -899,7 +899,7 @@ static struct clk_rcg2 gp3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp3_clk_src", .parent_names = gcc_parent_names_2, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_2), .ops = &clk_rcg2_ops, }, }; @@ -913,7 +913,7 @@ static struct clk_rcg2 hdmi_app_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_app_clk_src", .parent_names = gcc_parent_names_1, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), .ops = &clk_rcg2_ops, }, }; @@ -927,7 +927,7 @@ static struct clk_rcg2 hdmi_pclk_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_pclk_clk_src", .parent_names = gcc_parent_names_8, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_8), .ops = &clk_rcg2_ops, }, }; @@ -954,7 +954,7 @@ static struct clk_rcg2 mdp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mdp_clk_src", .parent_names = gcc_parent_names_9, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parent_names_9), .ops = &clk_rcg2_ops, }, }; @@ -973,7 +973,7 @@ static struct clk_rcg2 pcie_0_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pcie_0_aux_clk_src", .parent_names = gcc_parent_names_10, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_10), .ops = &clk_rcg2_ops, }, }; @@ -994,7 +994,7 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pcie_0_pipe_clk_src", .parent_names = gcc_parent_names_11, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_11), .ops = &clk_rcg2_ops, }, }; @@ -1007,7 +1007,7 @@ static struct clk_rcg2 pclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pclk0_clk_src", .parent_names = gcc_parent_names_12, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_12), .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, }, @@ -1028,7 +1028,7 @@ static struct clk_rcg2 pdm2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pdm2_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -1056,7 +1056,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_apps_clk_src", .parent_names = gcc_parent_names_13, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parent_names_13), .ops = &clk_rcg2_floor_ops, }, }; @@ -1076,7 +1076,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_ice_core_clk_src", .parent_names = gcc_parent_names_3, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_3), .ops = &clk_rcg2_ops, }, }; @@ -1102,7 +1102,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc2_apps_clk_src", .parent_names = gcc_parent_names_14, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_14), .ops = &clk_rcg2_floor_ops, }, }; @@ -1116,7 +1116,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb20_mock_utmi_clk_src", .parent_names = gcc_parent_names_1, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), .ops = &clk_rcg2_ops, }, }; @@ -1138,7 +1138,7 @@ static struct clk_rcg2 usb30_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_master_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -1152,7 +1152,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_mock_utmi_clk_src", .parent_names = gcc_parent_names_1, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), .ops = &clk_rcg2_ops, }, }; @@ -1166,7 +1166,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb3_phy_aux_clk_src", .parent_names = gcc_parent_names_1, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), .ops = &clk_rcg2_ops, }, }; @@ -1189,7 +1189,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb_hs_system_clk_src", .parent_names = gcc_parent_names_3, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_3), .ops = &clk_rcg2_ops, }, }; @@ -1203,7 +1203,7 @@ static struct clk_rcg2 vsync_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vsync_clk_src", .parent_names = gcc_parent_names_15, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_15), .ops = &clk_rcg2_ops, }, }; @@ -1225,7 +1225,7 @@ static struct clk_rcg2 cdsp_bimc_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "cdsp_bimc_clk_src", .parent_names = gcc_parent_names_16, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_16), .ops = &clk_rcg2_ops, }, }; From patchwork Sat Dec 17 00:17:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80F60C4708E for ; Sat, 17 Dec 2022 00:24:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229880AbiLQAYH (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:37 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Stephen Boyd Subject: [PATCH 08/15] clk: qcom: gcc-qcs404: get rid of the test clock Date: Sat, 17 Dec 2022 02:17:23 +0200 Message-Id: <20221217001730.540502-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 34 ---------------------------------- 1 file changed, 34 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 5636c6524d0f..fb94c57a00af 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -22,7 +22,6 @@ #include "reset.h" enum { - P_CORE_BI_PLL_TEST_SE, P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_DSICLK, /* P_GPLL0_OUT_AUX, */ @@ -41,29 +40,24 @@ enum { static const struct parent_map gcc_parent_map_0[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_0[] = { "cxo", "gpll0_out_main", - "core_bi_pll_test_se", }; static const char * const gcc_parent_names_ao_0[] = { "cxo", "gpll0_ao_out_main", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_1[] = { { P_XO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_1[] = { "cxo", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_2[] = { @@ -84,54 +78,46 @@ static const struct parent_map gcc_parent_map_3[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL6_OUT_AUX, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_3[] = { "cxo", "gpll0_out_main", "gpll6_out_aux", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_4[] = { { P_XO, 0 }, { P_GPLL1_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_4[] = { "cxo", "gpll1_out_main", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_5[] = { { P_XO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, /* { P_GPLL0_OUT_AUX, 2 }, */ - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_5[] = { "cxo", "dsi0pllbyte", /* "gpll0_out_aux", */ - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_6[] = { { P_XO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, /* { P_GPLL0_OUT_AUX, 3 }, */ - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_6[] = { "cxo", "dsi0pllbyte", /* "gpll0_out_aux", */ - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_7[] = { @@ -140,7 +126,6 @@ static const struct parent_map gcc_parent_map_7[] = { { P_GPLL3_OUT_MAIN, 2 }, { P_GPLL6_OUT_AUX, 3 }, /* { P_GPLL4_OUT_AUX, 4 }, */ - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_7[] = { @@ -149,19 +134,16 @@ static const char * const gcc_parent_names_7[] = { "gpll3_out_main", "gpll6_out_aux", /* "gpll4_out_aux", */ - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_8[] = { { P_XO, 0 }, { P_HDMI_PHY_PLL_CLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_8[] = { "cxo", "hdmi_pll", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_9[] = { @@ -169,7 +151,6 @@ static const struct parent_map gcc_parent_map_9[] = { { P_GPLL0_OUT_MAIN, 1 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 2 }, { P_GPLL6_OUT_AUX, 3 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_9[] = { @@ -177,45 +158,38 @@ static const char * const gcc_parent_names_9[] = { "gpll0_out_main", "dsi0pll", "gpll6_out_aux", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_10[] = { { P_XO, 0 }, { P_SLEEP_CLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_10[] = { "cxo", "sleep_clk", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_11[] = { { P_XO, 0 }, { P_PCIE_0_PIPE_CLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_11[] = { "cxo", "pcie_0_pipe_clk", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_12[] = { { P_XO, 0 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, /* { P_GPLL0_OUT_AUX, 2 }, */ - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_12[] = { "cxo", "dsi0pll", /* "gpll0_out_aux", */ - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_13[] = { @@ -223,7 +197,6 @@ static const struct parent_map gcc_parent_map_13[] = { { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL4_OUT_MAIN, 2 }, { P_GPLL6_OUT_AUX, 3 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_13[] = { @@ -231,47 +204,40 @@ static const char * const gcc_parent_names_13[] = { "gpll0_out_main", "gpll4_out_main", "gpll6_out_aux", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_14[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, /* { P_GPLL4_OUT_AUX, 2 }, */ - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_14[] = { "cxo", "gpll0_out_main", /* "gpll4_out_aux", */ - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_15[] = { { P_XO, 0 }, /* { P_GPLL0_OUT_AUX, 2 }, */ - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_15[] = { "cxo", /* "gpll0_out_aux", */ - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_16[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, /* { P_GPLL0_OUT_AUX, 2 }, */ - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_16[] = { "cxo", "gpll0_out_main", /* "gpll0_out_aux", */ - "core_bi_pll_test_se", }; static struct clk_fixed_factor cxo = { From patchwork Sat Dec 17 00:17:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635041 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0372BC53210 for ; Sat, 17 Dec 2022 00:24:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230281AbiLQAYJ (ORCPT ); Fri, 16 Dec 2022 19:24:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230286AbiLQAXO (ORCPT ); Fri, 16 Dec 2022 19:23:14 -0500 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87C5D7E2A6 for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:40 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 12/15] clk: qcom: gcc-qcs404: add support for GDSCs Date: Sat, 17 Dec 2022 02:17:27 +0200 Message-Id: <20221217001730.540502-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for two GDSCs provided by this clock controller. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 8fb268671f0c..f8dbfffc2b8e 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -19,6 +19,7 @@ #include "clk-rcg.h" #include "clk-regmap.h" #include "common.h" +#include "gdsc.h" #include "reset.h" enum { @@ -2598,6 +2599,22 @@ static struct clk_branch gcc_wdsp_q6ss_axim_clk = { }, }; +static struct gdsc mdss_gdsc = { + .gdscr = 0x4d078, + .pd = { + .name = "mdss", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc oxili_gdsc = { + .gdscr = 0x5901c, + .pd = { + .name = "oxili", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct clk_hw *gcc_qcs404_hws[] = { &cxo.hw, }; @@ -2748,6 +2765,11 @@ static struct clk_regmap *gcc_qcs404_clocks[] = { }; +static struct gdsc *gcc_qcs404_gdscs[] = { + [MDSS_GDSC] = &mdss_gdsc, + [OXILI_GDSC] = &oxili_gdsc, +}; + static const struct qcom_reset_map gcc_qcs404_resets[] = { [GCC_GENI_IR_BCR] = { 0x0F000 }, [GCC_CDSP_RESTART] = { 0x18000 }, @@ -2790,6 +2812,8 @@ static const struct qcom_cc_desc gcc_qcs404_desc = { .num_resets = ARRAY_SIZE(gcc_qcs404_resets), .clk_hws = gcc_qcs404_hws, .num_clk_hws = ARRAY_SIZE(gcc_qcs404_hws), + .gdscs = gcc_qcs404_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_qcs404_gdscs), }; static const struct of_device_id gcc_qcs404_match_table[] = { From patchwork Sat Dec 17 00:17:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635040 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 92A8DC63707 for ; Sat, 17 Dec 2022 00:24:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230342AbiLQAYM (ORCPT ); Fri, 16 Dec 2022 19:24:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230320AbiLQAXQ (ORCPT ); Fri, 16 Dec 2022 19:23:16 -0500 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB9627E2A9 for ; Fri, 16 Dec 2022 16:17:43 -0800 (PST) Received: by mail-lf1-x132.google.com with SMTP id j4so5973183lfk.0 for ; Fri, 16 Dec 2022 16:17:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=A4AidH89fDpMmt6amLOtMiqausw19uEwRJmaxMyMhmE=; b=mvu+zcFLAf58M4jAxZ4udj7LLuscOB0CGdZ9pnf9THwitGd3A6WpFJqlaHcZoAJ4C3 d0BHEov/lFbUST22RE9eJPDpp1g48jpR+STO9gwkEs0v6yPnzGTGpp+rb9QehomtTd/1 AhQyWGUaoA9kGX7GOBioyC9ak1IV34i+x4Fv5CWsgzEXyburjLG2H1/AQnuJBQ/6E6zI ImeHDRGIY3Hh2AVE8vafDPkf92sIHfKII4W3dPRuCqDSHJrsASVGuC9gyw9/IMsu06LB tyGAC4B9Sm53yl3btc4wizgr5L2DTFH8Tqh3910+ozR+LHKTXKwIA0f7F22bPhllwSeI QDJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A4AidH89fDpMmt6amLOtMiqausw19uEwRJmaxMyMhmE=; b=QroIKxcLLLqhwe6jvzfUlO6ppTYS0kGhYtXbonB6/3riZaLyrjWNeezR+Z/gzKRGp+ ilPyFB9z0e4BIq+gN4oBQgYy/WoU9L5dBVxH9jeq2QV6ltdzGno1FZGzSiEoBoD5NZNE lkDvyApalajOelOzmIUrgvDZROtSrmqGVgUopwtO/YvQKLu2iWC0xWxl+O4i2RNKQU1z x18VkZHoXWf0JOCg6qPh47v15i0QpKkawgofeQVZj/oaXsGzr0EnDS5Rc+RnGmsijiqA swvT7u5OsJDKS9sJBrLfK7Y1FAAFP93g17UDmEzkt+ntjqyRe0YrC/rWY7exmMsg3upK QYDA== X-Gm-Message-State: ANoB5pmxdiODeH1jn1hvR4JXEisv79BGxMfhfKj2WQ4WQTwON3+sdh6R bK8HG0AC5pX98nXSJPfu1+gxyg== X-Google-Smtp-Source: AA0mqf7EboJmYvwsEFdy2YkliyzGZdHk1/a6i6rKNTBx99M1bmqrk/TOuENbGUuAQodZq8RRIt2FmA== X-Received: by 2002:a05:6512:3990:b0:4b6:d28a:2558 with SMTP id j16-20020a056512399000b004b6d28a2558mr15344090lfu.49.1671236262055; Fri, 16 Dec 2022 16:17:42 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:41 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 13/15] arm64: dts: qcom: qcs404: use symbol names for PCIe resets Date: Sat, 17 Dec 2022 02:17:28 +0200 Message-Id: <20221217001730.540502-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The commit e5bbbff5b7d7 ("clk: gcc-qcs404: Add PCIe resets") added names for PCIe resets, but it did not change the existing qcs404.dtsi to use these names. Do it now and use symbol names to make it easier to check and modify the dtsi in future. Fixes: e5bbbff5b7d7 ("clk: gcc-qcs404: Add PCIe resets") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index ffffaa7507cf..ffc4b081bb62 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -806,7 +806,7 @@ pcie_phy: phy@7786000 { clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, - <&gcc 21>; + <&gcc GCC_PCIE_0_PIPE_ARES>; reset-names = "phy", "pipe"; clock-output-names = "pcie_0_pipe_clk"; @@ -1337,12 +1337,12 @@ pcie: pci@10000000 { <&gcc GCC_PCIE_0_SLV_AXI_CLK>; clock-names = "iface", "aux", "master_bus", "slave_bus"; - resets = <&gcc 18>, - <&gcc 17>, - <&gcc 15>, - <&gcc 19>, + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, <&gcc GCC_PCIE_0_BCR>, - <&gcc 16>; + <&gcc GCC_PCIE_0_AHB_ARES>; reset-names = "axi_m", "axi_s", "axi_m_sticky", From patchwork Sat Dec 17 00:17:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635039 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7ED6C4167B for ; Sat, 17 Dec 2022 00:24:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230347AbiLQAYP (ORCPT ); Fri, 16 Dec 2022 19:24:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57694 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230120AbiLQAXS (ORCPT ); Fri, 16 Dec 2022 19:23:18 -0500 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 430527E299 for ; Fri, 16 Dec 2022 16:17:43 -0800 (PST) Received: by mail-lf1-x12a.google.com with SMTP id c1so5877123lfi.7 for ; Fri, 16 Dec 2022 16:17:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1Hsa31ymOeybHDD6Oy0urHW3AuIWlU3Je1yr2qvFGAY=; b=VgI3nLWS3nexAa4ub9/UR1Rq9pDey2EJDDSCbEaJGoAbQrscscKiVHeDBy4rN/8D45 24b4WLE1T/MjA0CTpYkbcgZEcXETxTDNgaSzLeF+Tfm4Znlinn41mi5ut55njZCad/us +WXufuTh45XyAQXqrpDRadg7NEh/7ElZMbPbdGXwtW1kL/cDi2z0lAF9dXCoPl62enkD oSw8A0a/hcL2iCtukYBPNg4GiBKjn+BMmhGF4jlBMsqs/toBWH+s6qYvWhgOjdZy7sRX IXjEDpt3oMwNgwvweMokV7iXv7b0gOLtzCcfjfd3L2Y0BEyIylAUYk55EPCfqZStzrbZ lXgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1Hsa31ymOeybHDD6Oy0urHW3AuIWlU3Je1yr2qvFGAY=; b=CCDKPAXGlADQJI9s7FfqP+z2VAP2aD4wNQEN1aNAx3NZCwJ2FWeBuJuPau7ShFpgi3 FYT7X3ZsJQHWCJOw8vGS4nzxcMYTNHiiFH29HTAeOF9pFAXPp6/7FnnYW3ta69ryMhp1 q48g9KaFkWis2M6/UHEtA6+vVTNKQzxt+C/Vr6rImCVgkxjkC+eaegSqiO3TIFof5ren +pDx3NmXhohcShKI9d6zIE/N5VjtNKF6jKDotuF+/N9UmotR4gTGdJdsY2OsIatLLa/J IE4MJYqXrl6qli1tljIJE/PTw6FmRbCbdzFctwiw7MD1ZmTqPEfpxH07ulBBYg9WI5SH JRqw== X-Gm-Message-State: ANoB5pnzMMpsxbptLN9kE4eLajgnplHtu5tQwEnEhuH7oR5EmsUoU5Z5 W2pBcmIvbZAl8J0S/C/99y/RSA== X-Google-Smtp-Source: AA0mqf5bsvN6t916su3JhYhq1Z8++hWXdyWEbPhMmOtVCvinfLd2TxCbGNZ6yrEJEBeEg+NIA3y/WQ== X-Received: by 2002:a05:6512:acf:b0:4a4:68b7:dec0 with SMTP id n15-20020a0565120acf00b004a468b7dec0mr10439992lfu.28.1671236262850; Fri, 16 Dec 2022 16:17:42 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:42 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 14/15] arm64: dts: qcom: qcs404: add power-domains-cells to gcc node Date: Sat, 17 Dec 2022 02:17:29 +0200 Message-Id: <20221217001730.540502-15-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As gcc now provides two GDSCs, add #power-domain-cells property to the gcc device node. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index ffc4b081bb62..b72542631337 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -729,6 +729,7 @@ gcc: clock-controller@1800000 { reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; assigned-clock-rates = <19200000>; From patchwork Sat Dec 17 00:17:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 635038 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C3EFC3DA6E for ; Sat, 17 Dec 2022 00:24:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230120AbiLQAYQ (ORCPT ); Fri, 16 Dec 2022 19:24:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230338AbiLQAXU (ORCPT ); Fri, 16 Dec 2022 19:23:20 -0500 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 52C9D7E29A for ; Fri, 16 Dec 2022 16:17:45 -0800 (PST) Received: by mail-lf1-x133.google.com with SMTP id bf43so5891868lfb.6 for ; Fri, 16 Dec 2022 16:17:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IakMGoNeAkiafUmQyTYpE4STAOzYx1wLgMpz/v+W8ao=; b=gtUM7rgOl3NWuHdHVJ+11cJsj01C6/8ZgNNQ/DlRMO8KZoTb3WAeN8TQW2gTc0l/QL 6FRIJCuQBH1OEUCzXYkR52dMEAJyNxMfCm7Ao83or+QxGqPdMRu9ut5spBcRdOk8oDJ0 aUi/dv3zc3z1QZqsv6L08kaf/9n2YSJfpzcP07/Lqhj1TdZe21sgCvnhu1IiF8dcgkUR UotVQdtVd0KtlNf1ColX1NRF2OdeGAGkmpjG5694VpQ4Xyy6MEk3qDfDIYZgNVX/mxeQ MItvvdh0ETgtdhzDuVvEFvJeR+KkLW7H6ZujyQ05B1ofw6XV/Jw0pPB+2NRT4l0rU9NQ urhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IakMGoNeAkiafUmQyTYpE4STAOzYx1wLgMpz/v+W8ao=; b=wHH/qKQOEQNiYejGltVauXvVMycm+xAJiqIHbDQApQmk0MGQUjtM5hak7jLxnn0qjZ mz1OLqYBB/8gjSKUVSmsCaWY1ujPdIF1ywcwk8+eTEo8JqwubEgbwO6YdB33bOmL403X 1W0aeQV+jlm9Vts5xk0/Cx15vGn0Fl2jjXyy5/GZbPfmazYyjsluvQ14kLZ6UsLmii1F 5rJ+N2MbN3lOPU8Jc0rokMMWDSZbz3L/AvUGHBfx7H9GGrh8Jf9LY6Vm/KAcW0xzSPYw EU+9cnzRUeK9eSWmGIV5UW57yYLE/76UvUvFOA1jFhIrpTUtjtynLARWtgOV4EcdxZnL 0yEw== X-Gm-Message-State: ANoB5pnAn/vuGDg9oWJPRHD2iZhrHsGAxbQolYP7mRHJw/FLBpGIK2Fy ZN9f91CEiQFv5aZibqN2x4IpcA== X-Google-Smtp-Source: AA0mqf7x2WdR/+5Wh61oqWdZBmYm7BWZfGQtYvK7acmOqBpQ6tod/EDIbGs+3nxToPHONFh7ye+lkA== X-Received: by 2002:a05:6512:7b:b0:4a9:9827:68e8 with SMTP id i27-20020a056512007b00b004a9982768e8mr7609075lfo.7.1671236263654; Fri, 16 Dec 2022 16:17:43 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:43 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 15/15] arm64: dts: qcom: qcs404: add clocks to the gcc node Date: Sat, 17 Dec 2022 02:17:30 +0200 Message-Id: <20221217001730.540502-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Populate the gcc node with the clocks and clock-names properties to enable DT-based lookups for the parent clocks. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index b72542631337..ee337a3980fa 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -731,6 +731,19 @@ gcc: clock-controller@1800000 { #reset-cells = <1>; #power-domain-cells = <1>; + clocks = <&xo_board>, + <&sleep_clk>, + <&pcie_phy>, + <0>, + <0>, + <0>; + clock-names = "cxo", + "sleep_clk", + "pcie_0_pipe_clk_src", + "dsi0pll", + "dsi0pllbyte", + "hdmi_pll"; + assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; assigned-clock-rates = <19200000>; };