From patchwork Sat Dec 17 00:17:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 634878 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C606EC53210 for ; Sat, 17 Dec 2022 00:23:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230006AbiLQAXd (ORCPT ); Fri, 16 Dec 2022 19:23:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230452AbiLQAXD (ORCPT ); Fri, 16 Dec 2022 19:23:03 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ADA2B66C3D for ; Fri, 16 Dec 2022 16:17:33 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id y25so5868029lfa.9 for ; Fri, 16 Dec 2022 16:17:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Xw0n1LkFyR04NfrsZcxul+5/yjJGz7Sdv3Db/gbp0H8=; b=U50zxo8n/BD6fQ/v/hWIab/sQDbcMY1DAGIDGZmwtczhL7OKc7YbnT7F67SxtTszZk jEU0AxaYsZRcwJGFb/9pFqjE0LXA8LpkP0hDRoVHPgyJ0/VQ8YJIsVEl4htCQbkX5raG fCJnn+SWeTEJ51X2LhfvMcJBc2fb0HSDbq4Ouj5VfXSSVEB8so1CIUV110wJl7hbnNDl eoTCfwgP8EbJrM3cFeEsLCA6eFmaPo0/eR0mRnqdpj9r6svJuyxuXpBUy3N8FMFeENWf VOfU8PS2g+THHj+sgoZnuDKvGw71v0l9x89assRHTPGK8guczNvDsKyKUxDaiLYdMPMB e5Lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xw0n1LkFyR04NfrsZcxul+5/yjJGz7Sdv3Db/gbp0H8=; b=RaXcBbHT9fRoc3q4Nh7RMum9FZc/Nu195xUHiX3A1S9a7Jj+WMSuD9dOFzCs4fVPQq +lB7LMCwMYdRq/Z5x6det8wuHlmk1MJuj5f82R/T0rpsAae/GWGi6dNu7pI9B87VPdR0 eC/7uXZP9s7qAuiJ6dZBsyrTWyEqyZKusIh9LHVYaOhuEXYlh5rTmNXBmRC2uiKE5Q7D hDg3FOuNDvGNLlw2AueJt9kl5gdp93C9kVXE65XCSM+Tu3G4fG7gwLjpGo4uE1QpFtNy VLs3abU1dmlx0u0Nc9sHBk7hJ2Fj1nyFqjTase9o/qcrhmHHMGildkh+oicxMJivHj1o bUrQ== X-Gm-Message-State: ANoB5pkCFH8fldYxBGBZJGCzD/T6jfCIde0S6mr3nhOgtPqr+44Jdycq BBQ0TVNyUyjB+hOPcRsmyFB6CA== X-Google-Smtp-Source: AA0mqf49NRUCkB+rHihLGWKrvFeZlWFy4qTa00HW+o604lrVwXriqc9YxMeQtPG9YgYunx4dm8VvQw== X-Received: by 2002:a05:6512:3992:b0:4a4:68b7:dec3 with SMTP id j18-20020a056512399200b004a468b7dec3mr12330945lfu.31.1671236252091; Fri, 16 Dec 2022 16:17:32 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:31 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 01/15] dt-bindings: clock: qcom: gcc-qcs404: add two GDSC entries Date: Sat, 17 Dec 2022 02:17:16 +0200 Message-Id: <20221217001730.540502-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On QCS404 platform the Global Clock Controller supports two GDSCs: MDSS (display) and OXILI (GPU). Add corresponding indices. Signed-off-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,gcc-qcs404.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h index bc3051543347..126a51898571 100644 --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h @@ -177,4 +177,8 @@ #define GCC_PCIE_0_PIPE_ARES 21 #define GCC_WDSP_RESTART 22 +/* Indexes for GDSCs */ +#define MDSS_GDSC 0 +#define OXILI_GDSC 1 + #endif From patchwork Sat Dec 17 00:17:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 634879 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0AA6CC3DA7C for ; Sat, 17 Dec 2022 00:23:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230438AbiLQAXc (ORCPT ); Fri, 16 Dec 2022 19:23:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230006AbiLQAXD (ORCPT ); Fri, 16 Dec 2022 19:23:03 -0500 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8F7CED134 for ; Fri, 16 Dec 2022 16:17:34 -0800 (PST) Received: by mail-lf1-x134.google.com with SMTP id b3so5922377lfv.2 for ; Fri, 16 Dec 2022 16:17:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CWDEXJzpxC4huaA0slWAfF/NQqnpK+eVzsXesechI68=; b=ZM+yJDsO4PF6SLgMkRXKqOLBmkr4aePNEveh3MLwWck2DRedVIehlz+t321+Per36C Q4Gb7s/U5GmJ1xkxycHgLZdBQn32HrV3PXIQD7vTZEwkQVmjGO6H7s5I724DnIdLzsXX cdQNc2i72/DW7QV8PjUOdqXgQJEvJnHj2I97KnoVeTrTeUrxqeBbi/SsaFxs6Ihv+4b4 tym+YGhIgfULSnP15kgZ8PIeK8lHVMjol1WuAgjkUkisA3fEY8wBezj3OzdxdKwRgVbw aXTWsrPEHvgdRWXsKH/NrE4p+gfv9P4mv0+C9LuxXrGuV+ddt/g9+WraqyFDKEBlRmxw PEUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CWDEXJzpxC4huaA0slWAfF/NQqnpK+eVzsXesechI68=; b=CaBQxqE1aVmN2SKDt9qpcgUcpWOGWvbiue7T6DfwfP2RvZfPlufPhEAUtokAl/m+9G kn9d7XWwNXwA9p/s5+deYzj9b7BBlm+YzPEtncEuSLygoQhga5bMt+puIkE/AE+JlnCq dvhvQh3Q22Fv2kUB3AZokgMqoYx+cmdhLHnqjT7qyy3NzhWmNK8i+ZekczdTW1H7CFrb 0Yw0TzSArmsDl3jyeJbl/K5C+qu/DQ2AutM8VaZvdfShBHbjSTtA4L8S7BmQnO32FttW Qq+IwBjhbQa6XUouES+85CdmM9d5Be7kQGdJ0t5C68CMF57Ovsg7ix+SgwJ248npzvkq qjVw== X-Gm-Message-State: ANoB5pm3NbkyzUpYT5U/H2e7tIOLR/IQdMYv7rxUrEaTZ6Fqp+HvuKCS 3wIX8flbFzjZOL3SiqGqUgdA9w== X-Google-Smtp-Source: AA0mqf6L/thwkt+x+ppQjT9ni0s1uXIDIr5UKDKwpKCb2/rgfqzuayJaDX3ZCrQqSwl1nvqP1vxo8g== X-Received: by 2002:a19:6719:0:b0:4b5:7374:90a4 with SMTP id b25-20020a196719000000b004b5737490a4mr8947691lfc.49.1671236252968; Fri, 16 Dec 2022 16:17:32 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:32 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 02/15] dt-bindings: clock: qcom: gcc-qcs404: switch to gcc.yaml Date: Sat, 17 Dec 2022 02:17:17 +0200 Message-Id: <20221217001730.540502-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now as the gcc-qcs404 gained support for GDSC and requires using the #power-domain-cells property, switch the qcom,gcc-qcs404.yaml schema to use common gcc.yaml. Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,gcc-qcs404.yaml | 22 +++++-------------- 1 file changed, 5 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml index dca5775f79a4..b70901e0d5cf 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml @@ -20,26 +20,13 @@ properties: compatible: const: qcom,gcc-qcs404 - '#clock-cells': - const: 1 - - '#reset-cells': - const: 1 - - reg: - maxItems: 1 - - protected-clocks: - description: - Protected clock specifier list as per common clock binding. - required: - compatible - - reg - - '#clock-cells' - - '#reset-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | @@ -48,5 +35,6 @@ examples: reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; }; ... 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:33 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 03/15] dt-bindings: clock: qcom: gcc-qcs404: define clocks/clock-names for QCS404 Date: Sat, 17 Dec 2022 02:17:18 +0200 Message-Id: <20221217001730.540502-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Define clock/clock-names properties of the GCC device node to be used on QCS404 platform. Signed-off-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,gcc-qcs404.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml index b70901e0d5cf..b2256f81b265 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qcs404.yaml @@ -20,6 +20,24 @@ properties: compatible: const: qcom,gcc-qcs404 + clocks: + items: + - description: XO source + - description: Sleep clock source + - description: PCIe 0 PIPE clock (optional) + - description: DSI phy instance 0 dsi clock + - description: DSI phy instance 0 byte clock + - description: HDMI phy PLL clock + + clock-names: + items: + - const: cxo + - const: sleep_clk + - const: pcie_0_pipe_clk_src + - const: dsi0pll + - const: dsi0pllbyte + - const: hdmi_pll + required: - compatible From patchwork Sat Dec 17 00:17:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 634991 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21EC8C53210 for ; Sat, 17 Dec 2022 00:24:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230129AbiLQAYF (ORCPT ); Fri, 16 Dec 2022 19:24:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229851AbiLQAXF (ORCPT ); Fri, 16 Dec 2022 19:23:05 -0500 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6084C7E281 for ; Fri, 16 Dec 2022 16:17:36 -0800 (PST) Received: by mail-lf1-x136.google.com with SMTP id cf42so5926828lfb.1 for ; Fri, 16 Dec 2022 16:17:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pNEPONWFMBruQnee+APHuJo/Zl1rzM8Br1Tby3omEos=; b=nWWsRzcRq8/Vx8+74jS/tvFmTyutpKQGriHhBJDwdFj9HvW4FrriSOVEoe8zEOFl0N emOF4ThnyyiexO02fnU/5eECh+yhKLaw1kMS6edNbkEAxTHg9sfs/25TzlBFRGZoO3Vy jLWMC94k1GU2iRRXQzCV7o/TMdN/zp+PzjjQyMzgMMZNvXkk1ihDv3Tf6hc6Xx7jmhDe aBbLjqb9AVuM6Fw11THXJZdC4auBQEGvECz3DPK5yx2mMhgG99dtMsu6Xelk0L9tRyhD klbeDbe5VzxD8As+yLTfR/uR9fJ3MbUl/6h92OfqNi5mbB0YU4CKTS0kVanjqlpldDCR kDBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pNEPONWFMBruQnee+APHuJo/Zl1rzM8Br1Tby3omEos=; b=tlzTflHWiDTKisQdwavBIIHzIb3ZbJmQQW6oOgu7eSdX9kN3N03Vjira4Z5wv0fw80 NAmWdkeQpadaSaRcHSU+bFYsDzPbR5EByKdwEb3v//uwYdIAOjXBNW2186AcxuMQeWXE Z/P2iLTCsJLQCgN5js5/2H3c7OebHkTOFnKKwmV0cXiIXQhoJHLdgH3F+gtojp7qq7+b ZRNc0FAXOYFs1IfF9XBlcvegFAJxLaBEIwlZ030Iwkk9hTEdiDsEcw02yzUx8AcxzYJS eFDr5K6BDTF+A3UTJ2TovGjK+RlcJfPd234gnYsv/oolof0t7HmiTsktcUF2pWD2QNfW 1PwQ== X-Gm-Message-State: ANoB5plhpV0QKL/JSInSr9KAKQ1QZxSibG+GpmEJONGUMEQdOR9mGr6i aAxRBT3L4WFvUhfLjOY3GtrDIw== X-Google-Smtp-Source: AA0mqf6V1Ya+qRbNkEL4R+4qw4T1RzZGjMvOBDn3H0uwg2LyeB+2u0X56U6FrtVe0C4fILlUg1/T1g== X-Received: by 2002:a05:6512:282b:b0:4b6:fdbe:773d with SMTP id cf43-20020a056512282b00b004b6fdbe773dmr6458550lfb.43.1671236254753; Fri, 16 Dec 2022 16:17:34 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:34 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 04/15] clk: qcom: gcc-qcs404: use ARRAY_SIZE instead of specifying num_parents Date: Sat, 17 Dec 2022 02:17:19 +0200 Message-Id: <20221217001730.540502-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use ARRAY_SIZE() instead of manually specifying num_parents. This makes adding/removing entries to/from parent_data/names/hws easy and errorproof. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 86 +++++++++++++++++------------------ 1 file changed, 43 insertions(+), 43 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 46d314d69250..f60a0ab42da1 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -440,7 +440,7 @@ static struct clk_rcg2 apss_ahb_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "apss_ahb_clk_src", .parent_names = gcc_parent_names_ao_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_ao_0), .flags = CLK_IS_CRITICAL, .ops = &clk_rcg2_ops, }, @@ -461,7 +461,7 @@ static struct clk_rcg2 blsp1_qup0_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup0_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -486,7 +486,7 @@ static struct clk_rcg2 blsp1_qup0_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup0_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -500,7 +500,7 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -525,7 +525,7 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -539,7 +539,7 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -565,7 +565,7 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -579,7 +579,7 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -593,7 +593,7 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -607,7 +607,7 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -621,7 +621,7 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -655,7 +655,7 @@ static struct clk_rcg2 blsp1_uart0_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart0_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -669,7 +669,7 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart1_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -683,7 +683,7 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart2_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -698,7 +698,7 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart3_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -712,7 +712,7 @@ static struct clk_rcg2 blsp2_qup0_i2c_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup0_i2c_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -726,7 +726,7 @@ static struct clk_rcg2 blsp2_qup0_spi_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup0_spi_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -740,7 +740,7 @@ static struct clk_rcg2 blsp2_uart0_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart0_apps_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -753,7 +753,7 @@ static struct clk_rcg2 byte0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "byte0_clk_src", .parent_names = gcc_parent_names_5, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_5), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -776,7 +776,7 @@ static struct clk_rcg2 emac_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "emac_clk_src", .parent_names = gcc_parent_names_4, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_4), .ops = &clk_rcg2_ops, }, }; @@ -797,7 +797,7 @@ static struct clk_rcg2 emac_ptp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "emac_ptp_clk_src", .parent_names = gcc_parent_names_4, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_4), .ops = &clk_rcg2_ops, }, }; @@ -816,7 +816,7 @@ static struct clk_rcg2 esc0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "esc0_clk_src", .parent_names = gcc_parent_names_6, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_6), .ops = &clk_rcg2_ops, }, }; @@ -850,7 +850,7 @@ static struct clk_rcg2 gfx3d_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gfx3d_clk_src", .parent_names = gcc_parent_names_7, - .num_parents = 6, + .num_parents = ARRAY_SIZE(gcc_parent_names_7), .ops = &clk_rcg2_ops, }, }; @@ -871,7 +871,7 @@ static struct clk_rcg2 gp1_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp1_clk_src", .parent_names = gcc_parent_names_2, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_2), .ops = &clk_rcg2_ops, }, }; @@ -885,7 +885,7 @@ static struct clk_rcg2 gp2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp2_clk_src", .parent_names = gcc_parent_names_2, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_2), .ops = &clk_rcg2_ops, }, }; @@ -899,7 +899,7 @@ static struct clk_rcg2 gp3_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "gp3_clk_src", .parent_names = gcc_parent_names_2, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_2), .ops = &clk_rcg2_ops, }, }; @@ -913,7 +913,7 @@ static struct clk_rcg2 hdmi_app_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_app_clk_src", .parent_names = gcc_parent_names_1, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), .ops = &clk_rcg2_ops, }, }; @@ -927,7 +927,7 @@ static struct clk_rcg2 hdmi_pclk_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_pclk_clk_src", .parent_names = gcc_parent_names_8, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_8), .ops = &clk_rcg2_ops, }, }; @@ -954,7 +954,7 @@ static struct clk_rcg2 mdp_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "mdp_clk_src", .parent_names = gcc_parent_names_9, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parent_names_9), .ops = &clk_rcg2_ops, }, }; @@ -973,7 +973,7 @@ static struct clk_rcg2 pcie_0_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pcie_0_aux_clk_src", .parent_names = gcc_parent_names_10, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_10), .ops = &clk_rcg2_ops, }, }; @@ -994,7 +994,7 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pcie_0_pipe_clk_src", .parent_names = gcc_parent_names_11, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_11), .ops = &clk_rcg2_ops, }, }; @@ -1007,7 +1007,7 @@ static struct clk_rcg2 pclk0_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pclk0_clk_src", .parent_names = gcc_parent_names_12, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_12), .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, }, @@ -1028,7 +1028,7 @@ static struct clk_rcg2 pdm2_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "pdm2_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -1056,7 +1056,7 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_apps_clk_src", .parent_names = gcc_parent_names_13, - .num_parents = 5, + .num_parents = ARRAY_SIZE(gcc_parent_names_13), .ops = &clk_rcg2_floor_ops, }, }; @@ -1076,7 +1076,7 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_ice_core_clk_src", .parent_names = gcc_parent_names_3, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_3), .ops = &clk_rcg2_ops, }, }; @@ -1102,7 +1102,7 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc2_apps_clk_src", .parent_names = gcc_parent_names_14, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_14), .ops = &clk_rcg2_floor_ops, }, }; @@ -1116,7 +1116,7 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb20_mock_utmi_clk_src", .parent_names = gcc_parent_names_1, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), .ops = &clk_rcg2_ops, }, }; @@ -1138,7 +1138,7 @@ static struct clk_rcg2 usb30_master_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_master_clk_src", .parent_names = gcc_parent_names_0, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_0), .ops = &clk_rcg2_ops, }, }; @@ -1152,7 +1152,7 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_mock_utmi_clk_src", .parent_names = gcc_parent_names_1, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), .ops = &clk_rcg2_ops, }, }; @@ -1166,7 +1166,7 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb3_phy_aux_clk_src", .parent_names = gcc_parent_names_1, - .num_parents = 2, + .num_parents = ARRAY_SIZE(gcc_parent_names_1), .ops = &clk_rcg2_ops, }, }; @@ -1189,7 +1189,7 @@ static struct clk_rcg2 usb_hs_system_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "usb_hs_system_clk_src", .parent_names = gcc_parent_names_3, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_3), .ops = &clk_rcg2_ops, }, }; @@ -1203,7 +1203,7 @@ static struct clk_rcg2 vsync_clk_src = { .clkr.hw.init = &(struct clk_init_data){ .name = "vsync_clk_src", .parent_names = gcc_parent_names_15, - .num_parents = 3, + .num_parents = ARRAY_SIZE(gcc_parent_names_15), .ops = &clk_rcg2_ops, }, }; @@ -1225,7 +1225,7 @@ static struct clk_rcg2 cdsp_bimc_clk_src = { .clkr.hw.init = &(struct clk_init_data) { .name = "cdsp_bimc_clk_src", .parent_names = gcc_parent_names_16, - .num_parents = 4, + .num_parents = ARRAY_SIZE(gcc_parent_names_16), .ops = &clk_rcg2_ops, }, }; From patchwork Sat Dec 17 00:17:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 634877 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FA26C4708D for ; Sat, 17 Dec 2022 00:24:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231307AbiLQAYE (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:35 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 05/15] clk: qcom: gcc-qcs404: disable gpll[04]_out_aux parents Date: Sat, 17 Dec 2022 02:17:20 +0200 Message-Id: <20221217001730.540502-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On the QCS404 platform the driver for the Global Clock Controller doens't define gpll0_out_aux and gpll4_out_aux clocks, so it's not possible to use them as parents. Comment out entries for these clocks. Note: backporting this patch to earlier kernels would also require a previous patch which switches the gcc driver to use ARRAY_SIZE for parent data arrays. Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404") Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index f60a0ab42da1..c48326da1bb3 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -25,11 +25,11 @@ enum { P_CORE_BI_PLL_TEST_SE, P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_DSICLK, - P_GPLL0_OUT_AUX, + /* P_GPLL0_OUT_AUX, */ P_GPLL0_OUT_MAIN, P_GPLL1_OUT_MAIN, P_GPLL3_OUT_MAIN, - P_GPLL4_OUT_AUX, + /* P_GPLL4_OUT_AUX, */ P_GPLL4_OUT_MAIN, P_GPLL6_OUT_AUX, P_HDMI_PHY_PLL_CLK, @@ -109,28 +109,28 @@ static const char * const gcc_parent_names_4[] = { static const struct parent_map gcc_parent_map_5[] = { { P_XO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, - { P_GPLL0_OUT_AUX, 2 }, + /* { P_GPLL0_OUT_AUX, 2 }, */ { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_5[] = { "cxo", "dsi0pll_byteclk_src", - "gpll0_out_aux", + /* "gpll0_out_aux", */ "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_6[] = { { P_XO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, - { P_GPLL0_OUT_AUX, 3 }, + /* { P_GPLL0_OUT_AUX, 3 }, */ { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_6[] = { "cxo", "dsi0_phy_pll_out_byteclk", - "gpll0_out_aux", + /* "gpll0_out_aux", */ "core_bi_pll_test_se", }; @@ -139,7 +139,7 @@ static const struct parent_map gcc_parent_map_7[] = { { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL3_OUT_MAIN, 2 }, { P_GPLL6_OUT_AUX, 3 }, - { P_GPLL4_OUT_AUX, 4 }, + /* { P_GPLL4_OUT_AUX, 4 }, */ { P_CORE_BI_PLL_TEST_SE, 7 }, }; @@ -148,7 +148,7 @@ static const char * const gcc_parent_names_7[] = { "gpll0_out_main", "gpll3_out_main", "gpll6_out_aux", - "gpll4_out_aux", + /* "gpll4_out_aux", */ "core_bi_pll_test_se", }; @@ -207,14 +207,14 @@ static const char * const gcc_parent_names_11[] = { static const struct parent_map gcc_parent_map_12[] = { { P_XO, 0 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, - { P_GPLL0_OUT_AUX, 2 }, + /* { P_GPLL0_OUT_AUX, 2 }, */ { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_12[] = { "cxo", "dsi0pll_pclk_src", - "gpll0_out_aux", + /* "gpll0_out_aux", */ "core_bi_pll_test_se", }; @@ -237,40 +237,40 @@ static const char * const gcc_parent_names_13[] = { static const struct parent_map gcc_parent_map_14[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL4_OUT_AUX, 2 }, + /* { P_GPLL4_OUT_AUX, 2 }, */ { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_14[] = { "cxo", "gpll0_out_main", - "gpll4_out_aux", + /* "gpll4_out_aux", */ "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_15[] = { { P_XO, 0 }, - { P_GPLL0_OUT_AUX, 2 }, + /* { P_GPLL0_OUT_AUX, 2 }, */ { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_15[] = { "cxo", - "gpll0_out_aux", + /* "gpll0_out_aux", */ "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_16[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, - { P_GPLL0_OUT_AUX, 2 }, + /* { P_GPLL0_OUT_AUX, 2 }, */ { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_16[] = { "cxo", "gpll0_out_main", - "gpll0_out_aux", + /* "gpll0_out_aux", */ "core_bi_pll_test_se", }; From patchwork Sat Dec 17 00:17:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 634874 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A562CC3DA7D for ; Sat, 17 Dec 2022 00:24:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229820AbiLQAYH (ORCPT ); Fri, 16 Dec 2022 19:24:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57678 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230181AbiLQAXK (ORCPT ); Fri, 16 Dec 2022 19:23:10 -0500 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C14877CFCF for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:35 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 06/15] clk: qcom: gcc-qcs404: fix names of the DSI clocks used as parents Date: Sat, 17 Dec 2022 02:17:21 +0200 Message-Id: <20221217001730.540502-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The QCS404 uses 28nm LPM DSI PHY, which registers dsi0pll and dsi0pllbyte clocks. Fix all DSI PHY clock names used as parents inside the GCC driver. Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404") Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index c48326da1bb3..23562096298d 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -115,7 +115,7 @@ static const struct parent_map gcc_parent_map_5[] = { static const char * const gcc_parent_names_5[] = { "cxo", - "dsi0pll_byteclk_src", + "dsi0pllbyte", /* "gpll0_out_aux", */ "core_bi_pll_test_se", }; @@ -129,7 +129,7 @@ static const struct parent_map gcc_parent_map_6[] = { static const char * const gcc_parent_names_6[] = { "cxo", - "dsi0_phy_pll_out_byteclk", + "dsi0pllbyte", /* "gpll0_out_aux", */ "core_bi_pll_test_se", }; @@ -175,7 +175,7 @@ static const struct parent_map gcc_parent_map_9[] = { static const char * const gcc_parent_names_9[] = { "cxo", "gpll0_out_main", - "dsi0_phy_pll_out_dsiclk", + "dsi0pll", "gpll6_out_aux", "core_bi_pll_test_se", }; @@ -213,7 +213,7 @@ static const struct parent_map gcc_parent_map_12[] = { static const char * const gcc_parent_names_12[] = { "cxo", - "dsi0pll_pclk_src", + "dsi0pll", /* "gpll0_out_aux", */ "core_bi_pll_test_se", }; From patchwork Sat Dec 17 00:17:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 634875 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3082FC54EBD for ; Sat, 17 Dec 2022 00:24:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230181AbiLQAYI (ORCPT ); Fri, 16 Dec 2022 19:24:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230268AbiLQAXM (ORCPT ); Fri, 16 Dec 2022 19:23:12 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 931387E292 for ; Fri, 16 Dec 2022 16:17:38 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id o6so1013319lfi.5 for ; Fri, 16 Dec 2022 16:17:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z8N5ydZapE9yeBlNhMZ07JwORTldxH5hrTYllEJ/OYg=; b=gsZ6e4ArpWVKRfXvUFCMFQaok7KPdHcbGL1SokLjFt2lfX8ObjodGKOllyyEk2wi1F Oe/BF0kYzh+jf36azDhiyscU56m/Vzlu1gZt5zWrF8/YipGZo69lgZahFKWOMBHmvYYJ jx91DRE041+fQdZb+qXNIHeHzhDPq1PqbZK1roH0KyuJWzbOw3Ac/Agj6DrCek930thV SgAvjrK9ZjJGkLZ7TSvyzbhb6iXe93UjRxbWJJTk4+TytLyU6r98WO/b0WV900XVqAbw F0HwdmUwMZA1XujLU5RIs/Z1HV+FjulU3VacvAhPhH6ok4t3TCm02mpyZLSb1zHNLUsX jNwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z8N5ydZapE9yeBlNhMZ07JwORTldxH5hrTYllEJ/OYg=; b=Kdj0gMqYOI9CfNv3FnyN8rDzZtNgwXJ2IHf+tYduG+XtyNAU1NwUiopWCPvNMcmIzP qYEzmpvwCfTNA6QlPBBOTScZov+xAr3HMLsLwKTV4jw43TdO7Rta6zCPd87/Za2Rp3g4 1v3AlAEMX/dHwOEZ4pZgNp089Tpc6VbQbv6Ilqcu8nJKd9IX79OpJ+JSSEAXpkTRdTLj TS5zq5MZIGoYjoG54/YP4vfjQhiXKVpGWjs3inaGgIgVZLHkwpXbuqCLG4PwOF9+GM26 /blinRIFOrOSlhKh/kbxRf/EYT9brkdncpFBu0R+Dle2TohWLaOLmd356PQII9owE4Em rWiA== X-Gm-Message-State: ANoB5pnmZKUDbjO1++XZRKg9v2oaoQ1MFDMiWvaclWS4xYi4JDBsAbbH 06RtwZIPUq+7Zf7AskLwzi6vSw== X-Google-Smtp-Source: AA0mqf5mg7VY7/KBkYk1y6GR4jSGPJNJQOvxLSEk/ZTtVtm0d4bfZaOx+unI/KndIl9kL0th0ZEI7Q== X-Received: by 2002:ac2:5f49:0:b0:4b6:e121:4617 with SMTP id 9-20020ac25f49000000b004b6e1214617mr7340690lfz.68.1671236256942; Fri, 16 Dec 2022 16:17:36 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:36 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 07/15] clk: qcom: gcc-qcs404: fix the name of the HDMI PLL clock Date: Sat, 17 Dec 2022 02:17:22 +0200 Message-Id: <20221217001730.540502-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The QCS404 uses 28nm HDMI PHY. The in-kernel driver doesn't provide the PLL (yet), but the out of tree patches used the name "hdmi_pll" for it. Other Qualcomm HDMI PHYs use either the name "hdmi_pll" (8960) or "hdmipll" (8996). Thus change the expected HDMI PLL clock name to "hdmi_pll". Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/gcc-qcs404.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 23562096298d..5636c6524d0f 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -160,7 +160,7 @@ static const struct parent_map gcc_parent_map_8[] = { static const char * const gcc_parent_names_8[] = { "cxo", - "hdmi_phy_pll_clk", + "hdmi_pll", "core_bi_pll_test_se", }; From patchwork Sat Dec 17 00:17:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 634876 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56A94C4708D for ; Sat, 17 Dec 2022 00:24:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230203AbiLQAYG (ORCPT ); Fri, 16 Dec 2022 19:24:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230194AbiLQAXL (ORCPT ); Fri, 16 Dec 2022 19:23:11 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4755D7CFF1 for ; Fri, 16 Dec 2022 16:17:38 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id q6so5856399lfm.10 for ; Fri, 16 Dec 2022 16:17:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ejXopAhmRRfTQDrdbh16bauZClOndTKd32RJWFyXEFU=; b=dYtsxszz6l5UcPVkjExiam2/97xRQisgIa0UB/Il4mVIiT2P252UlZw6bgMIWUFAgQ E1DVglMosZw037HOHu/bbpXq1nwUZ7Vplv2VAuO5gfgVqSgbUcmNY5IaJ1XufncEuv6p lZpuqODDXyyOceDDjEsNg0k5LoxQ9yxH9tntsg06i4SGCSmvy3avIF0UbZFNPwFsxR3I F80PDpxtbv79y0hsNxbX5Y60fAW0/AXxihbRuXS4Ui1L2Jgol8ojckIMJL+sGi7cVKQJ fhosyd63VGRs32hF9ksOqZqHebhKR+g3FuRx6dGcIxaH/zGaPPiepPlRH9iXs81wO7tY 0o+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ejXopAhmRRfTQDrdbh16bauZClOndTKd32RJWFyXEFU=; b=GEweP6wI/CXs7Q73dobF5lqOjPFdwi7SKwa86uDoBxnP3PtWy7XrNANASP3YyqXuiR R41HKGurtPShUDZSYccYuX3D5A3b+qot07Hv1btUo1AocdE8ACjZ0S8NVnfpUYMfe59M 0FZz66kqVxaOT2i27S4CPovSQbsDqwQHNy57tYACZgVm1xL7eEeeXOKOUSyv6VIP3HgD Eg/mnbPA+i+Wl8WVyYXxL/FiYMrKEWSBUVP2zKdlX5hz/eh5STK27AiV3FO1zzoIJpB1 Mv3w86dmS6q99TqakBrMerIjFUdnP6lMLJC1RjGLjjKa/F20ty2xI3C9LcNvle/F2mdR mKzw== X-Gm-Message-State: ANoB5pmlAIVmAlpYjj1uQteAR80uKdeluBDcHfT9UkCb+7zSa1Eruba0 Ur1OB7FolRPwOY3eTYy48iOEzw== X-Google-Smtp-Source: AA0mqf50aFXRjcQx+lhAftVnc/V/OyvpBQagzqCn1VULHTJ2/UKawruwu48xa0lzZ1KO1+1z24ZiPA== X-Received: by 2002:a05:6512:128e:b0:4a4:68b8:f4e5 with SMTP id u14-20020a056512128e00b004a468b8f4e5mr12619645lfs.43.1671236257843; Fri, 16 Dec 2022 16:17:37 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:37 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Stephen Boyd Subject: [PATCH 08/15] clk: qcom: gcc-qcs404: get rid of the test clock Date: Sat, 17 Dec 2022 02:17:23 +0200 Message-Id: <20221217001730.540502-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The test clock isn't in the bindings and apparently it's not used by anyone upstream. Remove it. Suggested-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 34 ---------------------------------- 1 file changed, 34 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 5636c6524d0f..fb94c57a00af 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -22,7 +22,6 @@ #include "reset.h" enum { - P_CORE_BI_PLL_TEST_SE, P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_DSICLK, /* P_GPLL0_OUT_AUX, */ @@ -41,29 +40,24 @@ enum { static const struct parent_map gcc_parent_map_0[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_0[] = { "cxo", "gpll0_out_main", - "core_bi_pll_test_se", }; static const char * const gcc_parent_names_ao_0[] = { "cxo", "gpll0_ao_out_main", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_1[] = { { P_XO, 0 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_1[] = { "cxo", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_2[] = { @@ -84,54 +78,46 @@ static const struct parent_map gcc_parent_map_3[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL6_OUT_AUX, 2 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_3[] = { "cxo", "gpll0_out_main", "gpll6_out_aux", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_4[] = { { P_XO, 0 }, { P_GPLL1_OUT_MAIN, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_4[] = { "cxo", "gpll1_out_main", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_5[] = { { P_XO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 }, /* { P_GPLL0_OUT_AUX, 2 }, */ - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_5[] = { "cxo", "dsi0pllbyte", /* "gpll0_out_aux", */ - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_6[] = { { P_XO, 0 }, { P_DSI0_PHY_PLL_OUT_BYTECLK, 2 }, /* { P_GPLL0_OUT_AUX, 3 }, */ - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_6[] = { "cxo", "dsi0pllbyte", /* "gpll0_out_aux", */ - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_7[] = { @@ -140,7 +126,6 @@ static const struct parent_map gcc_parent_map_7[] = { { P_GPLL3_OUT_MAIN, 2 }, { P_GPLL6_OUT_AUX, 3 }, /* { P_GPLL4_OUT_AUX, 4 }, */ - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_7[] = { @@ -149,19 +134,16 @@ static const char * const gcc_parent_names_7[] = { "gpll3_out_main", "gpll6_out_aux", /* "gpll4_out_aux", */ - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_8[] = { { P_XO, 0 }, { P_HDMI_PHY_PLL_CLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_8[] = { "cxo", "hdmi_pll", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_9[] = { @@ -169,7 +151,6 @@ static const struct parent_map gcc_parent_map_9[] = { { P_GPLL0_OUT_MAIN, 1 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 2 }, { P_GPLL6_OUT_AUX, 3 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_9[] = { @@ -177,45 +158,38 @@ static const char * const gcc_parent_names_9[] = { "gpll0_out_main", "dsi0pll", "gpll6_out_aux", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_10[] = { { P_XO, 0 }, { P_SLEEP_CLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_10[] = { "cxo", "sleep_clk", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_11[] = { { P_XO, 0 }, { P_PCIE_0_PIPE_CLK, 1 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_11[] = { "cxo", "pcie_0_pipe_clk", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_12[] = { { P_XO, 0 }, { P_DSI0_PHY_PLL_OUT_DSICLK, 1 }, /* { P_GPLL0_OUT_AUX, 2 }, */ - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_12[] = { "cxo", "dsi0pll", /* "gpll0_out_aux", */ - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_13[] = { @@ -223,7 +197,6 @@ static const struct parent_map gcc_parent_map_13[] = { { P_GPLL0_OUT_MAIN, 1 }, { P_GPLL4_OUT_MAIN, 2 }, { P_GPLL6_OUT_AUX, 3 }, - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_13[] = { @@ -231,47 +204,40 @@ static const char * const gcc_parent_names_13[] = { "gpll0_out_main", "gpll4_out_main", "gpll6_out_aux", - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_14[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, /* { P_GPLL4_OUT_AUX, 2 }, */ - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_14[] = { "cxo", "gpll0_out_main", /* "gpll4_out_aux", */ - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_15[] = { { P_XO, 0 }, /* { P_GPLL0_OUT_AUX, 2 }, */ - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_15[] = { "cxo", /* "gpll0_out_aux", */ - "core_bi_pll_test_se", }; static const struct parent_map gcc_parent_map_16[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, /* { P_GPLL0_OUT_AUX, 2 }, */ - { P_CORE_BI_PLL_TEST_SE, 7 }, }; static const char * const gcc_parent_names_16[] = { "cxo", "gpll0_out_main", /* "gpll0_out_aux", */ - "core_bi_pll_test_se", }; static struct clk_fixed_factor cxo = { From patchwork Sat Dec 17 00:17:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 634988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 840E4C54EBF for ; Sat, 17 Dec 2022 00:24:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230305AbiLQAYK (ORCPT ); Fri, 16 Dec 2022 19:24:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230299AbiLQAXP (ORCPT ); Fri, 16 Dec 2022 19:23:15 -0500 Received: from mail-lf1-x129.google.com (mail-lf1-x129.google.com [IPv6:2a00:1450:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8D6D666C2A for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:38 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 09/15] clk: qcom: gcc-qcs404: move PLL clocks up Date: Sat, 17 Dec 2022 02:17:24 +0200 Message-Id: <20221217001730.540502-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move PLL clock declarations up, before clock parent tables, so that we can use pll hw clock fields in the next commit. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 298 +++++++++++++++++----------------- 1 file changed, 149 insertions(+), 149 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index fb94c57a00af..5ae7a6b2a326 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -37,6 +37,155 @@ enum { P_XO, }; +static struct clk_fixed_factor cxo = { + .mult = 1, + .div = 1, + .hw.init = &(struct clk_init_data){ + .name = "cxo", + .parent_names = (const char *[]){ "xo-board" }, + .num_parents = 1, + .ops = &clk_fixed_factor_ops, + }, +}; + +static struct clk_alpha_pll gpll0_sleep_clk_src = { + .offset = 0x21000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x45008, + .enable_mask = BIT(23), + .enable_is_inverted = true, + .hw.init = &(struct clk_init_data){ + .name = "gpll0_sleep_clk_src", + .parent_names = (const char *[]){ "cxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll0_out_main = { + .offset = 0x21000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .flags = SUPPORTS_FSM_MODE, + .clkr = { + .enable_reg = 0x45000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_out_main", + .parent_names = (const char *[]) + { "cxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll0_ao_out_main = { + .offset = 0x21000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .flags = SUPPORTS_FSM_MODE, + .clkr = { + .enable_reg = 0x45000, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "gpll0_ao_out_main", + .parent_names = (const char *[]){ "cxo" }, + .num_parents = 1, + .flags = CLK_IS_CRITICAL, + .ops = &clk_alpha_pll_fixed_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll1_out_main = { + .offset = 0x20000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x45000, + .enable_mask = BIT(1), + .hw.init = &(struct clk_init_data){ + .name = "gpll1_out_main", + .parent_names = (const char *[]){ "cxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +/* 930MHz configuration */ +static const struct alpha_pll_config gpll3_config = { + .l = 48, + .alpha = 0x0, + .alpha_en_mask = BIT(24), + .post_div_mask = 0xf << 8, + .post_div_val = 0x1 << 8, + .vco_mask = 0x3 << 20, + .main_output_mask = 0x1, + .config_ctl_val = 0x4001055b, +}; + +static const struct pll_vco gpll3_vco[] = { + { 700000000, 1400000000, 0 }, +}; + +static struct clk_alpha_pll gpll3_out_main = { + .offset = 0x22000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .vco_table = gpll3_vco, + .num_vco = ARRAY_SIZE(gpll3_vco), + .clkr = { + .hw.init = &(struct clk_init_data){ + .name = "gpll3_out_main", + .parent_names = (const char *[]){ "cxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_alpha_pll gpll4_out_main = { + .offset = 0x24000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .clkr = { + .enable_reg = 0x45000, + .enable_mask = BIT(5), + .hw.init = &(struct clk_init_data){ + .name = "gpll4_out_main", + .parent_names = (const char *[]){ "cxo" }, + .num_parents = 1, + .ops = &clk_alpha_pll_ops, + }, + }, +}; + +static struct clk_pll gpll6 = { + .l_reg = 0x37004, + .m_reg = 0x37008, + .n_reg = 0x3700C, + .config_reg = 0x37014, + .mode_reg = 0x37000, + .status_reg = 0x3701C, + .status_bit = 17, + .clkr.hw.init = &(struct clk_init_data){ + .name = "gpll6", + .parent_names = (const char *[]){ "cxo" }, + .num_parents = 1, + .ops = &clk_pll_ops, + }, +}; + +static struct clk_regmap gpll6_out_aux = { + .enable_reg = 0x45000, + .enable_mask = BIT(7), + .hw.init = &(struct clk_init_data){ + .name = "gpll6_out_aux", + .parent_names = (const char *[]){ "gpll6" }, + .num_parents = 1, + .ops = &clk_pll_vote_ops, + }, +}; + static const struct parent_map gcc_parent_map_0[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, @@ -240,155 +389,6 @@ static const char * const gcc_parent_names_16[] = { /* "gpll0_out_aux", */ }; -static struct clk_fixed_factor cxo = { - .mult = 1, - .div = 1, - .hw.init = &(struct clk_init_data){ - .name = "cxo", - .parent_names = (const char *[]){ "xo-board" }, - .num_parents = 1, - .ops = &clk_fixed_factor_ops, - }, -}; - -static struct clk_alpha_pll gpll0_sleep_clk_src = { - .offset = 0x21000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], - .clkr = { - .enable_reg = 0x45008, - .enable_mask = BIT(23), - .enable_is_inverted = true, - .hw.init = &(struct clk_init_data){ - .name = "gpll0_sleep_clk_src", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - }, - }, -}; - -static struct clk_alpha_pll gpll0_out_main = { - .offset = 0x21000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], - .flags = SUPPORTS_FSM_MODE, - .clkr = { - .enable_reg = 0x45000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpll0_out_main", - .parent_names = (const char *[]) - { "cxo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - }, - }, -}; - -static struct clk_alpha_pll gpll0_ao_out_main = { - .offset = 0x21000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], - .flags = SUPPORTS_FSM_MODE, - .clkr = { - .enable_reg = 0x45000, - .enable_mask = BIT(0), - .hw.init = &(struct clk_init_data){ - .name = "gpll0_ao_out_main", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, - .flags = CLK_IS_CRITICAL, - .ops = &clk_alpha_pll_fixed_ops, - }, - }, -}; - -static struct clk_alpha_pll gpll1_out_main = { - .offset = 0x20000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], - .clkr = { - .enable_reg = 0x45000, - .enable_mask = BIT(1), - .hw.init = &(struct clk_init_data){ - .name = "gpll1_out_main", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - }, - }, -}; - -/* 930MHz configuration */ -static const struct alpha_pll_config gpll3_config = { - .l = 48, - .alpha = 0x0, - .alpha_en_mask = BIT(24), - .post_div_mask = 0xf << 8, - .post_div_val = 0x1 << 8, - .vco_mask = 0x3 << 20, - .main_output_mask = 0x1, - .config_ctl_val = 0x4001055b, -}; - -static const struct pll_vco gpll3_vco[] = { - { 700000000, 1400000000, 0 }, -}; - -static struct clk_alpha_pll gpll3_out_main = { - .offset = 0x22000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], - .vco_table = gpll3_vco, - .num_vco = ARRAY_SIZE(gpll3_vco), - .clkr = { - .hw.init = &(struct clk_init_data){ - .name = "gpll3_out_main", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - }, - }, -}; - -static struct clk_alpha_pll gpll4_out_main = { - .offset = 0x24000, - .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], - .clkr = { - .enable_reg = 0x45000, - .enable_mask = BIT(5), - .hw.init = &(struct clk_init_data){ - .name = "gpll4_out_main", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, - .ops = &clk_alpha_pll_ops, - }, - }, -}; - -static struct clk_pll gpll6 = { - .l_reg = 0x37004, - .m_reg = 0x37008, - .n_reg = 0x3700C, - .config_reg = 0x37014, - .mode_reg = 0x37000, - .status_reg = 0x3701C, - .status_bit = 17, - .clkr.hw.init = &(struct clk_init_data){ - .name = "gpll6", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, - .ops = &clk_pll_ops, - }, -}; - -static struct clk_regmap gpll6_out_aux = { - .enable_reg = 0x45000, - .enable_mask = BIT(7), - .hw.init = &(struct clk_init_data){ - .name = "gpll6_out_aux", - .parent_names = (const char *[]){ "gpll6" }, - .num_parents = 1, - .ops = &clk_pll_vote_ops, - }, -}; - static const struct freq_tbl ftbl_apss_ahb_clk_src[] = { F(19200000, P_XO, 1, 0, 0), F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0), From patchwork Sat Dec 17 00:17:25 2022 Content-Type: text/plain; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:39 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 10/15] clk: qcom: gcc-qcs404: use parent_hws/_data instead of parent_names Date: Sat, 17 Dec 2022 02:17:25 +0200 Message-Id: <20221217001730.540502-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 515 ++++++++++++++++++---------------- 1 file changed, 266 insertions(+), 249 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 5ae7a6b2a326..3941175d73a5 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -42,7 +42,9 @@ static struct clk_fixed_factor cxo = { .div = 1, .hw.init = &(struct clk_init_data){ .name = "cxo", - .parent_names = (const char *[]){ "xo-board" }, + .parent_data = &(const struct clk_parent_data) { + .name = "xo-board", + }, .num_parents = 1, .ops = &clk_fixed_factor_ops, }, @@ -57,7 +59,9 @@ static struct clk_alpha_pll gpll0_sleep_clk_src = { .enable_is_inverted = true, .hw.init = &(struct clk_init_data){ .name = "gpll0_sleep_clk_src", - .parent_names = (const char *[]){ "cxo" }, + .parent_data = &(const struct clk_parent_data) { + .hw = &cxo.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -73,8 +77,9 @@ static struct clk_alpha_pll gpll0_out_main = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpll0_out_main", - .parent_names = (const char *[]) - { "cxo" }, + .parent_data = &(const struct clk_parent_data) { + .hw = &cxo.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -90,7 +95,9 @@ static struct clk_alpha_pll gpll0_ao_out_main = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpll0_ao_out_main", - .parent_names = (const char *[]){ "cxo" }, + .parent_data = &(const struct clk_parent_data) { + .hw = &cxo.hw, + }, .num_parents = 1, .flags = CLK_IS_CRITICAL, .ops = &clk_alpha_pll_fixed_ops, @@ -106,7 +113,9 @@ static struct clk_alpha_pll gpll1_out_main = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gpll1_out_main", - .parent_names = (const char *[]){ "cxo" }, + .parent_data = &(const struct clk_parent_data) { + .hw = &cxo.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -137,7 +146,9 @@ static struct clk_alpha_pll gpll3_out_main = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "gpll3_out_main", - .parent_names = (const char *[]){ "cxo" }, + .parent_data = &(const struct clk_parent_data) { + .hw = &cxo.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -152,7 +163,9 @@ static struct clk_alpha_pll gpll4_out_main = { .enable_mask = BIT(5), .hw.init = &(struct clk_init_data){ .name = "gpll4_out_main", - .parent_names = (const char *[]){ "cxo" }, + .parent_data = &(const struct clk_parent_data) { + .hw = &cxo.hw, + }, .num_parents = 1, .ops = &clk_alpha_pll_ops, }, @@ -169,7 +182,9 @@ static struct clk_pll gpll6 = { .status_bit = 17, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll6", - .parent_names = (const char *[]){ "cxo" }, + .parent_data = &(const struct clk_parent_data) { + .hw = &cxo.hw, + }, .num_parents = 1, .ops = &clk_pll_ops, }, @@ -180,7 +195,9 @@ static struct clk_regmap gpll6_out_aux = { .enable_mask = BIT(7), .hw.init = &(struct clk_init_data){ .name = "gpll6_out_aux", - .parent_names = (const char *[]){ "gpll6" }, + .parent_hws = (const struct clk_hw*[]) { + &gpll6.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -191,22 +208,22 @@ static const struct parent_map gcc_parent_map_0[] = { { P_GPLL0_OUT_MAIN, 1 }, }; -static const char * const gcc_parent_names_0[] = { - "cxo", - "gpll0_out_main", +static const struct clk_parent_data gcc_parent_data_0[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_out_main.clkr.hw }, }; -static const char * const gcc_parent_names_ao_0[] = { - "cxo", - "gpll0_ao_out_main", +static const struct clk_parent_data gcc_parent_data_ao_0[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_ao_out_main.clkr.hw }, }; static const struct parent_map gcc_parent_map_1[] = { { P_XO, 0 }, }; -static const char * const gcc_parent_names_1[] = { - "cxo", +static const struct clk_parent_data gcc_parent_data_1[] = { + { .hw = &cxo.hw }, }; static const struct parent_map gcc_parent_map_2[] = { @@ -216,11 +233,11 @@ static const struct parent_map gcc_parent_map_2[] = { { P_SLEEP_CLK, 6 }, }; -static const char * const gcc_parent_names_2[] = { - "cxo", - "gpll0_out_main", - "gpll6_out_aux", - "sleep_clk", +static const struct clk_parent_data gcc_parent_data_2[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_out_main.clkr.hw }, + { .hw = &gpll6_out_aux.hw }, + { .fw_name = "sleep_clk", .name = "sleep_clk" }, }; static const struct parent_map gcc_parent_map_3[] = { @@ -229,10 +246,10 @@ static const struct parent_map gcc_parent_map_3[] = { { P_GPLL6_OUT_AUX, 2 }, }; -static const char * const gcc_parent_names_3[] = { - "cxo", - "gpll0_out_main", - "gpll6_out_aux", +static const struct clk_parent_data gcc_parent_data_3[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_out_main.clkr.hw }, + { .hw = &gpll6_out_aux.hw }, }; static const struct parent_map gcc_parent_map_4[] = { @@ -240,9 +257,9 @@ static const struct parent_map gcc_parent_map_4[] = { { P_GPLL1_OUT_MAIN, 1 }, }; -static const char * const gcc_parent_names_4[] = { - "cxo", - "gpll1_out_main", +static const struct clk_parent_data gcc_parent_data_4[] = { + { .hw = &cxo.hw }, + { .hw = &gpll1_out_main.clkr.hw }, }; static const struct parent_map gcc_parent_map_5[] = { @@ -251,9 +268,9 @@ static const struct parent_map gcc_parent_map_5[] = { /* { P_GPLL0_OUT_AUX, 2 }, */ }; -static const char * const gcc_parent_names_5[] = { - "cxo", - "dsi0pllbyte", +static const struct clk_parent_data gcc_parent_data_5[] = { + { .hw = &cxo.hw }, + { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" }, /* "gpll0_out_aux", */ }; @@ -263,9 +280,9 @@ static const struct parent_map gcc_parent_map_6[] = { /* { P_GPLL0_OUT_AUX, 3 }, */ }; -static const char * const gcc_parent_names_6[] = { - "cxo", - "dsi0pllbyte", +static const struct clk_parent_data gcc_parent_data_6[] = { + { .hw = &cxo.hw }, + { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" }, /* "gpll0_out_aux", */ }; @@ -277,11 +294,11 @@ static const struct parent_map gcc_parent_map_7[] = { /* { P_GPLL4_OUT_AUX, 4 }, */ }; -static const char * const gcc_parent_names_7[] = { - "cxo", - "gpll0_out_main", - "gpll3_out_main", - "gpll6_out_aux", +static const struct clk_parent_data gcc_parent_data_7[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_out_main.clkr.hw }, + { .hw = &gpll3_out_main.clkr.hw }, + { .hw = &gpll6_out_aux.hw }, /* "gpll4_out_aux", */ }; @@ -290,9 +307,9 @@ static const struct parent_map gcc_parent_map_8[] = { { P_HDMI_PHY_PLL_CLK, 1 }, }; -static const char * const gcc_parent_names_8[] = { - "cxo", - "hdmi_pll", +static const struct clk_parent_data gcc_parent_data_8[] = { + { .hw = &cxo.hw }, + { .fw_name = "hdmi_pll", .name = "hdmi_pll" }, }; static const struct parent_map gcc_parent_map_9[] = { @@ -302,11 +319,11 @@ static const struct parent_map gcc_parent_map_9[] = { { P_GPLL6_OUT_AUX, 3 }, }; -static const char * const gcc_parent_names_9[] = { - "cxo", - "gpll0_out_main", - "dsi0pll", - "gpll6_out_aux", +static const struct clk_parent_data gcc_parent_data_9[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_out_main.clkr.hw }, + { .fw_name = "dsi0pll", .name = "dsi0pll" }, + { .hw = &gpll6_out_aux.hw }, }; static const struct parent_map gcc_parent_map_10[] = { @@ -314,9 +331,9 @@ static const struct parent_map gcc_parent_map_10[] = { { P_SLEEP_CLK, 1 }, }; -static const char * const gcc_parent_names_10[] = { - "cxo", - "sleep_clk", +static const struct clk_parent_data gcc_parent_data_10[] = { + { .hw = &cxo.hw }, + { .fw_name = "sleep_clk", .name = "sleep_clk" }, }; static const struct parent_map gcc_parent_map_11[] = { @@ -324,9 +341,9 @@ static const struct parent_map gcc_parent_map_11[] = { { P_PCIE_0_PIPE_CLK, 1 }, }; -static const char * const gcc_parent_names_11[] = { - "cxo", - "pcie_0_pipe_clk", +static const struct clk_parent_data gcc_parent_data_11[] = { + { .hw = &cxo.hw }, + { .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" }, }; static const struct parent_map gcc_parent_map_12[] = { @@ -335,9 +352,9 @@ static const struct parent_map gcc_parent_map_12[] = { /* { P_GPLL0_OUT_AUX, 2 }, */ }; -static const char * const gcc_parent_names_12[] = { - "cxo", - "dsi0pll", +static const struct clk_parent_data gcc_parent_data_12[] = { + { .hw = &cxo.hw }, + { .fw_name = "dsi0pll", .name = "dsi0pll" }, /* "gpll0_out_aux", */ }; @@ -348,11 +365,11 @@ static const struct parent_map gcc_parent_map_13[] = { { P_GPLL6_OUT_AUX, 3 }, }; -static const char * const gcc_parent_names_13[] = { - "cxo", - "gpll0_out_main", - "gpll4_out_main", - "gpll6_out_aux", +static const struct clk_parent_data gcc_parent_data_13[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_out_main.clkr.hw }, + { .hw = &gpll4_out_main.clkr.hw }, + { .hw = &gpll6_out_aux.hw }, }; static const struct parent_map gcc_parent_map_14[] = { @@ -361,9 +378,9 @@ static const struct parent_map gcc_parent_map_14[] = { /* { P_GPLL4_OUT_AUX, 2 }, */ }; -static const char * const gcc_parent_names_14[] = { - "cxo", - "gpll0_out_main", +static const struct clk_parent_data gcc_parent_data_14[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_out_main.clkr.hw }, /* "gpll4_out_aux", */ }; @@ -372,8 +389,8 @@ static const struct parent_map gcc_parent_map_15[] = { /* { P_GPLL0_OUT_AUX, 2 }, */ }; -static const char * const gcc_parent_names_15[] = { - "cxo", +static const struct clk_parent_data gcc_parent_data_15[] = { + { .hw = &cxo.hw }, /* "gpll0_out_aux", */ }; @@ -383,9 +400,9 @@ static const struct parent_map gcc_parent_map_16[] = { /* { P_GPLL0_OUT_AUX, 2 }, */ }; -static const char * const gcc_parent_names_16[] = { - "cxo", - "gpll0_out_main", +static const struct clk_parent_data gcc_parent_data_16[] = { + { .hw = &cxo.hw }, + { .hw = &gpll0_out_main.clkr.hw }, /* "gpll0_out_aux", */ }; @@ -405,8 +422,8 @@ static struct clk_rcg2 apss_ahb_clk_src = { .freq_tbl = ftbl_apss_ahb_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "apss_ahb_clk_src", - .parent_names = gcc_parent_names_ao_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_ao_0), + .parent_data = gcc_parent_data_ao_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_ao_0), .flags = CLK_IS_CRITICAL, .ops = &clk_rcg2_ops, }, @@ -426,8 +443,8 @@ static struct clk_rcg2 blsp1_qup0_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup0_i2c_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -451,8 +468,8 @@ static struct clk_rcg2 blsp1_qup0_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup0_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -465,8 +482,8 @@ static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_i2c_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -490,8 +507,8 @@ static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup1_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -504,8 +521,8 @@ static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_i2c_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -530,8 +547,8 @@ static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup2_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -544,8 +561,8 @@ static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_i2c_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -558,8 +575,8 @@ static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup3_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -572,8 +589,8 @@ static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_i2c_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -586,8 +603,8 @@ static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_qup4_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -620,8 +637,8 @@ static struct clk_rcg2 blsp1_uart0_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart0_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart0_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -634,8 +651,8 @@ static struct clk_rcg2 blsp1_uart1_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart0_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart1_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -648,8 +665,8 @@ static struct clk_rcg2 blsp1_uart2_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart0_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart2_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -663,8 +680,8 @@ static struct clk_rcg2 blsp1_uart3_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart0_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp1_uart3_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -677,8 +694,8 @@ static struct clk_rcg2 blsp2_qup0_i2c_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_i2c_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup0_i2c_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -691,8 +708,8 @@ static struct clk_rcg2 blsp2_qup0_spi_apps_clk_src = { .freq_tbl = ftbl_blsp1_qup0_spi_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_qup0_spi_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -705,8 +722,8 @@ static struct clk_rcg2 blsp2_uart0_apps_clk_src = { .freq_tbl = ftbl_blsp1_uart0_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "blsp2_uart0_apps_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -718,8 +735,8 @@ static struct clk_rcg2 byte0_clk_src = { .parent_map = gcc_parent_map_5, .clkr.hw.init = &(struct clk_init_data){ .name = "byte0_clk_src", - .parent_names = gcc_parent_names_5, - .num_parents = ARRAY_SIZE(gcc_parent_names_5), + .parent_data = gcc_parent_data_5, + .num_parents = ARRAY_SIZE(gcc_parent_data_5), .flags = CLK_SET_RATE_PARENT, .ops = &clk_byte2_ops, }, @@ -741,8 +758,8 @@ static struct clk_rcg2 emac_clk_src = { .freq_tbl = ftbl_emac_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "emac_clk_src", - .parent_names = gcc_parent_names_4, - .num_parents = ARRAY_SIZE(gcc_parent_names_4), + .parent_data = gcc_parent_data_4, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), .ops = &clk_rcg2_ops, }, }; @@ -762,8 +779,8 @@ static struct clk_rcg2 emac_ptp_clk_src = { .freq_tbl = ftbl_emac_ptp_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "emac_ptp_clk_src", - .parent_names = gcc_parent_names_4, - .num_parents = ARRAY_SIZE(gcc_parent_names_4), + .parent_data = gcc_parent_data_4, + .num_parents = ARRAY_SIZE(gcc_parent_data_4), .ops = &clk_rcg2_ops, }, }; @@ -781,8 +798,8 @@ static struct clk_rcg2 esc0_clk_src = { .freq_tbl = ftbl_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "esc0_clk_src", - .parent_names = gcc_parent_names_6, - .num_parents = ARRAY_SIZE(gcc_parent_names_6), + .parent_data = gcc_parent_data_6, + .num_parents = ARRAY_SIZE(gcc_parent_data_6), .ops = &clk_rcg2_ops, }, }; @@ -815,8 +832,8 @@ static struct clk_rcg2 gfx3d_clk_src = { .freq_tbl = ftbl_gfx3d_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gfx3d_clk_src", - .parent_names = gcc_parent_names_7, - .num_parents = ARRAY_SIZE(gcc_parent_names_7), + .parent_data = gcc_parent_data_7, + .num_parents = ARRAY_SIZE(gcc_parent_data_7), .ops = &clk_rcg2_ops, }, }; @@ -836,8 +853,8 @@ static struct clk_rcg2 gp1_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp1_clk_src", - .parent_names = gcc_parent_names_2, - .num_parents = ARRAY_SIZE(gcc_parent_names_2), + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; @@ -850,8 +867,8 @@ static struct clk_rcg2 gp2_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp2_clk_src", - .parent_names = gcc_parent_names_2, - .num_parents = ARRAY_SIZE(gcc_parent_names_2), + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; @@ -864,8 +881,8 @@ static struct clk_rcg2 gp3_clk_src = { .freq_tbl = ftbl_gp1_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gp3_clk_src", - .parent_names = gcc_parent_names_2, - .num_parents = ARRAY_SIZE(gcc_parent_names_2), + .parent_data = gcc_parent_data_2, + .num_parents = ARRAY_SIZE(gcc_parent_data_2), .ops = &clk_rcg2_ops, }, }; @@ -878,8 +895,8 @@ static struct clk_rcg2 hdmi_app_clk_src = { .freq_tbl = ftbl_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_app_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = ARRAY_SIZE(gcc_parent_names_1), + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; @@ -892,8 +909,8 @@ static struct clk_rcg2 hdmi_pclk_clk_src = { .freq_tbl = ftbl_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "hdmi_pclk_clk_src", - .parent_names = gcc_parent_names_8, - .num_parents = ARRAY_SIZE(gcc_parent_names_8), + .parent_data = gcc_parent_data_8, + .num_parents = ARRAY_SIZE(gcc_parent_data_8), .ops = &clk_rcg2_ops, }, }; @@ -919,8 +936,8 @@ static struct clk_rcg2 mdp_clk_src = { .freq_tbl = ftbl_mdp_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "mdp_clk_src", - .parent_names = gcc_parent_names_9, - .num_parents = ARRAY_SIZE(gcc_parent_names_9), + .parent_data = gcc_parent_data_9, + .num_parents = ARRAY_SIZE(gcc_parent_data_9), .ops = &clk_rcg2_ops, }, }; @@ -938,8 +955,8 @@ static struct clk_rcg2 pcie_0_aux_clk_src = { .freq_tbl = ftbl_pcie_0_aux_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "pcie_0_aux_clk_src", - .parent_names = gcc_parent_names_10, - .num_parents = ARRAY_SIZE(gcc_parent_names_10), + .parent_data = gcc_parent_data_10, + .num_parents = ARRAY_SIZE(gcc_parent_data_10), .ops = &clk_rcg2_ops, }, }; @@ -959,8 +976,8 @@ static struct clk_rcg2 pcie_0_pipe_clk_src = { .freq_tbl = ftbl_pcie_0_pipe_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "pcie_0_pipe_clk_src", - .parent_names = gcc_parent_names_11, - .num_parents = ARRAY_SIZE(gcc_parent_names_11), + .parent_data = gcc_parent_data_11, + .num_parents = ARRAY_SIZE(gcc_parent_data_11), .ops = &clk_rcg2_ops, }, }; @@ -972,8 +989,8 @@ static struct clk_rcg2 pclk0_clk_src = { .parent_map = gcc_parent_map_12, .clkr.hw.init = &(struct clk_init_data){ .name = "pclk0_clk_src", - .parent_names = gcc_parent_names_12, - .num_parents = ARRAY_SIZE(gcc_parent_names_12), + .parent_data = gcc_parent_data_12, + .num_parents = ARRAY_SIZE(gcc_parent_data_12), .flags = CLK_SET_RATE_PARENT, .ops = &clk_pixel_ops, }, @@ -993,8 +1010,8 @@ static struct clk_rcg2 pdm2_clk_src = { .freq_tbl = ftbl_pdm2_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "pdm2_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -1021,8 +1038,8 @@ static struct clk_rcg2 sdcc1_apps_clk_src = { .freq_tbl = ftbl_sdcc1_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_apps_clk_src", - .parent_names = gcc_parent_names_13, - .num_parents = ARRAY_SIZE(gcc_parent_names_13), + .parent_data = gcc_parent_data_13, + .num_parents = ARRAY_SIZE(gcc_parent_data_13), .ops = &clk_rcg2_floor_ops, }, }; @@ -1041,8 +1058,8 @@ static struct clk_rcg2 sdcc1_ice_core_clk_src = { .freq_tbl = ftbl_sdcc1_ice_core_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc1_ice_core_clk_src", - .parent_names = gcc_parent_names_3, - .num_parents = ARRAY_SIZE(gcc_parent_names_3), + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), .ops = &clk_rcg2_ops, }, }; @@ -1067,8 +1084,8 @@ static struct clk_rcg2 sdcc2_apps_clk_src = { .freq_tbl = ftbl_sdcc2_apps_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "sdcc2_apps_clk_src", - .parent_names = gcc_parent_names_14, - .num_parents = ARRAY_SIZE(gcc_parent_names_14), + .parent_data = gcc_parent_data_14, + .num_parents = ARRAY_SIZE(gcc_parent_data_14), .ops = &clk_rcg2_floor_ops, }, }; @@ -1081,8 +1098,8 @@ static struct clk_rcg2 usb20_mock_utmi_clk_src = { .freq_tbl = ftbl_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb20_mock_utmi_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = ARRAY_SIZE(gcc_parent_names_1), + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; @@ -1103,8 +1120,8 @@ static struct clk_rcg2 usb30_master_clk_src = { .freq_tbl = ftbl_usb30_master_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_master_clk_src", - .parent_names = gcc_parent_names_0, - .num_parents = ARRAY_SIZE(gcc_parent_names_0), + .parent_data = gcc_parent_data_0, + .num_parents = ARRAY_SIZE(gcc_parent_data_0), .ops = &clk_rcg2_ops, }, }; @@ -1117,8 +1134,8 @@ static struct clk_rcg2 usb30_mock_utmi_clk_src = { .freq_tbl = ftbl_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb30_mock_utmi_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = ARRAY_SIZE(gcc_parent_names_1), + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; @@ -1131,8 +1148,8 @@ static struct clk_rcg2 usb3_phy_aux_clk_src = { .freq_tbl = ftbl_pcie_0_aux_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb3_phy_aux_clk_src", - .parent_names = gcc_parent_names_1, - .num_parents = ARRAY_SIZE(gcc_parent_names_1), + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_rcg2_ops, }, }; @@ -1154,8 +1171,8 @@ static struct clk_rcg2 usb_hs_system_clk_src = { .freq_tbl = ftbl_usb_hs_system_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "usb_hs_system_clk_src", - .parent_names = gcc_parent_names_3, - .num_parents = ARRAY_SIZE(gcc_parent_names_3), + .parent_data = gcc_parent_data_3, + .num_parents = ARRAY_SIZE(gcc_parent_data_3), .ops = &clk_rcg2_ops, }, }; @@ -1168,8 +1185,8 @@ static struct clk_rcg2 vsync_clk_src = { .freq_tbl = ftbl_esc0_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "vsync_clk_src", - .parent_names = gcc_parent_names_15, - .num_parents = ARRAY_SIZE(gcc_parent_names_15), + .parent_data = gcc_parent_data_15, + .num_parents = ARRAY_SIZE(gcc_parent_data_15), .ops = &clk_rcg2_ops, }, }; @@ -1190,8 +1207,8 @@ static struct clk_rcg2 cdsp_bimc_clk_src = { .freq_tbl = ftbl_cdsp_bimc_clk_src, .clkr.hw.init = &(struct clk_init_data) { .name = "cdsp_bimc_clk_src", - .parent_names = gcc_parent_names_16, - .num_parents = ARRAY_SIZE(gcc_parent_names_16), + .parent_data = gcc_parent_data_16, + .num_parents = ARRAY_SIZE(gcc_parent_data_16), .ops = &clk_rcg2_ops, }, }; @@ -1204,8 +1221,8 @@ static struct clk_branch gcc_apss_ahb_clk = { .enable_mask = BIT(14), .hw.init = &(struct clk_init_data){ .name = "gcc_apss_ahb_clk", - .parent_names = (const char *[]){ - "apss_ahb_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &apss_ahb_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1236,8 +1253,8 @@ static struct clk_branch gcc_bimc_gfx_clk = { .hw.init = &(struct clk_init_data){ .name = "gcc_bimc_gfx_clk", .ops = &clk_branch2_ops, - .parent_names = (const char *[]){ - "gcc_apss_tcu_clk", + .parent_hws = (const struct clk_hw*[]) { + &gcc_apss_tcu_clk.clkr.hw, }, }, @@ -1265,8 +1282,8 @@ static struct clk_branch gcc_bimc_cdsp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data) { .name = "gcc_bimc_cdsp_clk", - .parent_names = (const char *[]) { - "cdsp_bimc_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &cdsp_bimc_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1335,8 +1352,8 @@ static struct clk_branch gcc_blsp1_qup0_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup0_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup0_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup0_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1353,8 +1370,8 @@ static struct clk_branch gcc_blsp1_qup0_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup0_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup0_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup0_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1371,8 +1388,8 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup1_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup1_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup1_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1389,8 +1406,8 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup1_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup1_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup1_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1407,8 +1424,8 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup2_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup2_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup2_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1425,8 +1442,8 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup2_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup2_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup2_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1443,8 +1460,8 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup3_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup3_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup3_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1461,8 +1478,8 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup3_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup3_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup3_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1479,8 +1496,8 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup4_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup4_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup4_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1497,8 +1514,8 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_qup4_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp1_qup4_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_qup4_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1515,8 +1532,8 @@ static struct clk_branch gcc_blsp1_uart0_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart0_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart0_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_uart0_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1533,8 +1550,8 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart1_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart1_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_uart1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1551,8 +1568,8 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart2_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart2_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_uart2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1569,8 +1586,8 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp1_uart3_apps_clk", - .parent_names = (const char *[]){ - "blsp1_uart3_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp1_uart3_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1600,8 +1617,8 @@ static struct clk_branch gcc_blsp2_qup0_i2c_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup0_i2c_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup0_i2c_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp2_qup0_i2c_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1618,8 +1635,8 @@ static struct clk_branch gcc_blsp2_qup0_spi_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_qup0_spi_apps_clk", - .parent_names = (const char *[]){ - "blsp2_qup0_spi_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp2_qup0_spi_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1636,8 +1653,8 @@ static struct clk_branch gcc_blsp2_uart0_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_blsp2_uart0_apps_clk", - .parent_names = (const char *[]){ - "blsp2_uart0_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &blsp2_uart0_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1719,8 +1736,8 @@ static struct clk_branch gcc_eth_ptp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_eth_ptp_clk", - .parent_names = (const char *[]){ - "emac_ptp_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &emac_ptp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1737,8 +1754,8 @@ static struct clk_branch gcc_eth_rgmii_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_eth_rgmii_clk", - .parent_names = (const char *[]){ - "emac_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &emac_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1820,8 +1837,8 @@ static struct clk_branch gcc_cdsp_tbu_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data) { .name = "gcc_cdsp_tbu_clk", - .parent_names = (const char *[]) { - "cdsp_bimc_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &cdsp_bimc_clk_src.clkr.hw }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1838,8 +1855,8 @@ static struct clk_branch gcc_gp1_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp1_clk", - .parent_names = (const char *[]){ - "gp1_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gp1_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1856,8 +1873,8 @@ static struct clk_branch gcc_gp2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp2_clk", - .parent_names = (const char *[]){ - "gp2_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gp2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1874,8 +1891,8 @@ static struct clk_branch gcc_gp3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_gp3_clk", - .parent_names = (const char *[]){ - "gp3_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gp3_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1944,8 +1961,8 @@ static struct clk_branch gcc_mdss_byte0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mdss_byte0_clk", - .parent_names = (const char *[]){ - "byte0_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &byte0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1962,8 +1979,8 @@ static struct clk_branch gcc_mdss_esc0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mdss_esc0_clk", - .parent_names = (const char *[]){ - "esc0_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &esc0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1980,8 +1997,8 @@ static struct clk_branch gcc_mdss_hdmi_app_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mdss_hdmi_app_clk", - .parent_names = (const char *[]){ - "hdmi_app_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &hdmi_app_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -1998,8 +2015,8 @@ static struct clk_branch gcc_mdss_hdmi_pclk_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mdss_hdmi_pclk_clk", - .parent_names = (const char *[]){ - "hdmi_pclk_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &hdmi_pclk_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2016,8 +2033,8 @@ static struct clk_branch gcc_mdss_mdp_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mdss_mdp_clk", - .parent_names = (const char *[]){ - "mdp_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &mdp_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2034,8 +2051,8 @@ static struct clk_branch gcc_mdss_pclk0_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mdss_pclk0_clk", - .parent_names = (const char *[]){ - "pclk0_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &pclk0_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2052,8 +2069,8 @@ static struct clk_branch gcc_mdss_vsync_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_mdss_vsync_clk", - .parent_names = (const char *[]){ - "vsync_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &vsync_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2083,8 +2100,8 @@ static struct clk_branch gcc_oxili_gfx3d_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_oxili_gfx3d_clk", - .parent_names = (const char *[]){ - "gfx3d_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &gfx3d_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2101,8 +2118,8 @@ static struct clk_branch gcc_pcie_0_aux_clk = { .enable_mask = BIT(27), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_aux_clk", - .parent_names = (const char *[]){ - "pcie_0_aux_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &pcie_0_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2145,8 +2162,8 @@ static struct clk_branch gcc_pcie_0_pipe_clk = { .enable_mask = BIT(28), .hw.init = &(struct clk_init_data){ .name = "gcc_pcie_0_pipe_clk", - .parent_names = (const char *[]){ - "pcie_0_pipe_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &pcie_0_pipe_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2204,8 +2221,8 @@ static struct clk_branch gcc_pdm2_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_pdm2_clk", - .parent_names = (const char *[]){ - "pdm2_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &pdm2_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2314,8 +2331,8 @@ static struct clk_branch gcc_sdcc1_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_apps_clk", - .parent_names = (const char *[]){ - "sdcc1_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &sdcc1_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2332,8 +2349,8 @@ static struct clk_branch gcc_sdcc1_ice_core_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc1_ice_core_clk", - .parent_names = (const char *[]){ - "sdcc1_ice_core_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &sdcc1_ice_core_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2376,8 +2393,8 @@ static struct clk_branch gcc_sdcc2_apps_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sdcc2_apps_clk", - .parent_names = (const char *[]){ - "sdcc2_apps_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &sdcc2_apps_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2407,8 +2424,8 @@ static struct clk_branch gcc_sys_noc_usb3_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_sys_noc_usb3_clk", - .parent_names = (const char *[]){ - "usb30_master_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch2_ops, @@ -2437,8 +2454,8 @@ static struct clk_branch gcc_usb20_mock_utmi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb20_mock_utmi_clk", - .parent_names = (const char *[]){ - "usb20_mock_utmi_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb20_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2468,8 +2485,8 @@ static struct clk_branch gcc_usb30_master_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_master_clk", - .parent_names = (const char *[]){ - "usb30_master_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb30_master_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2486,8 +2503,8 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb30_mock_utmi_clk", - .parent_names = (const char *[]){ - "usb30_mock_utmi_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb30_mock_utmi_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2517,8 +2534,8 @@ static struct clk_branch gcc_usb3_phy_aux_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb3_phy_aux_clk", - .parent_names = (const char *[]){ - "usb3_phy_aux_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb3_phy_aux_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, @@ -2560,8 +2577,8 @@ static struct clk_branch gcc_usb_hs_system_clk = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gcc_usb_hs_system_clk", - .parent_names = (const char *[]){ - "usb_hs_system_clk_src", + .parent_hws = (const struct clk_hw*[]) { + &usb_hs_system_clk_src.clkr.hw, }, .num_parents = 1, .flags = CLK_SET_RATE_PARENT, From patchwork Sat Dec 17 00:17:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 634872 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6E94C64981 for ; Sat, 17 Dec 2022 00:24:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230331AbiLQAYP (ORCPT ); Fri, 16 Dec 2022 19:24:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56818 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230326AbiLQAXR (ORCPT ); Fri, 16 Dec 2022 19:23:17 -0500 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1623B7E2A7 for ; Fri, 16 Dec 2022 16:17:42 -0800 (PST) Received: by mail-lf1-x12b.google.com with SMTP id bf43so5891734lfb.6 for ; Fri, 16 Dec 2022 16:17:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BOTCjV+liMFCiMVQWm/dz56fIC+0pWALeNa+WSMKaKQ=; b=feK2BzMlgVpbWgZo9xkjTvqq4h3fCQhapTO9dueMOoCtl+op2HXmPWHrCgja3GWkLq JZhN+GhPOi24/XyAO6MIF/p2BW9wygCFkwE52Ho+Xs/K6KjJcNglKOi6kYtqtbYinyOR yDd/qNocBLKeWc97Gm5z7zRlZelKl0fXGeoPIalzm2SlIJyG0IgudkOKX9AaJKR42Vs5 sF85dLr7KM9M/bY0mTwforlGocFsXWiqe8CKjHRbm2KnpdZS83BnzWu3F7G3j17XN4a4 Fc7L+bAC8ZYXso6raeP65aJ9g7EPnQ3W3vSWndjZcZeEsXwOwe0Fk29ia2uVGu3tv7z2 YnvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BOTCjV+liMFCiMVQWm/dz56fIC+0pWALeNa+WSMKaKQ=; b=D4J6f9i6eJgZHBOFMzONBXbZOJx5SUNM65qnrgutW9LQPMLSpLqWkLwGFYxQ+Z3jEn 6+Hla7kmgP26mjM/GKAkvIZW1egc09+krU/jlymERbb13XvmuO2meRD7o6DIieEGYoRA 1xnjrmVcns5LrZp++8ttTkbZNp9qeWiaVsABPV0ke9KdBsjoo4dokfyrV8QJAbDVuwLB khSdQhu1bDgFTgU78jH/kn6Dk52E++/lzQQZUWmkmB1okfEm9u5RIxHU8rmbMFIgSx7D O+LIEqzLvN5P6PnQxHsVQRSMuWUBXjBWdHciHfvG/9rXEtW3l9WfvqxWEQYRTaHYVZxP tH8g== X-Gm-Message-State: ANoB5pkYXjmeF2bwPOqMSCjFBod8H+N5i3uxiqSoxa09lMJrg+rLfxJR d8hqNkbfLnVt+0kQinrZmJgJnQ== X-Google-Smtp-Source: AA0mqf50LRwjYdF6wl6WBbd8tOtHhpobZuhhhHxMpo8GzDj69YbuoLxBuxqjmtrOuTq9hAuLM2Nl3g== X-Received: by 2002:a05:6512:1193:b0:4a9:4061:1dc8 with SMTP id g19-20020a056512119300b004a940611dc8mr12676013lfr.33.1671236260378; Fri, 16 Dec 2022 16:17:40 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:39 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 11/15] clk: qcom: gcc-qcs404: sort out the cxo clock Date: Sat, 17 Dec 2022 02:17:26 +0200 Message-Id: <20221217001730.540502-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The GCC driver registers the cxo clock as a thin wrapper around board's xo_board clock. Nowadays we can use the xo_board directly in all the clocks that use it. Use the fw_name "cxo" for this clock. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 97 +++++++++++++++-------------------- 1 file changed, 41 insertions(+), 56 deletions(-) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 3941175d73a5..8fb268671f0c 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -37,14 +37,21 @@ enum { P_XO, }; +static const struct parent_map gcc_parent_map_1[] = { + { P_XO, 0 }, +}; + +static const struct clk_parent_data gcc_parent_data_1[] = { + { .fw_name = "cxo", .name = "xo-board" }, +}; + static struct clk_fixed_factor cxo = { .mult = 1, .div = 1, .hw.init = &(struct clk_init_data){ .name = "cxo", - .parent_data = &(const struct clk_parent_data) { - .name = "xo-board", - }, + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .num_parents = 1, .ops = &clk_fixed_factor_ops, }, @@ -59,10 +66,8 @@ static struct clk_alpha_pll gpll0_sleep_clk_src = { .enable_is_inverted = true, .hw.init = &(struct clk_init_data){ .name = "gpll0_sleep_clk_src", - .parent_data = &(const struct clk_parent_data) { - .hw = &cxo.hw, - }, - .num_parents = 1, + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_alpha_pll_ops, }, }, @@ -77,10 +82,8 @@ static struct clk_alpha_pll gpll0_out_main = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpll0_out_main", - .parent_data = &(const struct clk_parent_data) { - .hw = &cxo.hw, - }, - .num_parents = 1, + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_alpha_pll_ops, }, }, @@ -95,10 +98,8 @@ static struct clk_alpha_pll gpll0_ao_out_main = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "gpll0_ao_out_main", - .parent_data = &(const struct clk_parent_data) { - .hw = &cxo.hw, - }, - .num_parents = 1, + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .flags = CLK_IS_CRITICAL, .ops = &clk_alpha_pll_fixed_ops, }, @@ -113,10 +114,8 @@ static struct clk_alpha_pll gpll1_out_main = { .enable_mask = BIT(1), .hw.init = &(struct clk_init_data){ .name = "gpll1_out_main", - .parent_data = &(const struct clk_parent_data) { - .hw = &cxo.hw, - }, - .num_parents = 1, + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_alpha_pll_ops, }, }, @@ -146,10 +145,8 @@ static struct clk_alpha_pll gpll3_out_main = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "gpll3_out_main", - .parent_data = &(const struct clk_parent_data) { - .hw = &cxo.hw, - }, - .num_parents = 1, + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_alpha_pll_ops, }, }, @@ -163,10 +160,8 @@ static struct clk_alpha_pll gpll4_out_main = { .enable_mask = BIT(5), .hw.init = &(struct clk_init_data){ .name = "gpll4_out_main", - .parent_data = &(const struct clk_parent_data) { - .hw = &cxo.hw, - }, - .num_parents = 1, + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_alpha_pll_ops, }, }, @@ -182,10 +177,8 @@ static struct clk_pll gpll6 = { .status_bit = 17, .clkr.hw.init = &(struct clk_init_data){ .name = "gpll6", - .parent_data = &(const struct clk_parent_data) { - .hw = &cxo.hw, - }, - .num_parents = 1, + .parent_data = gcc_parent_data_1, + .num_parents = ARRAY_SIZE(gcc_parent_data_1), .ops = &clk_pll_ops, }, }; @@ -209,23 +202,15 @@ static const struct parent_map gcc_parent_map_0[] = { }; static const struct clk_parent_data gcc_parent_data_0[] = { - { .hw = &cxo.hw }, + { .fw_name = "cxo", .name = "xo-board" }, { .hw = &gpll0_out_main.clkr.hw }, }; static const struct clk_parent_data gcc_parent_data_ao_0[] = { - { .hw = &cxo.hw }, + { .fw_name = "cxo", .name = "xo-board" }, { .hw = &gpll0_ao_out_main.clkr.hw }, }; -static const struct parent_map gcc_parent_map_1[] = { - { P_XO, 0 }, -}; - -static const struct clk_parent_data gcc_parent_data_1[] = { - { .hw = &cxo.hw }, -}; - static const struct parent_map gcc_parent_map_2[] = { { P_XO, 0 }, { P_GPLL0_OUT_MAIN, 1 }, @@ -234,7 +219,7 @@ static const struct parent_map gcc_parent_map_2[] = { }; static const struct clk_parent_data gcc_parent_data_2[] = { - { .hw = &cxo.hw }, + { .fw_name = "cxo", .name = "xo-board" }, { .hw = &gpll0_out_main.clkr.hw }, { .hw = &gpll6_out_aux.hw }, { .fw_name = "sleep_clk", .name = "sleep_clk" }, @@ -247,7 +232,7 @@ static const struct parent_map gcc_parent_map_3[] = { }; static const struct clk_parent_data gcc_parent_data_3[] = { - { .hw = &cxo.hw }, + { .fw_name = "cxo", .name = "xo-board" }, { .hw = &gpll0_out_main.clkr.hw }, { .hw = &gpll6_out_aux.hw }, }; @@ -258,7 +243,7 @@ static const struct parent_map gcc_parent_map_4[] = { }; static const struct clk_parent_data gcc_parent_data_4[] = { - { .hw = &cxo.hw }, + { .fw_name = "cxo", .name = "xo-board" }, { .hw = &gpll1_out_main.clkr.hw }, }; @@ -269,7 +254,7 @@ static const struct parent_map gcc_parent_map_5[] = { }; static const struct clk_parent_data gcc_parent_data_5[] = { - { .hw = &cxo.hw }, + { .fw_name = "cxo", .name = "xo-board" }, { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" }, /* "gpll0_out_aux", */ }; @@ -281,7 +266,7 @@ static const struct parent_map gcc_parent_map_6[] = { }; static const struct clk_parent_data gcc_parent_data_6[] = { - { .hw = &cxo.hw }, + { .fw_name = "cxo", .name = "xo-board" }, { .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" }, /* "gpll0_out_aux", */ }; @@ -295,7 +280,7 @@ static const struct parent_map gcc_parent_map_7[] = { }; static const struct clk_parent_data gcc_parent_data_7[] = { - { .hw = &cxo.hw }, + { .fw_name = "cxo", .name = "xo-board" }, { .hw = &gpll0_out_main.clkr.hw }, { .hw = &gpll3_out_main.clkr.hw }, { .hw = &gpll6_out_aux.hw }, @@ -308,7 +293,7 @@ static const struct parent_map gcc_parent_map_8[] = { }; static const struct clk_parent_data gcc_parent_data_8[] = { - { .hw = &cxo.hw }, + { .fw_name = "cxo", .name = "xo-board" }, { .fw_name = "hdmi_pll", .name = "hdmi_pll" }, }; @@ -320,7 +305,7 @@ static const struct parent_map gcc_parent_map_9[] = { }; static const struct clk_parent_data gcc_parent_data_9[] = { - { .hw = &cxo.hw }, + { .fw_name = "cxo", .name = "xo-board" }, { .hw = &gpll0_out_main.clkr.hw }, { .fw_name = "dsi0pll", .name = "dsi0pll" }, { .hw = &gpll6_out_aux.hw }, @@ -332,7 +317,7 @@ static const struct parent_map gcc_parent_map_10[] = { }; static const struct clk_parent_data gcc_parent_data_10[] = { - { .hw = &cxo.hw }, + { .fw_name = "cxo", .name = "xo-board" }, { .fw_name = "sleep_clk", .name = "sleep_clk" }, }; @@ -342,7 +327,7 @@ static const struct parent_map gcc_parent_map_11[] = { }; static const struct clk_parent_data gcc_parent_data_11[] = { - { .hw = &cxo.hw }, + { .fw_name = "cxo", .name = "xo-board" }, { .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" }, }; @@ -353,7 +338,7 @@ static const struct parent_map gcc_parent_map_12[] = { }; static const struct clk_parent_data gcc_parent_data_12[] = { - { .hw = &cxo.hw }, + { .fw_name = "cxo", .name = "xo-board" }, { .fw_name = "dsi0pll", .name = "dsi0pll" }, /* "gpll0_out_aux", */ }; @@ -366,7 +351,7 @@ static const struct parent_map gcc_parent_map_13[] = { }; static const struct clk_parent_data gcc_parent_data_13[] = { - { .hw = &cxo.hw }, + { .fw_name = "cxo", .name = "xo-board" }, { .hw = &gpll0_out_main.clkr.hw }, { .hw = &gpll4_out_main.clkr.hw }, { .hw = &gpll6_out_aux.hw }, @@ -379,7 +364,7 @@ static const struct parent_map gcc_parent_map_14[] = { }; static const struct clk_parent_data gcc_parent_data_14[] = { - { .hw = &cxo.hw }, + { .fw_name = "cxo", .name = "xo-board" }, { .hw = &gpll0_out_main.clkr.hw }, /* "gpll4_out_aux", */ }; @@ -390,7 +375,7 @@ static const struct parent_map gcc_parent_map_15[] = { }; static const struct clk_parent_data gcc_parent_data_15[] = { - { .hw = &cxo.hw }, + { .fw_name = "cxo", .name = "xo-board" }, /* "gpll0_out_aux", */ }; @@ -401,7 +386,7 @@ static const struct parent_map gcc_parent_map_16[] = { }; static const struct clk_parent_data gcc_parent_data_16[] = { - { .hw = &cxo.hw }, + { .fw_name = "cxo", .name = "xo-board" }, { .hw = &gpll0_out_main.clkr.hw }, /* "gpll0_out_aux", */ }; From patchwork Sat Dec 17 00:17:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 634990 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 123F5C5479D for ; Sat, 17 Dec 2022 00:24:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230252AbiLQAYJ (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:40 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 12/15] clk: qcom: gcc-qcs404: add support for GDSCs Date: Sat, 17 Dec 2022 02:17:27 +0200 Message-Id: <20221217001730.540502-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for two GDSCs provided by this clock controller. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-qcs404.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 8fb268671f0c..f8dbfffc2b8e 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -19,6 +19,7 @@ #include "clk-rcg.h" #include "clk-regmap.h" #include "common.h" +#include "gdsc.h" #include "reset.h" enum { @@ -2598,6 +2599,22 @@ static struct clk_branch gcc_wdsp_q6ss_axim_clk = { }, }; +static struct gdsc mdss_gdsc = { + .gdscr = 0x4d078, + .pd = { + .name = "mdss", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + +static struct gdsc oxili_gdsc = { + .gdscr = 0x5901c, + .pd = { + .name = "oxili", + }, + .pwrsts = PWRSTS_OFF_ON, +}; + static struct clk_hw *gcc_qcs404_hws[] = { &cxo.hw, }; @@ -2748,6 +2765,11 @@ static struct clk_regmap *gcc_qcs404_clocks[] = { }; +static struct gdsc *gcc_qcs404_gdscs[] = { + [MDSS_GDSC] = &mdss_gdsc, + [OXILI_GDSC] = &oxili_gdsc, +}; + static const struct qcom_reset_map gcc_qcs404_resets[] = { [GCC_GENI_IR_BCR] = { 0x0F000 }, [GCC_CDSP_RESTART] = { 0x18000 }, @@ -2790,6 +2812,8 @@ static const struct qcom_cc_desc gcc_qcs404_desc = { .num_resets = ARRAY_SIZE(gcc_qcs404_resets), .clk_hws = gcc_qcs404_hws, .num_clk_hws = ARRAY_SIZE(gcc_qcs404_hws), + .gdscs = gcc_qcs404_gdscs, + .num_gdscs = ARRAY_SIZE(gcc_qcs404_gdscs), }; static const struct of_device_id gcc_qcs404_match_table[] = { From patchwork Sat Dec 17 00:17:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 634989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FC89C63705 for ; Sat, 17 Dec 2022 00:24:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230299AbiLQAYL (ORCPT ); Fri, 16 Dec 2022 19:24:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230234AbiLQAXQ (ORCPT ); Fri, 16 Dec 2022 19:23:16 -0500 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 809CB7E297 for ; Fri, 16 Dec 2022 16:17:42 -0800 (PST) Received: by mail-lf1-x12a.google.com with SMTP id cf42so5927124lfb.1 for ; Fri, 16 Dec 2022 16:17:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=A4AidH89fDpMmt6amLOtMiqausw19uEwRJmaxMyMhmE=; b=mvu+zcFLAf58M4jAxZ4udj7LLuscOB0CGdZ9pnf9THwitGd3A6WpFJqlaHcZoAJ4C3 d0BHEov/lFbUST22RE9eJPDpp1g48jpR+STO9gwkEs0v6yPnzGTGpp+rb9QehomtTd/1 AhQyWGUaoA9kGX7GOBioyC9ak1IV34i+x4Fv5CWsgzEXyburjLG2H1/AQnuJBQ/6E6zI ImeHDRGIY3Hh2AVE8vafDPkf92sIHfKII4W3dPRuCqDSHJrsASVGuC9gyw9/IMsu06LB tyGAC4B9Sm53yl3btc4wizgr5L2DTFH8Tqh3910+ozR+LHKTXKwIA0f7F22bPhllwSeI QDJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A4AidH89fDpMmt6amLOtMiqausw19uEwRJmaxMyMhmE=; b=1KO6U6EugaB0Zocmy+6D/NZlw0EwS2JjuieR0H9BCeFcHgdndvRPXselA8Po8Y8Jie qPUpVIOYl80gJxgyFTNX2MnZVGYOeegy4aIzCwFsNTB+INtH1pvwKVkVoc/I1/Mph0OX 6YRC1gV1ZcfQQ4PgxpNf4GdVj4kJNnifVdA1Q8MFoJjhawwdOjssW6Ev2uKMRaCHcRS5 dEGotmnFnw3Q6TdBPykyTC19tvpRsmkKHFP5H124PDRTIAzfUbB2IV24xrrA2Jhi7Rah XMhD6aD6NHHcYADFj15Z/4SMyW0juIEFaNyjnXmXobYhoBPZiw20bQwYJveNlx/6Fd/V RwWg== X-Gm-Message-State: ANoB5pl6DChHVMhbcv82hblCLERzcXlcyT8q+lUCqtIp09vzYeewcCUt wzO4yGaE6iPJ3QDE8mTnyQ88sw== X-Google-Smtp-Source: AA0mqf7EboJmYvwsEFdy2YkliyzGZdHk1/a6i6rKNTBx99M1bmqrk/TOuENbGUuAQodZq8RRIt2FmA== X-Received: by 2002:a05:6512:3990:b0:4b6:d28a:2558 with SMTP id j16-20020a056512399000b004b6d28a2558mr15344090lfu.49.1671236262055; Fri, 16 Dec 2022 16:17:42 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:41 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 13/15] arm64: dts: qcom: qcs404: use symbol names for PCIe resets Date: Sat, 17 Dec 2022 02:17:28 +0200 Message-Id: <20221217001730.540502-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The commit e5bbbff5b7d7 ("clk: gcc-qcs404: Add PCIe resets") added names for PCIe resets, but it did not change the existing qcs404.dtsi to use these names. Do it now and use symbol names to make it easier to check and modify the dtsi in future. Fixes: e5bbbff5b7d7 ("clk: gcc-qcs404: Add PCIe resets") Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index ffffaa7507cf..ffc4b081bb62 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -806,7 +806,7 @@ pcie_phy: phy@7786000 { clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, - <&gcc 21>; + <&gcc GCC_PCIE_0_PIPE_ARES>; reset-names = "phy", "pipe"; clock-output-names = "pcie_0_pipe_clk"; @@ -1337,12 +1337,12 @@ pcie: pci@10000000 { <&gcc GCC_PCIE_0_SLV_AXI_CLK>; clock-names = "iface", "aux", "master_bus", "slave_bus"; - resets = <&gcc 18>, - <&gcc 17>, - <&gcc 15>, - <&gcc 19>, + resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, + <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, <&gcc GCC_PCIE_0_BCR>, - <&gcc 16>; + <&gcc GCC_PCIE_0_AHB_ARES>; reset-names = "axi_m", "axi_s", "axi_m_sticky", From patchwork Sat Dec 17 00:17:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 634873 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7A4AC63797 for ; Sat, 17 Dec 2022 00:24:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230234AbiLQAYM (ORCPT ); Fri, 16 Dec 2022 19:24:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230319AbiLQAXQ (ORCPT ); Fri, 16 Dec 2022 19:23:16 -0500 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 439057E29B for ; Fri, 16 Dec 2022 16:17:43 -0800 (PST) Received: by mail-lf1-x135.google.com with SMTP id m29so5659435lfo.11 for ; Fri, 16 Dec 2022 16:17:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1Hsa31ymOeybHDD6Oy0urHW3AuIWlU3Je1yr2qvFGAY=; b=VgI3nLWS3nexAa4ub9/UR1Rq9pDey2EJDDSCbEaJGoAbQrscscKiVHeDBy4rN/8D45 24b4WLE1T/MjA0CTpYkbcgZEcXETxTDNgaSzLeF+Tfm4Znlinn41mi5ut55njZCad/us +WXufuTh45XyAQXqrpDRadg7NEh/7ElZMbPbdGXwtW1kL/cDi2z0lAF9dXCoPl62enkD oSw8A0a/hcL2iCtukYBPNg4GiBKjn+BMmhGF4jlBMsqs/toBWH+s6qYvWhgOjdZy7sRX IXjEDpt3oMwNgwvweMokV7iXv7b0gOLtzCcfjfd3L2Y0BEyIylAUYk55EPCfqZStzrbZ lXgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1Hsa31ymOeybHDD6Oy0urHW3AuIWlU3Je1yr2qvFGAY=; b=T7IJekondQWZH41/5GHQpRTOJuQcmciOswocY+/HzhSc7pJMjAFpW8MFvRzWrxXrHL a980K9O6qb+wvikyaMpfAD+9qxFTHO9Qsyz8e51me4aGWYjfhCqay9xM6cW2wuzwpgwF DkNk985FJivEZsIIfm/sICqlRbXSExMhhjF7z3J32E6GOwMxrKvozXupAQ7waBgiUOv+ a/uj4VyThPmkd1nfids7ImkKXDNR7Fq1Nv1w7QuNGbeULE3XeFKc9fZjbAseObfGpN+2 56wWxeKxQyERoeK6dx0anNaLID2rtlNqHF9QBJwUqa8fVv7qr8Mvy70sURzKnic8Jwvm i40w== X-Gm-Message-State: ANoB5pknaNDSRnetUe095csM1Q+cPEm3K5Y+P5pfv6lB+xyKiI+E0dtj OMKOWzAUIPsjHWdjcbWd5Kpkng== X-Google-Smtp-Source: AA0mqf5bsvN6t916su3JhYhq1Z8++hWXdyWEbPhMmOtVCvinfLd2TxCbGNZ6yrEJEBeEg+NIA3y/WQ== X-Received: by 2002:a05:6512:acf:b0:4a4:68b7:dec0 with SMTP id n15-20020a0565120acf00b004a468b7dec0mr10439992lfu.28.1671236262850; Fri, 16 Dec 2022 16:17:42 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:42 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 14/15] arm64: dts: qcom: qcs404: add power-domains-cells to gcc node Date: Sat, 17 Dec 2022 02:17:29 +0200 Message-Id: <20221217001730.540502-15-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org As gcc now provides two GDSCs, add #power-domain-cells property to the gcc device node. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index ffc4b081bb62..b72542631337 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -729,6 +729,7 @@ gcc: clock-controller@1800000 { reg = <0x01800000 0x80000>; #clock-cells = <1>; #reset-cells = <1>; + #power-domain-cells = <1>; assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; assigned-clock-rates = <19200000>; From patchwork Sat Dec 17 00:17:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 634987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D058C46467 for ; Sat, 17 Dec 2022 00:24:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230326AbiLQAYQ (ORCPT ); Fri, 16 Dec 2022 19:24:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229635AbiLQAXT (ORCPT ); Fri, 16 Dec 2022 19:23:19 -0500 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DBA37E2AA for ; Fri, 16 Dec 2022 16:17:44 -0800 (PST) Received: by mail-lf1-x131.google.com with SMTP id 1so5899661lfz.4 for ; Fri, 16 Dec 2022 16:17:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IakMGoNeAkiafUmQyTYpE4STAOzYx1wLgMpz/v+W8ao=; b=gtUM7rgOl3NWuHdHVJ+11cJsj01C6/8ZgNNQ/DlRMO8KZoTb3WAeN8TQW2gTc0l/QL 6FRIJCuQBH1OEUCzXYkR52dMEAJyNxMfCm7Ao83or+QxGqPdMRu9ut5spBcRdOk8oDJ0 aUi/dv3zc3z1QZqsv6L08kaf/9n2YSJfpzcP07/Lqhj1TdZe21sgCvnhu1IiF8dcgkUR UotVQdtVd0KtlNf1ColX1NRF2OdeGAGkmpjG5694VpQ4Xyy6MEk3qDfDIYZgNVX/mxeQ MItvvdh0ETgtdhzDuVvEFvJeR+KkLW7H6ZujyQ05B1ofw6XV/Jw0pPB+2NRT4l0rU9NQ urhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IakMGoNeAkiafUmQyTYpE4STAOzYx1wLgMpz/v+W8ao=; b=4Rfvj2LBVOUvlgYXGHEeb96FqPVVRR7Sif4uLtavyP8f0cemHDGbJi31rCCax2qkHc Q/9mvn2s8lXq8DhVMKU2nMimjFeA/s24LDLkl1ZauUXuFLKh2r3gZTyJFHOAXcYDk2Xc Tyz2KO4Ki1blaXVkWdKZS52FAOLHltshYdORlCwMBlGCmN37Kp0qGgoHwTrrSnUN2q3+ T2jvjYPXBO16dR5rsuAvY0Jg1nWa5oKygJlVBymx20T/l2rdxu9JwIkY+iDDQNnAwfWP w0rlJyxMsW8cWmXXSCpe6aofk64gNsK1aRTsXdfKKSNPxXUL9Dw9PkdLabiwRkrLuVPo +e6Q== X-Gm-Message-State: ANoB5pnzgQCqk0EpLiDNHCxZ/NoAbbh/86ZPnVdJo3Qn5SPI0NdhCITU Yt8KB/MyzR728qBMXsMDqZ3DPg== X-Google-Smtp-Source: AA0mqf7x2WdR/+5Wh61oqWdZBmYm7BWZfGQtYvK7acmOqBpQ6tod/EDIbGs+3nxToPHONFh7ye+lkA== X-Received: by 2002:a05:6512:7b:b0:4a9:9827:68e8 with SMTP id i27-20020a056512007b00b004a9982768e8mr7609075lfo.7.1671236263654; Fri, 16 Dec 2022 16:17:43 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id c19-20020a056512325300b004b5adb59ed5sm341228lfr.297.2022.12.16.16.17.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Dec 2022 16:17:43 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 15/15] arm64: dts: qcom: qcs404: add clocks to the gcc node Date: Sat, 17 Dec 2022 02:17:30 +0200 Message-Id: <20221217001730.540502-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> References: <20221217001730.540502-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Populate the gcc node with the clocks and clock-names properties to enable DT-based lookups for the parent clocks. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index b72542631337..ee337a3980fa 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -731,6 +731,19 @@ gcc: clock-controller@1800000 { #reset-cells = <1>; #power-domain-cells = <1>; + clocks = <&xo_board>, + <&sleep_clk>, + <&pcie_phy>, + <0>, + <0>, + <0>; + clock-names = "cxo", + "sleep_clk", + "pcie_0_pipe_clk_src", + "dsi0pll", + "dsi0pllbyte", + "hdmi_pll"; + assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; assigned-clock-rates = <19200000>; };