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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id 3-20020ac85643000000b003a816011d51sm1998185qtt.38.2022.12.12.10.23.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 10:23:23 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@linaro.org, robh+dt@kernel.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.com, quic_shazhuss@quicinc.com Subject: [PATCH 1/4] arm64: dts: qcom: sc8280xp: rename i2c5 to i2c21 Date: Mon, 12 Dec 2022 13:23:11 -0500 Message-Id: <20221212182314.1902632-2-bmasney@redhat.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221212182314.1902632-1-bmasney@redhat.com> References: <20221212182314.1902632-1-bmasney@redhat.com> MIME-Version: 1.0 Content-type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org According to the downstream 5.4 kernel sources for the sa8540p, i2c@894000 is labeled i2c bus 21, not 5. The interrupts and clocks also match. Let's go ahead and correct the name that's used in the three files where this is listed. Signed-off-by: Brian Masney Fixes: 152d1faf1e2f3 ("arm64: dts: qcom: add SC8280XP platform") Fixes: ccd3517faf183 ("arm64: dts: qcom: sc8280xp: Add reference device") Fixes: 32c231385ed43 ("arm64: dts: qcom: sc8280xp: add Lenovo Thinkpad X13s devicetree") --- arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 6 +++--- arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 6 +++--- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts index 551768f97729..1ab76724144d 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts @@ -326,11 +326,11 @@ &qup2 { status = "okay"; }; -&qup2_i2c5 { +&qup2_i2c21 { clock-frequency = <400000>; pinctrl-names = "default"; - pinctrl-0 = <&qup2_i2c5_default>; + pinctrl-0 = <&qup2_i2c21_default>; status = "okay"; @@ -598,7 +598,7 @@ qup0_i2c4_default: qup0-i2c4-default-state { drive-strength = <16>; }; - qup2_i2c5_default: qup2-i2c5-default-state { + qup2_i2c21_default: qup2-i2c21-default-state { pins = "gpio81", "gpio82"; function = "qup21"; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts index 568c6be1ceaa..284adf60386a 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts @@ -531,11 +531,11 @@ &qup2 { status = "okay"; }; -&qup2_i2c5 { +&qup2_i2c21 { clock-frequency = <400000>; pinctrl-names = "default"; - pinctrl-0 = <&qup2_i2c5_default>; + pinctrl-0 = <&qup2_i2c21_default>; status = "okay"; @@ -801,7 +801,7 @@ qup0_i2c4_default: qup0-i2c4-default-state { drive-strength = <16>; }; - qup2_i2c5_default: qup2-i2c5-default-state { + qup2_i2c21_default: qup2-i2c21-default-state { pins = "gpio81", "gpio82"; function = "qup21"; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 109c9d2b684d..875cc91324ce 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -827,7 +827,7 @@ qup2_uart17: serial@884000 { status = "disabled"; }; - qup2_i2c5: i2c@894000 { + qup2_i2c21: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0 0x00894000 0 0x4000>; clock-names = "se"; From patchwork Mon Dec 12 18:23:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Masney X-Patchwork-Id: 633748 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DA71C00145 for ; Mon, 12 Dec 2022 18:25:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232930AbiLLSZd (ORCPT ); Mon, 12 Dec 2022 13:25:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47032 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229629AbiLLSZR (ORCPT ); Mon, 12 Dec 2022 13:25:17 -0500 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 839D41055F for ; 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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id 3-20020ac85643000000b003a816011d51sm1998185qtt.38.2022.12.12.10.23.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 10:23:24 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@linaro.org, robh+dt@kernel.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.com, quic_shazhuss@quicinc.com Subject: [PATCH 2/4] arm64: dts: qcom: sc8280xp: add missing i2c nodes Date: Mon, 12 Dec 2022 13:23:12 -0500 Message-Id: <20221212182314.1902632-3-bmasney@redhat.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221212182314.1902632-1-bmasney@redhat.com> References: <20221212182314.1902632-1-bmasney@redhat.com> MIME-Version: 1.0 Content-type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the missing nodes for the i2c buses that's present on this SoC. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. Signed-off-by: Brian Masney --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 352 +++++++++++++++++++++++++ 1 file changed, 352 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 875cc91324ce..392a1509f0be 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -813,6 +813,38 @@ qup2: geniqup@8c0000 { status = "disabled"; + qup2_i2c16: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + qup2_i2c17: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00884000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + qup2_uart17: serial@884000 { compatible = "qcom,geni-uart"; reg = <0 0x00884000 0 0x4000>; @@ -827,6 +859,54 @@ qup2_uart17: serial@884000 { status = "disabled"; }; + qup2_i2c18: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + qup2_i2c19: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0088c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + qup2_i2c20: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00890000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + qup2_i2c21: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0 0x00894000 0 0x4000>; @@ -842,6 +922,38 @@ qup2_i2c21: i2c@894000 { interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; + + qup2_i2c22: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00898000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + qup2_i2c23: i2c@89c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0089c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; }; qup0: geniqup@9c0000 { @@ -858,6 +970,70 @@ qup0: geniqup@9c0000 { status = "disabled"; + qup0_i2c0: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00980000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + qup0_i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00984000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + qup0_i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00988000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + qup0_i2c3: i2c@98c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0098c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + qup0_i2c4: i2c@990000 { compatible = "qcom,geni-i2c"; reg = <0 0x00990000 0 0x4000>; @@ -873,6 +1049,54 @@ qup0_i2c4: i2c@990000 { interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; + + qup0_i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00994000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + qup0_i2c6: i2c@998000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00998000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + qup0_i2c7: i2c@99c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0099c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; }; qup1: geniqup@ac0000 { @@ -888,6 +1112,134 @@ qup1: geniqup@ac0000 { ranges; status = "disabled"; + + qup1_i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + qup1_i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + qup1_i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a88000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + qup1_i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + qup1_i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + qup1_i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + status = "disabled"; + }; + + qup1_i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a98000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC8280XP_CX>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 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[73.214.169.22]) by smtp.gmail.com with ESMTPSA id 3-20020ac85643000000b003a816011d51sm1998185qtt.38.2022.12.12.10.23.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 10:23:25 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@linaro.org, robh+dt@kernel.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.com, quic_shazhuss@quicinc.com Subject: [PATCH 3/4] arm64: dts: qcom: sa8540p-ride: add qup1_i2c15 and qup2_i2c18 nodes Date: Mon, 12 Dec 2022 13:23:13 -0500 Message-Id: <20221212182314.1902632-4-bmasney@redhat.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221212182314.1902632-1-bmasney@redhat.com> References: <20221212182314.1902632-1-bmasney@redhat.com> MIME-Version: 1.0 Content-type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the necessary nodes in order to get qup1_i2c15 and qup2_i2c18 functioning on the automotive board and exposed to userspace. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. This change was validated by using i2c-tools 4.3.3 on CentOS Stream 9: [root@localhost ~]# i2cdetect -l i2c-15 i2c Geni-I2C I2C adapter i2c-18 i2c Geni-I2C I2C adapter [root@localhost ~]# i2cdetect -a -y 15 Warning: Can't use SMBus Quick Write command, will skip some addresses 0 1 2 3 4 5 6 7 8 9 a b c d e f 00: 10: 20: 30: -- -- -- -- -- -- -- -- 40: 50: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 60: 70: Bus 18 has the same output. I validated that we get the same output on the downstream kernel. Signed-off-by: Brian Masney --- arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 46 +++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts index d70859803fbd..6dc3f3ff8ece 100644 --- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts @@ -17,6 +17,8 @@ / { compatible = "qcom,sa8540p-ride", "qcom,sa8540p"; aliases { + i2c15 = &qup1_i2c15; + i2c18 = &qup2_i2c18; serial0 = &qup2_uart17; }; @@ -188,10 +190,28 @@ &pcie3a_phy { status = "okay"; }; +&qup1 { + status = "okay"; +}; + +&qup1_i2c15 { + pinctrl-names = "default"; + pinctrl-0 = <&qup1_i2c15_default>; + + status = "okay"; +}; + &qup2 { status = "okay"; }; +&qup2_i2c18 { + pinctrl-names = "default"; + pinctrl-0 = <&qup2_i2c18_default>; + + status = "okay"; +}; + &qup2_uart17 { compatible = "qcom,geni-debug-uart"; status = "okay"; @@ -313,4 +333,30 @@ wake-pins { bias-pull-up; }; }; + + qup1_i2c15_default: qup1-i2c15-state { + mux-pins { + pins = "gpio36", "gpio37"; + function = "qup15"; + }; + + config-pins { + pins = "gpio36", "gpio37"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; + + qup2_i2c18_default: qup2-i2c18-state { + mux-pins { + pins = "gpio66", "gpio67"; + function = "qup18"; + }; + + config-pins { + pins = "gpio66", "gpio67"; + drive-strength = <0x02>; + bias-pull-up; + }; + }; }; From patchwork Mon Dec 12 18:23:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brian Masney X-Patchwork-Id: 633305 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90D73C4332F for ; Mon, 12 Dec 2022 18:25:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233101AbiLLSZe (ORCPT ); Mon, 12 Dec 2022 13:25:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232670AbiLLSZT (ORCPT ); Mon, 12 Dec 2022 13:25:19 -0500 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 897AC10571 for ; Mon, 12 Dec 2022 10:23:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1670869409; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=36MqwyXO1Uv69/AVbNcMRN0gMv1afzIDRB6zP0xQ7/8=; b=dlfXyjraOLpBDYqSJ6Gjuqi7sCY6IqIm9wrvFh7JFcsPeXf3eTzFhocXKS33P3c3W+kTvF n5PUrW+QAC0l/RKAjDLkcOPmgU5hYQ4EH3FwyTLzLi4C/4PUBlvy3cB0erBmqV7MakySw1 Cm3dLKKAtSV8esn9lRDtiKV2ksjLQWg= Received: from mail-qk1-f199.google.com (mail-qk1-f199.google.com [209.85.222.199]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-107-tQPilwAuO1CwGNEzhGFfuQ-1; Mon, 12 Dec 2022 13:23:28 -0500 X-MC-Unique: tQPilwAuO1CwGNEzhGFfuQ-1 Received: by mail-qk1-f199.google.com with SMTP id az39-20020a05620a172700b006ff85c3b19eso7206874qkb.18 for ; Mon, 12 Dec 2022 10:23:28 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=36MqwyXO1Uv69/AVbNcMRN0gMv1afzIDRB6zP0xQ7/8=; b=niCKGEG2L6jTw5RKRNcgTxtAboyCr91IJ3um4+hcZJoLC/dyUlEZnUNjqOaEpKrMUk Bp5uvuME2SntsitOCaLa9GzK7QQuc2Y1CcF2Mi6HuB5A9se1EahW6Higo2uv41XTv7L0 z/Q4XnyEtKpBmIi6N7N4uaV566Y2/Yv53ctbAycoHgQfV+86mCpr6fMibKB28KFVdfUa oz+b7mFOLp513EJTSP1WVw5VLsrKj/cPoPGmvXB2+2Wpgvy6jR1EA6H4Z7sGRt/rcCET bWmvuCPIVRslmTgjln06WF5+Nqq6fUFAVPt0iSYT+x8OqYUP8BtQh9H70i5RTWYGnr80 +5pA== X-Gm-Message-State: ANoB5plRaM3ZCEDrWRmFrtQ3tdo7koYvp7WQYXXJMKnxoN/Giv6vFUzj XxDTrO1x/ScxxVOS0S/h9lta8PCYCmUg+KaDvHPKyOT2Oe1TmDAHo9mKXCI21oRC2b3H1eOu24+ SVoJiWI0fVONS3Yy6s3s/mA== X-Received: by 2002:ac8:464d:0:b0:3a7:f91d:917c with SMTP id f13-20020ac8464d000000b003a7f91d917cmr25677480qto.31.1670869407695; Mon, 12 Dec 2022 10:23:27 -0800 (PST) X-Google-Smtp-Source: AA0mqf4FaqYavyVyGZG/vj8VyGoEgclGw7lUewz1j1Jz0jHaSMyYDoD/WW60hKddy3NpRJepxDd7XA== X-Received: by 2002:ac8:464d:0:b0:3a7:f91d:917c with SMTP id f13-20020ac8464d000000b003a7f91d917cmr25677453qto.31.1670869407385; Mon, 12 Dec 2022 10:23:27 -0800 (PST) Received: from x1.redhat.com (c-73-214-169-22.hsd1.pa.comcast.net. [73.214.169.22]) by smtp.gmail.com with ESMTPSA id 3-20020ac85643000000b003a816011d51sm1998185qtt.38.2022.12.12.10.23.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 10:23:26 -0800 (PST) From: Brian Masney To: andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: konrad.dybcio@linaro.org, robh+dt@kernel.org, johan+linaro@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ahalaney@redhat.com, echanude@redhat.com, quic_shazhuss@quicinc.com Subject: [PATCH 4/4] arm64: dts: qcom: sc8280xp: add missing spi nodes Date: Mon, 12 Dec 2022 13:23:14 -0500 Message-Id: <20221212182314.1902632-5-bmasney@redhat.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221212182314.1902632-1-bmasney@redhat.com> References: <20221212182314.1902632-1-bmasney@redhat.com> MIME-Version: 1.0 Content-type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the missing nodes for the spi buses that's present on this SoC. This work was derived from various patches that Qualcomm delivered to Red Hat in a downstream kernel. Signed-off-by: Brian Masney --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 384 +++++++++++++++++++++++++ 1 file changed, 384 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 392a1509f0be..b50db09feae2 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -829,6 +829,22 @@ qup2_i2c16: i2c@880000 { status = "disabled"; }; + qup2_spi16: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00880000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup2_i2c17: i2c@884000 { compatible = "qcom,geni-i2c"; reg = <0 0x00884000 0 0x4000>; @@ -845,6 +861,22 @@ qup2_i2c17: i2c@884000 { status = "disabled"; }; + qup2_spi17: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00884000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup2_uart17: serial@884000 { compatible = "qcom,geni-uart"; reg = <0 0x00884000 0 0x4000>; @@ -875,6 +907,22 @@ qup2_i2c18: i2c@888000 { status = "disabled"; }; + qup2_spi18: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00888000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup2_i2c19: i2c@88c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0088c000 0 0x4000>; @@ -891,6 +939,22 @@ qup2_i2c19: i2c@88c000 { status = "disabled"; }; + qup2_spi19: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0088c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup2_i2c20: i2c@890000 { compatible = "qcom,geni-i2c"; reg = <0 0x00890000 0 0x4000>; @@ -907,6 +971,22 @@ qup2_i2c20: i2c@890000 { status = "disabled"; }; + qup2_spi20: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00890000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup2_i2c21: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0 0x00894000 0 0x4000>; @@ -923,6 +1003,22 @@ qup2_i2c21: i2c@894000 { status = "disabled"; }; + qup2_spi21: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00894000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup2_i2c22: i2c@898000 { compatible = "qcom,geni-i2c"; reg = <0 0x00898000 0 0x4000>; @@ -939,6 +1035,22 @@ qup2_i2c22: i2c@898000 { status = "disabled"; }; + qup2_spi22: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00898000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup2_i2c23: i2c@89c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0089c000 0 0x4000>; @@ -954,6 +1066,22 @@ qup2_i2c23: i2c@89c000 { interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; + + qup2_spi23: spi@89c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0089c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, + <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; }; qup0: geniqup@9c0000 { @@ -986,6 +1114,22 @@ qup0_i2c0: i2c@980000 { status = "disabled"; }; + qup0_spi0: spi@980000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00980000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup0_i2c1: i2c@984000 { compatible = "qcom,geni-i2c"; reg = <0 0x00984000 0 0x4000>; @@ -1002,6 +1146,22 @@ qup0_i2c1: i2c@984000 { status = "disabled"; }; + qup0_spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00984000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup0_i2c2: i2c@988000 { compatible = "qcom,geni-i2c"; reg = <0 0x00988000 0 0x4000>; @@ -1018,6 +1178,22 @@ qup0_i2c2: i2c@988000 { status = "disabled"; }; + qup0_spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00988000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup0_i2c3: i2c@98c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0098c000 0 0x4000>; @@ -1034,6 +1210,22 @@ qup0_i2c3: i2c@98c000 { status = "disabled"; }; + qup0_spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0098c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup0_i2c4: i2c@990000 { compatible = "qcom,geni-i2c"; reg = <0 0x00990000 0 0x4000>; @@ -1050,6 +1242,22 @@ qup0_i2c4: i2c@990000 { status = "disabled"; }; + qup0_spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00990000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup0_i2c5: i2c@994000 { compatible = "qcom,geni-i2c"; reg = <0 0x00994000 0 0x4000>; @@ -1066,6 +1274,22 @@ qup0_i2c5: i2c@994000 { status = "disabled"; }; + qup0_spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00994000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup0_i2c6: i2c@998000 { compatible = "qcom,geni-i2c"; reg = <0 0x00998000 0 0x4000>; @@ -1082,6 +1306,22 @@ qup0_i2c6: i2c@998000 { status = "disabled"; }; + qup0_spi6: spi@998000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00998000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup0_i2c7: i2c@99c000 { compatible = "qcom,geni-i2c"; reg = <0 0x0099c000 0 0x4000>; @@ -1097,6 +1337,22 @@ qup0_i2c7: i2c@99c000 { interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; + + qup0_spi7: spi@99c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0099c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; }; qup1: geniqup@ac0000 { @@ -1129,6 +1385,22 @@ qup1_i2c8: i2c@a80000 { status = "disabled"; }; + qup1_spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup1_i2c9: i2c@a84000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a84000 0 0x4000>; @@ -1145,6 +1417,22 @@ qup1_i2c9: i2c@a84000 { status = "disabled"; }; + qup1_spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup1_i2c10: i2c@a88000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a88000 0 0x4000>; @@ -1161,6 +1449,22 @@ qup1_i2c10: i2c@a88000 { status = "disabled"; }; + qup1_spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a88000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup1_i2c11: i2c@a8c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a8c000 0 0x4000>; @@ -1177,6 +1481,22 @@ qup1_i2c11: i2c@a8c000 { status = "disabled"; }; + qup1_spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup1_i2c12: i2c@a90000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a90000 0 0x4000>; @@ -1193,6 +1513,22 @@ qup1_i2c12: i2c@a90000 { status = "disabled"; }; + qup1_spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup1_i2c13: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a94000 0 0x4000>; @@ -1209,6 +1545,22 @@ qup1_i2c13: i2c@a94000 { status = "disabled"; }; + qup1_spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a94000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup1_i2c14: i2c@a98000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a98000 0 0x4000>; @@ -1225,6 +1577,22 @@ qup1_i2c14: i2c@a98000 { status = "disabled"; }; + qup1_spi14: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a98000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; + qup1_i2c15: i2c@a9c000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a9c000 0 0x4000>; @@ -1240,6 +1608,22 @@ qup1_i2c15: i2c@a9c000 { interconnect-names = "qup-core", "qup-config", "qup-memory"; status = "disabled"; }; + + qup1_spi15: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a9c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, + <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + spi-max-frequency = <50000000>; + status = "disabled"; + }; }; pcie4: pcie@1c00000 {