From patchwork Fri Dec 9 16:48:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 632546 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B007C2D0CB for ; Fri, 9 Dec 2022 16:49:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229720AbiLIQtB (ORCPT ); Fri, 9 Dec 2022 11:49:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42826 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229751AbiLIQtA (ORCPT ); Fri, 9 Dec 2022 11:49:00 -0500 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6922B94186 for ; Fri, 9 Dec 2022 08:48:59 -0800 (PST) Received: by mail-lj1-x232.google.com with SMTP id h10so5489180ljk.11 for ; Fri, 09 Dec 2022 08:48:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bHOsQvXR3hakSFSmtqr6ZnE8Sp59mrLg73lyyGTu7WE=; b=EedMFybdjDgyC2qmrrxjHi95X/hbVzlwnXEkl7H8uZFxrExOn0ZD6A/jfJMsTRb5SU D74sKE/i2yEi8O48Mkje7IpC6GyIgd17JJb5gX7rSxo71b+ZCWoueYIEXsy5mvsxOM3q 32XPGId/v5vHs/Wyr64sv35Z+mXuhb6FAoCI3vjNkG1AA6Bpj9hdgKC9TJd97yQ9/gOb xnziuf7DnepAJej6m0eGxT/hdmV421FEVPVBcks+qym8hyV5kffuUavuViIfIXqOe3X+ fQjtEWa/eaoPP442bHQHjqMDvuExIC57mnl+LjfI00X615zFRTqNK6qX+jGgFOH5QPCv X62w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bHOsQvXR3hakSFSmtqr6ZnE8Sp59mrLg73lyyGTu7WE=; b=oDNFSWmva4tPd5xbSAT3gjOo9iBQzSo9snHsCaao9eosEz8P45N67ecpWa6O2+M2iN RPGbyg+TE6XlGFO600GI72W/NLekb0cb82rJJzbgc1brVuJnx43L37hlFpxsbXLSJVms 2nJPXx+Aiy+q7ns9fIuWAslDltQxsN36goAj4nRqJNH0ZbhWUhfjmjdHfjuRz3sqBZr5 pLX3u7lALOFcqyRvHk1W++stWTf2bGEIfqJHFv67iho5ST5gB8Bj+4Ru8Sqi6I4ukqfd cbMpqhub5b+hTPHnS6yDcVkqWUo4K3DkPsIkwQ3oJOZCs4FRBRWRFJfYbMgx4itwFOof XRVw== X-Gm-Message-State: ANoB5pna5XpPvBx45wi/LGJHCYNTLrIj08YU1NevMlz7uYwEEP0Jo4bC Jxfj5WJGoaKOsElKwZqHjkg43A== X-Google-Smtp-Source: AA0mqf511Y3cnon+M1mh4oCJiaUtKB0Z+KpwbRykcxtLSPAIE/C41dshN+gl/Rz6KDReE/PyJfGQ8w== X-Received: by 2002:a2e:300a:0:b0:27a:3d9d:81f5 with SMTP id w10-20020a2e300a000000b0027a3d9d81f5mr240439ljw.5.1670604537829; Fri, 09 Dec 2022 08:48:57 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id y2-20020a05651c106200b002770fb5722fsm275242ljm.123.2022.12.09.08.48.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 08:48:57 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Alex Elder Subject: [PATCH v3 02/19] clk: qcom: smd-rpm: enable pin-controlled ln_bb_clk clocks on qcs404 Date: Fri, 9 Dec 2022 18:48:38 +0200 Message-Id: <20221209164855.128798-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> References: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The commit eaeee28db289 ("clk: qcom: smd: Add support for QCS404 rpm clocks") defined the pin-controlled ln_bb_clk clocks, but didn't add them to the qcs404_clks array. Add them to make these clocks usable to platform devices. Fixes: eaeee28db289 ("clk: qcom: smd: Add support for QCS404 rpm clocks") Reviewed-by: Alex Elder Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index fea505876855..3082f38513fa 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -843,6 +843,8 @@ static struct clk_smd_rpm *qcs404_clks[] = { [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk, [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, + [RPM_SMD_LN_BB_CLK_PIN] = &qcs404_ln_bb_clk_pin, + [RPM_SMD_LN_BB_A_CLK_PIN] = &qcs404_ln_bb_clk_a_pin, }; static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { From patchwork Fri Dec 9 16:48:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 632545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E542C3DA71 for ; Fri, 9 Dec 2022 16:49:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229717AbiLIQtD (ORCPT ); Fri, 9 Dec 2022 11:49:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229785AbiLIQtC (ORCPT ); Fri, 9 Dec 2022 11:49:02 -0500 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0EF5194183 for ; Fri, 9 Dec 2022 08:49:01 -0800 (PST) Received: by mail-lj1-x22e.google.com with SMTP id f16so5496502ljc.8 for ; Fri, 09 Dec 2022 08:49:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AinftmkjJQ8pNGBIFGCctCkBud1cs1e176Qi1VgGv64=; b=rmtLigaHqRrsptldNKLKJhZZad/0KL5hyBh9Dwn8ABNEvYHtf/WcEo2XGi73ko5X2a EJlE11UWwS24AUn1rgwEBSo95tsxGFm6lMirqDUlQYDg9Z23djQCYozvws9bVP/J8BQr 9FxmnSuu0EeSiw0TDSQ2vVvt7FKt6QIzrbuZCvYr/29JYEAVeGNdiMBkMNZ8++neKpTV 4fFLronD+3B7tFFC82IPaXGNeIc2Mc7hVWydglzJK6ErG4vNVdV4OqTCuNSI+hirneJi YgK3sxGoxDB7mwIar6gpOEcsDJlUY5UdynllVIfTqFSyd6M1HLlVCuj9Nmz93KGdNIYZ 2OGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AinftmkjJQ8pNGBIFGCctCkBud1cs1e176Qi1VgGv64=; b=xlGRZGlwDF/+sOpUq6lU8uUD6Th0byqAfacqglydoSUQ5abuo3pFpp9UXB/4xbotvH qVkISezunLmlBPUPx62RJjGo+jX3qHVE0XnKYSLqxiQ7uLo0iKzg1Q2So4Y944hWlnq2 gWOT4oyiXIiIfJczcf7VXKUxzkuEFRE4yNsmaBjlrHLSzsZFSkJVtE4jGotVU2Vr2usc +Ve7de+cCpggSRT1e1d7JRjZzXWTEZrw02t2Xuok/WRBeMpVN+5LzkUru3jOa06EUc38 uF6Mk0O8wJKcGwPXSW+z9V/nOebDtjtr9RcjHX0wnCgEWXZe0f4QcYK/e5wL3wBrKESH iG9A== X-Gm-Message-State: ANoB5pnenovmfUxj3L+MM/Jwl8OHKK7Yq6/ri2JMT8evA2ycIbFjLOHT mqM4CP/trJnAPpVdh1RQJHYKR8wLrGA7vASAr5I= X-Google-Smtp-Source: AA0mqf4MBVfufrMHJUd4sAi/vyfTz3GKd2f6yoNS42PrGa+EWsAoW1YjWYLbSi63k4phpMEQsw8f6Q== X-Received: by 2002:a2e:9197:0:b0:279:dc21:7e4e with SMTP id f23-20020a2e9197000000b00279dc217e4emr1810961ljg.46.1670604539334; Fri, 09 Dec 2022 08:48:59 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id y2-20020a05651c106200b002770fb5722fsm275242ljm.123.2022.12.09.08.48.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 08:48:58 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Alex Elder Subject: [PATCH v3 04/19] clk: qcom: smd-rpm: remove duplication between qcs404 and qcm2290 clocks Date: Fri, 9 Dec 2022 18:48:40 +0200 Message-Id: <20221209164855.128798-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> References: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Reuse qcs404's QPIC and BIMC_GPU clock for qcm2290. Fixes: 78b727d02815 ("clk: qcom: smd-rpm: Add QCM2290 RPM clock support") Reviewed-by: Konrad Dybcio Reviewed-by: Alex Elder Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index ccc54913eca5..31ef6345ff01 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -1168,11 +1168,8 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6375 = { DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, ln_bb_clk2, ln_bb_clk2_a, 0x2, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, rf_clk3_a, 6, 38400000); -DEFINE_CLK_SMD_RPM(qcm2290, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc_clk, cpuss_gnoc_a_clk, QCOM_SMD_RPM_MEM_CLK, 1); -DEFINE_CLK_SMD_RPM(qcm2290, bimc_gpu_clk, bimc_gpu_a_clk, - QCOM_SMD_RPM_MEM_CLK, 2); static struct clk_smd_rpm *qcm2290_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, @@ -1203,14 +1200,14 @@ static struct clk_smd_rpm *qcm2290_clks[] = { [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk, [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, - [RPM_SMD_QPIC_CLK] = &qcm2290_qpic_clk, - [RPM_SMD_QPIC_CLK_A] = &qcm2290_qpic_a_clk, + [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, + [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk, [RPM_SMD_HWKM_CLK] = &qcm2290_hwkm_clk, [RPM_SMD_HWKM_A_CLK] = &qcm2290_hwkm_a_clk, [RPM_SMD_PKA_CLK] = &qcm2290_pka_clk, [RPM_SMD_PKA_A_CLK] = &qcm2290_pka_a_clk, - [RPM_SMD_BIMC_GPU_CLK] = &qcm2290_bimc_gpu_clk, - [RPM_SMD_BIMC_GPU_A_CLK] = &qcm2290_bimc_gpu_a_clk, + [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk, + [RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk, [RPM_SMD_CPUSS_GNOC_CLK] = &qcm2290_cpuss_gnoc_clk, [RPM_SMD_CPUSS_GNOC_A_CLK] = &qcm2290_cpuss_gnoc_a_clk, }; From patchwork Fri Dec 9 16:48:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 632544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0424C4708E for ; Fri, 9 Dec 2022 16:49:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229468AbiLIQtF (ORCPT ); Fri, 9 Dec 2022 11:49:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42828 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229796AbiLIQtD (ORCPT ); Fri, 9 Dec 2022 11:49:03 -0500 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF44994190 for ; Fri, 9 Dec 2022 08:49:01 -0800 (PST) Received: by mail-lj1-x236.google.com with SMTP id l8so5472031ljh.13 for ; Fri, 09 Dec 2022 08:49:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MnqrTSbkJyuo5I31bQQ+wroCE17TRU6AvhMX1/MhOH0=; b=kAWtI4EENbm2peRdjMsVtgWEVk9rRB8zAJSrFHb8c9v9SXZVaCfgouLn1I5XKbUtIi 0wXm8UW0uwfo537GJxzR9n709vStGLblSGSMWmqZOyv68YMOKoS3FkBuJnGODlQZx6k8 F+X3MgLRZT4gODkp16f2Ii4cqNFGJH0ohMhXCIjYlg4tXTl0Sxdw66ZlISon2P5nZnWH 9g1AILdj91e41wbUJL2UQxitNogHql/vcPeV8QupxSMcjKEhWjIaemuNPxxxly/eeTP/ UgLUJwtVwxybKDoMBe3i80Oz+dEyKlwrSxoxMI2O01n42IdgKoZS5pEpWUUBDtedDmRu XLvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MnqrTSbkJyuo5I31bQQ+wroCE17TRU6AvhMX1/MhOH0=; b=zBBpDMvfmafFKNa9k68spcwJ2q2dGm/KHWRU0Man2RIikjdCIDd8qsSe5ORuxctzfk MCtMilbb08MVxowSyssOJVAk6mdarCJT36gUOTeUGu3M/1i0C9Hnk2YGpyREBRz2oAys QVLuDuyFzKv8BOcYxw/AbgawkcfVQLc1ji018zkmpA3mAIXkZo3hJLuy+i4kbnd2L43N g568McWlXk/+CW21qEAoylSPFND7T76dJGIHAopisODKvYslx/aCfkGFfJGobbJbSWds AHhqLElA+iGIIjeENNaAwiKp7CGcNEUEXRpz8uLXvMHkIDmiP7Qltj9eYOCrtHjKqxdb Ppjg== X-Gm-Message-State: ANoB5pkDVR0DRCZNI1LCDklgPvHV5ZsV8/Lxm5qyziI9iEykXSIPhSJA 0rQEyMZNyF6R/hp/rgeABACy7A== X-Google-Smtp-Source: AA0mqf5KwlPb9WxsBiJ8wkoyUOEfv0HkCM2rIhTqSYyn6DU/fGF6Co/UWbq7LJUQxXi7fhbVvWizfQ== X-Received: by 2002:a05:651c:905:b0:277:155c:f4a3 with SMTP id e5-20020a05651c090500b00277155cf4a3mr1590903ljq.38.1670604540209; Fri, 09 Dec 2022 08:49:00 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id y2-20020a05651c106200b002770fb5722fsm275242ljm.123.2022.12.09.08.48.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 08:48:59 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Alex Elder Subject: [PATCH v3 05/19] clk: qcom: smd-rpm: add missing ln_bb_clkN clocks Date: Fri, 9 Dec 2022 18:48:41 +0200 Message-Id: <20221209164855.128798-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> References: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Newer platforms (msm8998, sdm660, sm6125) have low noise LN_BB_CLKn clocks. The driver already uses proper clock indices (RPM_SMD_LN_BB_CLKn). Fix clock names used by these platforms. Fixes: a0384ecfe2aa ("clk: qcom: smd-rpm: De-duplicate identical entries") Fixes: edeb2ca74716 ("clk: qcom: smd: Add support for SM6125 rpm clocks") Reviewed-by: Konrad Dybcio Reviewed-by: Alex Elder Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 44 ++++++++++++++++++---------------- 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 31ef6345ff01..a0bf58785921 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -852,6 +852,10 @@ static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { .num_clks = ARRAY_SIZE(qcs404_clks), }; +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk1, ln_bb_clk1_a, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk1_pin, ln_bb_clk1_a_pin, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk2, ln_bb_clk2_a, 2, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk2_pin, ln_bb_clk2_a_pin, 2, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin, 3, 19200000); DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk, @@ -882,16 +886,16 @@ static struct clk_smd_rpm *msm8998_clks[] = { [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, - [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1, - [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a, - [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2, - [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a, + [RPM_SMD_LN_BB_CLK1] = &msm8998_ln_bb_clk1, + [RPM_SMD_LN_BB_CLK1_A] = &msm8998_ln_bb_clk1_a, + [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2, + [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a, [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3, [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a, - [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, - [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, - [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, - [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, + [RPM_SMD_LN_BB_CLK1_PIN] = &msm8998_ln_bb_clk1_pin, + [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8998_ln_bb_clk1_a_pin, + [RPM_SMD_LN_BB_CLK2_PIN] = &msm8998_ln_bb_clk2_pin, + [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8998_ln_bb_clk2_a_pin, [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin, [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin, [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, @@ -946,18 +950,18 @@ static struct clk_smd_rpm *sdm660_clks[] = { [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, - [RPM_SMD_LN_BB_CLK] = &msm8916_bb_clk1, - [RPM_SMD_LN_BB_A_CLK] = &msm8916_bb_clk1_a, - [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2, - [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a, + [RPM_SMD_LN_BB_CLK] = &msm8998_ln_bb_clk1, + [RPM_SMD_LN_BB_A_CLK] = &msm8998_ln_bb_clk1_a, + [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2, + [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a, [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3, [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a, [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, - [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, - [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, - [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, - [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, + [RPM_SMD_LN_BB_CLK1_PIN] = &msm8998_ln_bb_clk1_pin, + [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8998_ln_bb_clk1_a_pin, + [RPM_SMD_LN_BB_CLK2_PIN] = &msm8998_ln_bb_clk2_pin, + [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8998_ln_bb_clk2_a_pin, [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin, [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin, }; @@ -1057,10 +1061,10 @@ static struct clk_smd_rpm *sm6125_clks[] = { [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, - [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1, - [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a, - [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2, - [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a, + [RPM_SMD_LN_BB_CLK1] = &msm8998_ln_bb_clk1, + [RPM_SMD_LN_BB_CLK1_A] = &msm8998_ln_bb_clk1_a, + [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2, + [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a, [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3, [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a, [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, From patchwork Fri Dec 9 16:48:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 632543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18747C3DA6D for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id y2-20020a05651c106200b002770fb5722fsm275242ljm.123.2022.12.09.08.49.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 08:49:02 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Alex Elder Subject: [PATCH v3 08/19] clk: qcom: smd-rpm: remove duplication between sm6375 and sm6125 clocks Date: Fri, 9 Dec 2022 18:48:44 +0200 Message-Id: <20221209164855.128798-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> References: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Reuse sm6125's MMAXI clocks for sm6375. Reviewed-by: Konrad Dybcio Reviewed-by: Alex Elder Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index add92ecd513d..024665438b62 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -1126,8 +1126,6 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { }; /* SM6375 */ -DEFINE_CLK_SMD_RPM(sm6375, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6375, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 1); DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0); DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0); DEFINE_CLK_SMD_RPM_BRANCH(sm6375, bimc_freq_log, bimc_freq_log_a, QCOM_SMD_RPM_MISC_CLK, 4, 1); @@ -1146,10 +1144,10 @@ static struct clk_smd_rpm *sm6375_clks[] = { [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk, - [RPM_SMD_MMRT_CLK] = &sm6375_mmrt_clk, - [RPM_SMD_MMRT_A_CLK] = &sm6375_mmrt_a_clk, - [RPM_SMD_MMNRT_CLK] = &sm6375_mmnrt_clk, - [RPM_SMD_MMNRT_A_CLK] = &sm6375_mmnrt_a_clk, + [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk, + [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, + [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, + [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk, [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk, [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk, From patchwork Fri Dec 9 16:48:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 632542 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2D8DC3DA6E for ; Fri, 9 Dec 2022 16:49:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229876AbiLIQtM (ORCPT ); Fri, 9 Dec 2022 11:49:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229804AbiLIQtH (ORCPT ); Fri, 9 Dec 2022 11:49:07 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3D7E944D3 for ; Fri, 9 Dec 2022 08:49:05 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id p36so7899335lfa.12 for ; Fri, 09 Dec 2022 08:49:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/SKz54S/Hjw6I67t6Tu+my8q9HQYMyowV2EgYU0Golw=; b=chDi9dFAXCP/IpWdhNKtxSnQjc/sdfV9yH56uQyCSsIADc85S9K9pwf9/lhTxFf5Cd 2EWjWucPjOOXWWPa3TOfiec3ld49hkmd5sx6VDoBuqyw+DdMr14yS5zPrnpSFE48/H+N +ZzkkEgMZZgCfu2Eq/1PN4H7lJXEfwlv3fxtqpPVjMOifAvU5SsEoroKLu3ffwqzaBXE GmPfCeMuxtPaKR7qSyg2jpVFufEsrJ/3Gu57+YO98sTkmf3FKJfwbVrokOhOVrP52xW2 Gx18vnO8lYEzy2zq1qJ5qgvu7dUlVjcJZK6oZf1oWKcdgla5hU/adXIPVFsrOEcBlhCW VVUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/SKz54S/Hjw6I67t6Tu+my8q9HQYMyowV2EgYU0Golw=; b=BVd0nPBpKVXUkp4jllTmiwcBjriaU9CHr8S/9TMnFcBhhzF8Cq/tiaV2/z4FtG8+06 wa8FBNMP+Z6dUL/ES73VJgGeExHOOS9SxlL0rAm0TgiyIGD1Cip9qpQCVgkApG2cQ2CP /7ouG+QGmUisPPuc1CDoeWwRb7OLLw+U/cP2UuwB73Fe0Jxq1C9ayI3m8i2O3KOQF4Lu tGFbS5DwjMTbpMXDst5oLKvq0x1qBMAto8XESgWs/bqfUsKEpSwsQJjHoKivhI797xNk MfS4f5BdyJrEHBeIjisrjaCYJ90WYiVl0anlF3Jeq5+OXHlf3zk3yHb0zCqrVzC0gwI5 PYcQ== X-Gm-Message-State: ANoB5pkxCnmeuRadO7LBRaSYadX0m3XX72VmGoWuzbF+DVxuq5ZUSEwR i5VpP2lJdCmHseg/2IBenkdw5w== X-Google-Smtp-Source: AA0mqf6s41C+QEfxLXovYE4ofH3lEY+Wm9pKTThewCPyopx64Q2mD6LimbktRJfMf+q2hzbkJ5jg0A== X-Received: by 2002:ac2:4950:0:b0:4b5:7925:870d with SMTP id o16-20020ac24950000000b004b57925870dmr1618694lfi.12.1670604544352; Fri, 09 Dec 2022 08:49:04 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id y2-20020a05651c106200b002770fb5722fsm275242ljm.123.2022.12.09.08.49.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 08:49:03 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Alex Elder Subject: [PATCH v3 10/19] clk: qcom: smd-rpm: drop the rpm_status_id field Date: Fri, 9 Dec 2022 18:48:46 +0200 Message-Id: <20221209164855.128798-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> References: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The rpm_status_id field is a leftover from the non-SMD clocks. It is of no use for the SMD-RPM clock driver and is always equal to zero. Drop it completely. Reviewed-by: Konrad Dybcio Reviewed-by: Alex Elder Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index f9d8382cd274..2075cfd34f99 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -25,13 +25,11 @@ #define QCOM_RPM_SMD_KEY_STATE 0x54415453 #define QCOM_RPM_SCALING_ENABLE_ID 0x2 -#define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id, \ - key) \ +#define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, key) \ static struct clk_smd_rpm _platform##_##_active; \ static struct clk_smd_rpm _platform##_##_name = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ - .rpm_status_id = (stat_id), \ .rpm_key = (key), \ .peer = &_platform##_##_active, \ .rate = INT_MAX, \ @@ -48,7 +46,6 @@ static struct clk_smd_rpm _platform##_##_active = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ - .rpm_status_id = (stat_id), \ .active_only = true, \ .rpm_key = (key), \ .peer = &_platform##_##_name, \ @@ -65,12 +62,11 @@ } #define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, \ - stat_id, r, key) \ + r, key) \ static struct clk_smd_rpm _platform##_##_active; \ static struct clk_smd_rpm _platform##_##_name = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ - .rpm_status_id = (stat_id), \ .rpm_key = (key), \ .branch = true, \ .peer = &_platform##_##_active, \ @@ -88,7 +84,6 @@ static struct clk_smd_rpm _platform##_##_active = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ - .rpm_status_id = (stat_id), \ .active_only = true, \ .rpm_key = (key), \ .branch = true, \ @@ -107,19 +102,19 @@ #define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id) \ __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \ - 0, QCOM_RPM_SMD_KEY_RATE) + QCOM_RPM_SMD_KEY_RATE) #define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r) \ __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, \ - r_id, 0, r, QCOM_RPM_SMD_KEY_ENABLE) + r_id, r, QCOM_RPM_SMD_KEY_ENABLE) #define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id) \ __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \ - 0, QCOM_RPM_SMD_KEY_STATE) + QCOM_RPM_SMD_KEY_STATE) #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id, r) \ __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \ - QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, r, \ + QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ QCOM_RPM_KEY_SOFTWARE_ENABLE) #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, \ @@ -128,7 +123,7 @@ r_id, r); \ __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name##_pin, \ _active##_pin, \ - QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, r, \ + QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY) #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw) @@ -137,7 +132,6 @@ struct clk_smd_rpm { const int rpm_res_type; const int rpm_key; const int rpm_clk_id; - const int rpm_status_id; const bool active_only; bool enabled; bool branch; From patchwork Fri Dec 9 16:48:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 632541 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8C30C2D0CB for ; Fri, 9 Dec 2022 16:49:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229907AbiLIQtR (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id y2-20020a05651c106200b002770fb5722fsm275242ljm.123.2022.12.09.08.49.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 08:49:04 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Alex Elder Subject: [PATCH v3 11/19] clk: qcom: smd-rpm: fix alignment of line breaking backslashes Date: Fri, 9 Dec 2022 18:48:47 +0200 Message-Id: <20221209164855.128798-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> References: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The commit 52a436e0b7fe ("clk: qcom: smd-rpm: Switch to parent_data") introduced ragged right alignment for the line breaking backslash. Fix it to make the code look consistently. Reviewed-by: Alex Elder Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 2075cfd34f99..7e43ecdda763 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -36,10 +36,10 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_ops, \ .name = #_name, \ - .parent_data = &(const struct clk_parent_data){ \ - .fw_name = "xo", \ - .name = "xo_board", \ - }, \ + .parent_data = &(const struct clk_parent_data){ \ + .fw_name = "xo", \ + .name = "xo_board", \ + }, \ .num_parents = 1, \ }, \ }; \ @@ -53,10 +53,10 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_ops, \ .name = #_active, \ - .parent_data = &(const struct clk_parent_data){ \ - .fw_name = "xo", \ - .name = "xo_board", \ - }, \ + .parent_data = &(const struct clk_parent_data){ \ + .fw_name = "xo", \ + .name = "xo_board", \ + }, \ .num_parents = 1, \ }, \ } @@ -74,10 +74,10 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_branch_ops, \ .name = #_name, \ - .parent_data = &(const struct clk_parent_data){ \ - .fw_name = "xo", \ - .name = "xo_board", \ - }, \ + .parent_data = &(const struct clk_parent_data){ \ + .fw_name = "xo", \ + .name = "xo_board", \ + }, \ .num_parents = 1, \ }, \ }; \ @@ -92,10 +92,10 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_branch_ops, \ .name = #_active, \ - .parent_data = &(const struct clk_parent_data){ \ - .fw_name = "xo", \ - .name = "xo_board", \ - }, \ + .parent_data = &(const struct clk_parent_data){ \ + .fw_name = "xo", \ + .name = "xo_board", \ + }, \ .num_parents = 1, \ }, \ } From patchwork Fri Dec 9 16:48:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 632540 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3D04C2D0CD for ; Fri, 9 Dec 2022 16:49:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229770AbiLIQtT (ORCPT ); Fri, 9 Dec 2022 11:49:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229854AbiLIQtL (ORCPT ); Fri, 9 Dec 2022 11:49:11 -0500 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED3B5944FD for ; Fri, 9 Dec 2022 08:49:08 -0800 (PST) Received: by mail-lj1-x232.google.com with SMTP id a19so5540550ljk.0 for ; Fri, 09 Dec 2022 08:49:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DcRM2oQ+Gq4mFc/zMOa9wJeHs53wWSGdrVqO33ePGR0=; b=KCyr+TQ11h0Lp5c23NZni/JHZeSu1zCzBBKzhG6WyLoQkYG2SSQIfk4cx4/HwQhaQW RhyYdLbR/yrmOCIBbeg58nkYulUNe4jL7M4TdT5oy+N3wUvDzUJMdm+dWhLyl4ltbPYr CzFLNFVj7ee0X4PcRbXTjI1UAS04lesOMQTdVma2wc8GrQn0qBMwf2F8pjlMQFoqjHrc IqAB4YrSXWidoXrBmUDfNtBWq3v4ORla81/Z6MzsZPuSKOTUgAUPSSTJlf3GWcD+gpPw zQk37s3Xz1Fsao0O/qHlcU5TsLq5etyKXpDdaSUgRuP17k7UQrHoBvRxdN2uwfCC6bGJ ZjKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DcRM2oQ+Gq4mFc/zMOa9wJeHs53wWSGdrVqO33ePGR0=; b=vmC5AouAzZPWZLZyCErQiEeB/GP37e4rhC9Ya0i3J3aHwHsqShbJFKe+hO0tHEG7Ti MzvBCq96uIuzn4ygoqqOwiqnP6EA0cWSoC7z4NHvKXgKd65XTbvyrs0BfzuJu+kJFrvt z0Z2eF03si1o0igJhxF5dBVhsf+UCsqhTF3CXQar1eeEaHrVo/DYsvOHWN3qRmEgM/2n 02SR1FiF1kpzZ4pvtlsr1BBaxx5wKuxtTnyJwk9xLyKWFVrSOHZIIqlTorKupo96CXik PBWANS7feWYWAGoN4k+KaQRCDQhZWN9Xc9S9Afuf6mF+P99DsKRbOGuvKQQXqL/IWmX5 ELYw== X-Gm-Message-State: ANoB5pkArlLbknd7GITIdpbC+jwvNrx+Pt+rNr6nV7mccPSm5X2cJsOP 8bTnwsRE1EIH+12MybXrgt4DZA== X-Google-Smtp-Source: AA0mqf7O18JBwa1Bhq11w+2oVZ9V3q94+p6gr1kY2+1DKW5pYymZX6JWK9Ueo/FnHNCoTbrh2iy6Ng== X-Received: by 2002:a05:651c:17a7:b0:276:5727:c57a with SMTP id bn39-20020a05651c17a700b002765727c57amr2251993ljb.29.1670604548243; Fri, 09 Dec 2022 08:49:08 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id y2-20020a05651c106200b002770fb5722fsm275242ljm.123.2022.12.09.08.49.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 08:49:07 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Alex Elder Subject: [PATCH v3 14/19] clk: qcom: smd-rpm: simplify XO_BUFFER clocks definitions Date: Fri, 9 Dec 2022 18:48:50 +0200 Message-Id: <20221209164855.128798-15-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> References: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Remove the duplication between the names of the normal and active-only XO_BUFFER and XO_BUFFER_PINCTRL clocks by using preprocessor logic to add _a suffix. Reviewed-by: Alex Elder Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 56 ++++++++++++++++------------------ 1 file changed, 27 insertions(+), 29 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index b32fc7cc1332..c5a4a648ddb1 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -112,17 +112,15 @@ __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \ QCOM_RPM_SMD_KEY_STATE) -#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id, r) \ - __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \ +#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, r_id, r) \ + __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _name##_a, \ QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ QCOM_RPM_KEY_SOFTWARE_ENABLE) -#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, \ - r_id, r) \ - DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, \ - r_id, r); \ +#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, r_id, r) \ + DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, r_id, r); \ __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name##_pin, \ - _active##_pin, \ + _name##_a##_pin, \ QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY) @@ -456,28 +454,28 @@ DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); DEFINE_CLK_SMD_RPM(sm6125, qup_clk, qup_a_clk, QCOM_SMD_RPM_QUP_CLK, 0); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1, bb_clk1_a, 1, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2, bb_clk2_a, 2, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk1, ln_bb_clk1_a, 1, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk2, ln_bb_clk2_a, 2, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1, rf_clk1_a, 4, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2, rf_clk2_a, 5, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3, rf_clk3_a, 6, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk, ln_bb_clk_a, 8, 19200000); - -DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, rf_clk3_a, 6, 38400000); - -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0, cxo_d0_a, 1, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1, cxo_d1_a, 2, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0, cxo_a0_a, 4, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1, cxo_a1_a, 5, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2, cxo_a2_a, 6, 19200000); - -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_clk_a, 7, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_clk1_a, 11, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_clk2_a, 12, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2, 2, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk1, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk2, 2, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3, 3, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1, 4, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2, 5, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3, 6, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk, 8, 19200000); + +DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, 6, 38400000); + +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1, 2, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0, 4, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1, 5, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2, 6, 19200000); + +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, 7, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, 11, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, 12, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, 13, 19200000); static struct clk_smd_rpm *msm8909_clks[] = { [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, From patchwork Fri Dec 9 16:48:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 632539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C45FAC4167B for ; Fri, 9 Dec 2022 16:49:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229655AbiLIQtY (ORCPT ); Fri, 9 Dec 2022 11:49:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229885AbiLIQtO (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id y2-20020a05651c106200b002770fb5722fsm275242ljm.123.2022.12.09.08.49.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 08:49:08 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Alex Elder Subject: [PATCH v3 15/19] clk: qcom: smd-rpm: simplify SMD_RPM/_BRANCH/_QDSS clock definitions Date: Fri, 9 Dec 2022 18:48:51 +0200 Message-Id: <20221209164855.128798-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> References: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Remove the duplication between the names of the normal and active-only clocks by moving common sufixes to the clock definition macros. This simplifies adding new clock definitions and reviewing existing defs. Reviewed-by: Alex Elder Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 96 +++++++++++++++++++--------------- 1 file changed, 53 insertions(+), 43 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index c5a4a648ddb1..a3f08ebcae4e 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -100,17 +100,27 @@ }, \ } -#define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id) \ - __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \ - QCOM_RPM_SMD_KEY_RATE) - -#define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r) \ - __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, \ +#define DEFINE_CLK_SMD_RPM(_platform, _name, type, r_id) \ + __DEFINE_CLK_SMD_RPM(_platform, _name##_clk, _name##_a_clk, \ + type, r_id, QCOM_RPM_SMD_KEY_RATE) + +#define DEFINE_CLK_SMD_RPM_CLK_SRC(_platform, _name, type, r_id) \ + __DEFINE_CLK_SMD_RPM(_platform, \ + _name##_clk_src, _name##_a_clk_src, \ + type, r_id, QCOM_RPM_SMD_KEY_RATE) + +#define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, type, r_id, r) \ + __DEFINE_CLK_SMD_RPM_BRANCH(_platform, \ + _name##_clk, _name##_a_clk, \ + type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE) + +#define DEFINE_CLK_SMD_RPM_BRANCH_A(_platform, _name, type, r_id, r) \ + __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _name##_a, type,\ r_id, r, QCOM_RPM_SMD_KEY_ENABLE) -#define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id) \ - __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \ - QCOM_RPM_SMD_KEY_STATE) +#define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, type, r_id) \ + __DEFINE_CLK_SMD_RPM(_platform, _name##_clk, _name##_a_clk, \ + type, r_id, QCOM_RPM_SMD_KEY_STATE) #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, r_id, r) \ __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _name##_a, \ @@ -408,51 +418,51 @@ static const struct clk_ops clk_smd_rpm_branch_ops = { .recalc_rate = clk_smd_rpm_recalc_rate, }; -DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000); -DEFINE_CLK_SMD_RPM_BRANCH(sm6125, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1, 19200000); -DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); -DEFINE_CLK_SMD_RPM_BRANCH(sm6375, bimc_freq_log, bimc_freq_log_a, QCOM_SMD_RPM_MISC_CLK, 4, 1); +DEFINE_CLK_SMD_RPM_BRANCH_A(sdm660, bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000); +DEFINE_CLK_SMD_RPM_BRANCH(sm6125, qdss, QCOM_SMD_RPM_MISC_CLK, 1, 19200000); +DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss, QCOM_SMD_RPM_MISC_CLK, 1); +DEFINE_CLK_SMD_RPM_BRANCH_A(sm6375, bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1); -DEFINE_CLK_SMD_RPM_BRANCH(msm8992, mss_cfg_ahb_clk, mss_cfg_ahb_a_clk, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000); +DEFINE_CLK_SMD_RPM_BRANCH(msm8992, mss_cfg_ahb, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000); -DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 1, 1000); -DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); -DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 2); +DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1, 1000); +DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); +DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1); +DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3); -DEFINE_CLK_SMD_RPM(sm6125, snoc_periph_clk, snoc_periph_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6125, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM(sm6125, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(sm6125, snoc_lpass_clk, snoc_lpass_a_clk, QCOM_SMD_RPM_BUS_CLK, 5); +DEFINE_CLK_SMD_RPM(msm8916, pcnoc, QCOM_SMD_RPM_BUS_CLK, 0); +DEFINE_CLK_SMD_RPM(msm8916, snoc, QCOM_SMD_RPM_BUS_CLK, 1); +DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc, QCOM_SMD_RPM_BUS_CLK, 2); +DEFINE_CLK_SMD_RPM(msm8974, cnoc, QCOM_SMD_RPM_BUS_CLK, 2); +DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb, QCOM_SMD_RPM_BUS_CLK, 3); +DEFINE_CLK_SMD_RPM(sm6125, snoc_periph, QCOM_SMD_RPM_BUS_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6125, cnoc, QCOM_SMD_RPM_BUS_CLK, 1); +DEFINE_CLK_SMD_RPM(sm6125, snoc, QCOM_SMD_RPM_BUS_CLK, 2); +DEFINE_CLK_SMD_RPM(sm6125, snoc_lpass, QCOM_SMD_RPM_BUS_CLK, 5); -DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); -DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc_clk, cpuss_gnoc_a_clk, QCOM_SMD_RPM_MEM_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); -DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); +DEFINE_CLK_SMD_RPM(msm8916, bimc, QCOM_SMD_RPM_MEM_CLK, 0); +DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc, QCOM_SMD_RPM_MEM_CLK, 1); +DEFINE_CLK_SMD_RPM_CLK_SRC(msm8974, gfx3d, QCOM_SMD_RPM_MEM_CLK, 1); +DEFINE_CLK_SMD_RPM(msm8974, ocmemgx, QCOM_SMD_RPM_MEM_CLK, 2); +DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu, QCOM_SMD_RPM_MEM_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2); +DEFINE_CLK_SMD_RPM(msm8992, ce1, QCOM_SMD_RPM_CE_CLK, 0); +DEFINE_CLK_SMD_RPM(msm8992, ce2, QCOM_SMD_RPM_CE_CLK, 1); +DEFINE_CLK_SMD_RPM(msm8994, ce3, QCOM_SMD_RPM_CE_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8976, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); +DEFINE_CLK_SMD_RPM(msm8976, ipa, QCOM_SMD_RPM_IPA_CLK, 0); -DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0); +DEFINE_CLK_SMD_RPM(qcm2290, hwkm, QCOM_SMD_RPM_HWKM_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6125, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6125, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 1); +DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm, QCOM_SMD_RPM_MMAXI_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6125, mmnrt, QCOM_SMD_RPM_MMAXI_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6125, mmrt, QCOM_SMD_RPM_MMAXI_CLK, 1); -DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0); +DEFINE_CLK_SMD_RPM(qcm2290, pka, QCOM_SMD_RPM_PKA_CLK, 0); -DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); +DEFINE_CLK_SMD_RPM(qcs404, qpic, QCOM_SMD_RPM_QPIC_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6125, qup_clk, qup_a_clk, QCOM_SMD_RPM_QUP_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6125, qup, QCOM_SMD_RPM_QUP_CLK, 0); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1, 1, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2, 2, 19200000); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id y2-20020a05651c106200b002770fb5722fsm275242ljm.123.2022.12.09.08.49.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Dec 2022 08:49:11 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Alex Elder Subject: [PATCH v3 18/19] clk: qcom: smd-rpm: rename SMD_RPM_BUS clocks Date: Fri, 9 Dec 2022 18:48:54 +0200 Message-Id: <20221209164855.128798-19-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> References: <20221209164855.128798-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add special macro for the clocks of QCOM_SMD_RPM_BUS_CLK type. Use it to insert the _bus_N part into the clock symbol name. The system (and userspace) name of these clocks remains intact. Reviewed-by: Konrad Dybcio Reviewed-by: Alex Elder Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 252 +++++++++++++++++---------------- 1 file changed, 131 insertions(+), 121 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 4db92d2d91b8..b8e649a6a76c 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -25,13 +25,14 @@ #define QCOM_RPM_SMD_KEY_STATE 0x54415453 #define QCOM_RPM_SCALING_ENABLE_ID 0x2 -#define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, key) \ - static struct clk_smd_rpm _platform##_##_active; \ - static struct clk_smd_rpm _platform##_##_name = { \ +#define __DEFINE_CLK_SMD_RPM_PREFIX(_platform, _prefix, _name, _active, \ + type, r_id, key) \ + static struct clk_smd_rpm _platform##_##_prefix##_active; \ + static struct clk_smd_rpm _platform##_##_prefix##_name = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ .rpm_key = (key), \ - .peer = &_platform##_##_active, \ + .peer = &_platform##_##_prefix##_active, \ .rate = INT_MAX, \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_ops, \ @@ -43,12 +44,12 @@ .num_parents = 1, \ }, \ }; \ - static struct clk_smd_rpm _platform##_##_active = { \ + static struct clk_smd_rpm _platform##_##_prefix##_active = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ .active_only = true, \ .rpm_key = (key), \ - .peer = &_platform##_##_name, \ + .peer = &_platform##_##_prefix##_name, \ .rate = INT_MAX, \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_ops, \ @@ -61,6 +62,10 @@ }, \ } +#define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, key) \ + __DEFINE_CLK_SMD_RPM_PREFIX(_platform, /* empty */, _name, _active, \ + type, r_id, key) + #define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_platform, _prefix, _name, _active,\ type, r_id, r, key) \ static struct clk_smd_rpm _platform##_##_prefix##_active; \ @@ -109,6 +114,11 @@ __DEFINE_CLK_SMD_RPM(_platform, _name##_clk, _name##_a_clk, \ type, r_id, QCOM_RPM_SMD_KEY_RATE) +#define DEFINE_CLK_SMD_RPM_BUS(_platform, _name, r_id) \ + __DEFINE_CLK_SMD_RPM_PREFIX(_platform, bus_##r_id##_, \ + _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \ + QCOM_RPM_SMD_KEY_RATE) + #define DEFINE_CLK_SMD_RPM_CLK_SRC(_platform, _name, type, r_id) \ __DEFINE_CLK_SMD_RPM(_platform, \ _name##_clk_src, _name##_a_clk_src, \ @@ -442,15 +452,15 @@ DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1); DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8916, pcnoc, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8916, snoc, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8974, cnoc, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb, QCOM_SMD_RPM_BUS_CLK, 3); -DEFINE_CLK_SMD_RPM(sm6125, snoc_periph, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6125, cnoc, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM(sm6125, snoc, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(sm6125, snoc_lpass, QCOM_SMD_RPM_BUS_CLK, 5); +DEFINE_CLK_SMD_RPM_BUS(msm8916, pcnoc, 0); +DEFINE_CLK_SMD_RPM_BUS(msm8916, snoc, 1); +DEFINE_CLK_SMD_RPM_BUS(msm8936, sysmmnoc, 2); +DEFINE_CLK_SMD_RPM_BUS(msm8974, cnoc, 2); +DEFINE_CLK_SMD_RPM_BUS(msm8974, mmssnoc_ahb, 3); +DEFINE_CLK_SMD_RPM_BUS(sm6125, snoc_periph, 0); +DEFINE_CLK_SMD_RPM_BUS(sm6125, cnoc, 1); +DEFINE_CLK_SMD_RPM_BUS(sm6125, snoc, 2); +DEFINE_CLK_SMD_RPM_BUS(sm6125, snoc_lpass, 5); DEFINE_CLK_SMD_RPM(msm8916, bimc, QCOM_SMD_RPM_MEM_CLK, 0); DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc, QCOM_SMD_RPM_MEM_CLK, 1); @@ -500,10 +510,10 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, 12, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, 13, 19200000); static struct clk_smd_rpm *msm8909_clks[] = { - [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, @@ -534,10 +544,10 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8909 = { }; static struct clk_smd_rpm *msm8916_clks[] = { - [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, @@ -566,14 +576,14 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8916 = { }; static struct clk_smd_rpm *msm8936_clks[] = { - [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_SYSMMNOC_CLK] = &msm8936_sysmmnoc_clk, - [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_sysmmnoc_a_clk, + [RPM_SMD_SYSMMNOC_CLK] = &msm8936_bus_2_sysmmnoc_clk, + [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_bus_2_sysmmnoc_a_clk, [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, @@ -600,14 +610,14 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8936 = { }; static struct clk_smd_rpm *msm8974_clks[] = { - [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, - [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, - [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, + [RPM_SMD_PNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, + [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_bus_3_mmssnoc_ahb_clk, + [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_bus_3_mmssnoc_ahb_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src, [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src, @@ -652,14 +662,14 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { static struct clk_smd_rpm *msm8976_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_SYSMMNOC_CLK] = &msm8936_sysmmnoc_clk, - [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_sysmmnoc_a_clk, + [RPM_SMD_SYSMMNOC_CLK] = &msm8936_bus_2_sysmmnoc_clk, + [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_bus_2_sysmmnoc_a_clk, [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, @@ -686,18 +696,18 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { static struct clk_smd_rpm *msm8992_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, + [RPM_SMD_PNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src, [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, @@ -716,8 +726,8 @@ static struct clk_smd_rpm *msm8992_clks[] = { [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_clk_a, - [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, - [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, + [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_bus_3_mmssnoc_ahb_clk, + [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_bus_3_mmssnoc_ahb_a_clk, [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_branch_mss_cfg_ahb_clk, [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_branch_mss_cfg_ahb_a_clk, [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, @@ -744,18 +754,18 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { static struct clk_smd_rpm *msm8994_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, + [RPM_SMD_PNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src, [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, @@ -774,8 +784,8 @@ static struct clk_smd_rpm *msm8994_clks[] = { [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_clk_a, - [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, - [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, + [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_bus_3_mmssnoc_ahb_clk, + [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_bus_3_mmssnoc_ahb_a_clk, [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_branch_mss_cfg_ahb_clk, [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_branch_mss_cfg_ahb_a_clk, [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, @@ -802,12 +812,12 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8994 = { }; static struct clk_smd_rpm *msm8996_clks[] = { - [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, @@ -856,10 +866,10 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { static struct clk_smd_rpm *qcs404_clks[] = { [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, - [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_PNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk, @@ -886,12 +896,12 @@ static struct clk_smd_rpm *msm8998_clks[] = { [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, @@ -944,12 +954,12 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { static struct clk_smd_rpm *sdm660_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, - [RPM_SMD_CNOC_PERIPH_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_CNOC_PERIPH_A_CLK] = &msm8916_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, + [RPM_SMD_CNOC_PERIPH_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_CNOC_PERIPH_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_MMSSNOC_AXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, @@ -990,8 +1000,8 @@ static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { static struct clk_smd_rpm *mdm9607_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, @@ -1012,16 +1022,16 @@ static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = { static struct clk_smd_rpm *msm8953_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, - [RPM_SMD_SYSMMNOC_CLK] = &msm8936_sysmmnoc_clk, - [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_sysmmnoc_a_clk, + [RPM_SMD_SYSMMNOC_CLK] = &msm8936_bus_2_sysmmnoc_clk, + [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_bus_2_sysmmnoc_a_clk, [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, @@ -1048,8 +1058,8 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8953 = { static struct clk_smd_rpm *sm6125_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, + [RPM_SMD_SNOC_CLK] = &sm6125_bus_2_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &sm6125_bus_2_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &sm6125_branch_qdss_clk, @@ -1058,8 +1068,8 @@ static struct clk_smd_rpm *sm6125_clks[] = { [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk, + [RPM_SMD_CNOC_CLK] = &sm6125_bus_1_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &sm6125_bus_1_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, @@ -1076,10 +1086,10 @@ static struct clk_smd_rpm *sm6125_clks[] = { [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, - [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk, - [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk, - [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk, - [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk, + [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_bus_0_snoc_periph_clk, + [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_bus_0_snoc_periph_a_clk, + [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_bus_5_snoc_lpass_clk, + [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_bus_5_snoc_lpass_a_clk, }; static const struct rpm_smd_clk_desc rpm_clk_sm6125 = { @@ -1091,8 +1101,8 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6125 = { static struct clk_smd_rpm *sm6115_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, + [RPM_SMD_SNOC_CLK] = &sm6125_bus_2_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &sm6125_bus_2_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &sm6125_branch_qdss_clk, @@ -1101,8 +1111,8 @@ static struct clk_smd_rpm *sm6115_clks[] = { [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk, + [RPM_SMD_CNOC_CLK] = &sm6125_bus_1_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &sm6125_bus_1_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, @@ -1113,10 +1123,10 @@ static struct clk_smd_rpm *sm6115_clks[] = { [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, - [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk, - [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk, - [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk, - [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk, + [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_bus_0_snoc_periph_clk, + [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_bus_0_snoc_periph_a_clk, + [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_bus_5_snoc_lpass_clk, + [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_bus_5_snoc_lpass_a_clk, [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, @@ -1131,14 +1141,14 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { static struct clk_smd_rpm *sm6375_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, + [RPM_SMD_SNOC_CLK] = &sm6125_bus_2_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &sm6125_bus_2_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &sm6125_branch_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &sm6125_branch_qdss_a_clk, - [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk, + [RPM_SMD_CNOC_CLK] = &sm6125_bus_1_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &sm6125_bus_1_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, @@ -1147,10 +1157,10 @@ static struct clk_smd_rpm *sm6375_clks[] = { [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, - [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk, - [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk, - [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk, - [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk, + [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_bus_0_snoc_periph_clk, + [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_bus_0_snoc_periph_a_clk, + [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_bus_5_snoc_lpass_clk, + [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_bus_5_snoc_lpass_a_clk, [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, [RPM_SMD_HWKM_CLK] = &qcm2290_hwkm_clk, @@ -1168,8 +1178,8 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6375 = { static struct clk_smd_rpm *qcm2290_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, + [RPM_SMD_SNOC_CLK] = &sm6125_bus_2_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &sm6125_bus_2_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &sm6125_branch_qdss_clk, @@ -1178,8 +1188,8 @@ static struct clk_smd_rpm *qcm2290_clks[] = { [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a, [RPM_SMD_RF_CLK3] = &qcm2290_38m4_rf_clk3, [RPM_SMD_RF_CLK3_A] = &qcm2290_38m4_rf_clk3_a, - [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk, + [RPM_SMD_CNOC_CLK] = &sm6125_bus_1_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &sm6125_bus_1_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, @@ -1188,10 +1198,10 @@ static struct clk_smd_rpm *qcm2290_clks[] = { [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, - [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk, - [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk, - [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk, - [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk, + [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_bus_0_snoc_periph_clk, + [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_bus_0_snoc_periph_a_clk, + [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_bus_5_snoc_lpass_clk, + [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_bus_5_snoc_lpass_a_clk, [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk,