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Fri, 09 Dec 2022 07:15:40 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Jiaxun Yang , Bernhard Beschow , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Thomas Huth , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-8.0 1/7] hw/mips/Kconfig: Introduce CONFIG_GT64120 to select gt64xxx_pci.c Date: Fri, 9 Dec 2022 16:15:27 +0100 Message-Id: <20221209151533.69516-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221209151533.69516-1-philmd@linaro.org> References: <20221209151533.69516-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Bernhard Beschow Reviewed-by: Bernhard Beschow Reviewed-by: Richard Henderson --- hw/mips/Kconfig | 6 ++++++ hw/mips/meson.build | 3 ++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index 725525358d..d6bbbe7069 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -1,5 +1,6 @@ config MALTA bool + select GT64120 select ISA_SUPERIO config MIPSSIM @@ -59,3 +60,8 @@ config MIPS_BOSTON config FW_CFG_MIPS bool + +config GT64120 + bool + select PCI + select I8259 diff --git a/hw/mips/meson.build b/hw/mips/meson.build index dd0101ad4d..6ccd385df0 100644 --- a/hw/mips/meson.build +++ b/hw/mips/meson.build @@ -2,7 +2,8 @@ mips_ss = ss.source_set() mips_ss.add(files('bootloader.c', 'mips_int.c')) mips_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c')) mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 'loongson3_virt.c')) -mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c')) +mips_ss.add(when: 'CONFIG_MALTA', if_true: files('malta.c')) +mips_ss.add(when: 'CONFIG_GT64120', if_true: files('gt64xxx_pci.c')) mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c')) if 'CONFIG_TCG' in config_all From patchwork Fri Dec 9 15:15:28 2022 Content-Type: text/plain; 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- configs/devices/mips-softmmu/common.mak | 1 - hw/mips/Kconfig | 1 + hw/mips/gt64xxx_pci.c | 8 ++++++++ hw/mips/malta.c | 7 ------- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/configs/devices/mips-softmmu/common.mak b/configs/devices/mips-softmmu/common.mak index 416161f833..c2b5f322fc 100644 --- a/configs/devices/mips-softmmu/common.mak +++ b/configs/devices/mips-softmmu/common.mak @@ -26,7 +26,6 @@ CONFIG_IDE_ISA=y CONFIG_PFLASH_CFI01=y CONFIG_I8259=y CONFIG_MC146818RTC=y -CONFIG_EMPTY_SLOT=y CONFIG_MIPS_CPS=y CONFIG_MIPS_ITU=y CONFIG_MALTA=y diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index d6bbbe7069..8f7bce38fb 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -64,4 +64,5 @@ config FW_CFG_MIPS config GT64120 bool select PCI + select EMPTY_SLOT select I8259 diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 19d0d9889f..1b9ac7f792 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -28,6 +28,7 @@ #include "qemu/log.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" +#include "hw/misc/empty_slot.h" #include "migration/vmstate.h" #include "hw/intc/i8259.h" #include "hw/irq.h" @@ -1162,6 +1163,13 @@ static void gt64120_realize(DeviceState *dev, Error **errp) PCI_DEVFN(18, 0), TYPE_PCI_BUS); pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci"); + + /* + * The whole address space decoded by the GT-64120A doesn't generate + * exception when accessing invalid memory. Create an empty slot to + * emulate this feature. + */ + empty_slot_init("GT64120", 0, 0x20000000); } static void gt64120_pci_realize(PCIDevice *d, Error **errp) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index c0a2e0ab04..ba92022f87 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -53,7 +53,6 @@ #include "sysemu/runstate.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "hw/misc/empty_slot.h" #include "sysemu/kvm.h" #include "semihosting/semihost.h" #include "hw/mips/cps.h" @@ -1393,12 +1392,6 @@ void mips_malta_init(MachineState *machine) /* Northbridge */ dev = sysbus_create_simple("gt64120", -1, NULL); pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci")); - /* - * The whole address space decoded by the GT-64120A doesn't generate - * exception when accessing invalid memory. Create an empty slot to - * emulate this feature. - */ - empty_slot_init("GT64120", 0, 0x20000000); /* Southbridge */ piix4 = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true, From patchwork Fri Dec 9 15:15:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 632264 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp918244pvb; Fri, 9 Dec 2022 07:18:36 -0800 (PST) X-Google-Smtp-Source: AA0mqf6hNjR7VW5d/kjxpvMNLy7FTIZ58cISwfhRmhDgwY3wmQZEymcjxpOb6P3zPkhdky1unXHz X-Received: by 2002:a05:6214:b0d:b0:4c7:1fa7:25e7 with SMTP id u13-20020a0562140b0d00b004c71fa725e7mr9779867qvj.3.1670599115829; Fri, 09 Dec 2022 07:18:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670599115; cv=none; d=google.com; s=arc-20160816; b=toHkKGWqBl+b/3Le9QWyBAcGC7nNObr16J92++rxZsRbmyoPmsqpRURkYohxNLP1aB 8QWBh4ITaDXUD02XoIiIXUyPefPi9+Jpv1xQnO16bTWTCEyhHfp5Z7fmDhyJzDzfLLCk 8dP0CUQ/VMRy43vdJgdFRKOxwRJsItu9dixXQmkTaS90UhqznyJdAASnRtN310fq8wes 5KXampZC9Abe3y/7APh5JJS5yL//priCC25F8LFh0/VuMj32a4XPHQH6rLcgkJiiC3vr KLZ3p9ShvFW8BPQYsU0kUJ+WUJBYJ9Yg1kQOH4sGpLjMS+ZbhbYC4ftDz3z6dzSm7MW1 WAAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KLG0xoWyhhBW457w36XngZbKe3qdM+Ngb1nAJqophKg=; b=FPOQCeUQNXDc6W1TnIG8cohlXoL2zvXwgIXJ6VgQ7VtgqgKgtcT8L8suiulpr4sb7K i56aVfsgJzuGCQnDXONHyO1iwgZbnYZoORDVYUZGX0nJ9EbPWeZzEk/a9xTu6esbzCNk mb1tsuyVy5f6Eth8B8rTQBJjXRV/dTHLBRuoysp97LcVA0xJ+f2v3xVExEMg9Sq5zZir 7V/xYjo/Xr+qFwWH8LP5S49HF5r08/AUFJ2H62Pli3y/rXnpzgMv8J8/3ILzA7r/zsr5 qhyyf979T/JTHzXQQBJk4LMmwdFPanF80QxEUTBwNja/P1yhX2c4jB4hMWPF29nmPQVM gLHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=We5OO8WG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Fri, 09 Dec 2022 07:15:50 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Jiaxun Yang , Bernhard Beschow , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Thomas Huth , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Subject: [PATCH-for-8.0 3/7] hw/mips/gt64xxx_pci: Manage endian bits with the RegisterField API Date: Fri, 9 Dec 2022 16:15:29 +0100 Message-Id: <20221209151533.69516-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221209151533.69516-1-philmd@linaro.org> References: <20221209151533.69516-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/gt64xxx_pci.c | 37 +++++++++++++++++++++++++------------ 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 1b9ac7f792..8c9ec80f7c 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "qemu/units.h" #include "qemu/log.h" +#include "hw/registerfields.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" #include "hw/misc/empty_slot.h" @@ -41,6 +42,9 @@ #define GT_CPU (0x000 >> 2) #define GT_MULTI (0x120 >> 2) +REG32(GT_CPU, 0x000) +FIELD(GT_CPU, Endianess, 12, 1) + /* CPU Address Decode */ #define GT_SCS10LD (0x008 >> 2) #define GT_SCS10HD (0x010 >> 2) @@ -210,6 +214,13 @@ #define GT_PCI0_CFGADDR (0xcf8 >> 2) #define GT_PCI0_CFGDATA (0xcfc >> 2) +REG32(GT_PCI0_CMD, 0xc00) +FIELD(GT_PCI0_CMD, MByteSwap, 0, 1) +FIELD(GT_PCI0_CMD, SByteSwap, 16, 1) +REG32(GT_PCI1_CMD, 0xc80) +FIELD(GT_PCI1_CMD, MByteSwap, 0, 1) +FIELD(GT_PCI1_CMD, SByteSwap, 16, 1) + /* Interrupts */ #define GT_INTRCAUSE (0xc18 >> 2) #define GT_INTRMASK (0xc1c >> 2) @@ -983,15 +994,17 @@ static const MemoryRegionOps isd_mem_ops = { static void gt64120_reset(DeviceState *dev) { GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev); +#if TARGET_BIG_ENDIAN + unsigned cpu_le = 0; +#else + unsigned cpu_le = 1; +#endif /* FIXME: Malta specific hw assumptions ahead */ /* CPU Configuration */ -#if TARGET_BIG_ENDIAN s->regs[GT_CPU] = 0x00000000; -#else - s->regs[GT_CPU] = 0x00001000; -#endif + s->regs[GT_CPU] = FIELD_DP32(s->regs[GT_CPU], GT_CPU, Endianess, cpu_le); s->regs[GT_MULTI] = 0x00000003; /* CPU Address decode */ @@ -1098,11 +1111,11 @@ static void gt64120_reset(DeviceState *dev) s->regs[GT_TC_CONTROL] = 0x00000000; /* PCI Internal */ -#if TARGET_BIG_ENDIAN s->regs[GT_PCI0_CMD] = 0x00000000; -#else - s->regs[GT_PCI0_CMD] = 0x00010001; -#endif + s->regs[GT_PCI0_CMD] = FIELD_DP32(s->regs[GT_PCI0_CMD], + GT_PCI0_CMD, MByteSwap, cpu_le); + s->regs[GT_PCI0_CMD] = FIELD_DP32(s->regs[GT_PCI0_CMD], + GT_PCI0_CMD, SByteSwap, cpu_le); s->regs[GT_PCI0_TOR] = 0x0000070f; s->regs[GT_PCI0_BS_SCS10] = 0x00fff000; s->regs[GT_PCI0_BS_SCS32] = 0x00fff000; @@ -1119,11 +1132,11 @@ static void gt64120_reset(DeviceState *dev) s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000; s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000; s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000; -#if TARGET_BIG_ENDIAN s->regs[GT_PCI1_CMD] = 0x00000000; -#else - s->regs[GT_PCI1_CMD] = 0x00010001; -#endif + s->regs[GT_PCI1_CMD] = FIELD_DP32(s->regs[GT_PCI1_CMD], + GT_PCI1_CMD, MByteSwap, cpu_le); + s->regs[GT_PCI1_CMD] = FIELD_DP32(s->regs[GT_PCI1_CMD], + GT_PCI1_CMD, SByteSwap, cpu_le); s->regs[GT_PCI1_TOR] = 0x0000070f; s->regs[GT_PCI1_BS_SCS10] = 0x00fff000; s->regs[GT_PCI1_BS_SCS32] = 0x00fff000; From patchwork Fri Dec 9 15:15:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 632262 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp917868pvb; Fri, 9 Dec 2022 07:18:01 -0800 (PST) X-Google-Smtp-Source: AA0mqf4PozAnehuNbsSNVoKFJS9vtXycT98FWAQsnUJKZIDAzOeSJflKUXzyHwJ8c4ttn7wW6lHC X-Received: by 2002:a05:7500:4d93:b0:ea:a1ac:7c5c with SMTP id kz19-20020a0575004d9300b000eaa1ac7c5cmr439292gab.10.1670599080947; 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Add a 'cpu_big_endian' property which sets the byte-swapping options if required. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/gt64xxx_pci.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 8c9ec80f7c..9ae4953d1e 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -26,6 +26,7 @@ #include "qapi/error.h" #include "qemu/units.h" #include "qemu/log.h" +#include "hw/qdev-properties.h" #include "hw/registerfields.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" @@ -242,6 +243,8 @@ FIELD(GT_PCI1_CMD, SByteSwap, 16, 1) OBJECT_DECLARE_SIMPLE_TYPE(GT64120State, GT64120_PCI_HOST_BRIDGE) +#define FEAT_CPU_LE 0 + struct GT64120State { PCIHostState parent_obj; @@ -252,6 +255,9 @@ struct GT64120State { PCI_MAPPING_ENTRY(ISD); MemoryRegion pci0_mem; AddressSpace pci0_mem_as; + + /* properties */ + uint32_t features; }; /* Adjust range to avoid touching space which isn't mappable via PCI */ @@ -994,11 +1000,7 @@ static const MemoryRegionOps isd_mem_ops = { static void gt64120_reset(DeviceState *dev) { GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev); -#if TARGET_BIG_ENDIAN - unsigned cpu_le = 0; -#else - unsigned cpu_le = 1; -#endif + unsigned cpu_le = extract32(s->features, FEAT_CPU_LE, 1); /* FIXME: Malta specific hw assumptions ahead */ @@ -1229,11 +1231,18 @@ static const TypeInfo gt64120_pci_info = { }, }; +static Property gt64120_properties[] = { + DEFINE_PROP_BIT("cpu-little-endian", GT64120State, + features, FEAT_CPU_LE, !TARGET_BIG_ENDIAN), + DEFINE_PROP_END_OF_LIST(), +}; + static void gt64120_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + device_class_set_props(dc, gt64120_properties); dc->realize = gt64120_realize; dc->reset = gt64120_reset; dc->vmsd = &vmstate_gt64120; From patchwork Fri Dec 9 15:15:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 632259 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp916968pvb; Fri, 9 Dec 2022 07:16:45 -0800 (PST) X-Google-Smtp-Source: AA0mqf4+W7gYH/sOHtkXK17LGqSe++XQ630Qy2puTz/h/4yZC6u4QFngnpWfxlNTTaFzgitLU3Gw X-Received: by 2002:ac8:75ce:0:b0:39c:da1f:f80d with SMTP id z14-20020ac875ce000000b0039cda1ff80dmr8251184qtq.51.1670599004832; Fri, 09 Dec 2022 07:16:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670599004; cv=none; d=google.com; s=arc-20160816; b=xa64w6ZFxj/25Fx5xj8s346i1zyjBsVJ719Ot6EsHmuSMHw5PAPSd9P1a/0C94tboF IfAB6SE+hnTEOFOiaPRrsVjGkgwOEE4FlZo5mi6/oKi2QQNLo5x1H2AGXa3iIC4TYPfU pMbm1HsRM+9xTPicsoZwe8nqcApIowWitJoWkQWqgwg29yEkTC1ZIIDe2VEB5FtW+SRZ 8jqh8/cno8WzJcW4vbunYXN29z3vhZkbYDJyKk145eKmyV6L8rxf80w+7dVEH3ntOTFV P+AzdxgIGB3i5qEV3eah8LD/zMvLV6EJDb4nbIE7pe0erl0O6WcKuTkl0axWnHnh04i2 ac9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=hLnlg0af127g44EFIKtJ/oSICYhWK5zaYVn5ekJtC5E=; b=Rmkm2eMcN+sXJZA12YIE1X8eFRsra4QAPm17kHSPDUpAm7aaAlwQRARttImIcrJ7wE WmNXdpAr2MnEbUjHIHNiFk4i52fNavJ/tusC1x0lq2Qbulsh2EcVaQ8sldJAOLtBH+pm QDW/oj7fENddY/R/TPMShE7gNmTs5HNene6Fxlm8hggB6PhID/KSXtkuq5WdcXozVe2p uYB5/6E/+8HUkBMb3gTVxzpGgeHqirvGJ0BosVdew8N8kxlqB76r+lwKTdnoOyaZxDUP rST9tapJJQWNgN0qO8aIFbTNrKVh4LKfh1l/m0tYojqiCHObXuU0O5EvwxiZa89j1STu ch6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i1qeGqXB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l13-20020ac84a8d000000b0039a2d64c513si896314qtq.337.2022.12.09.07.16.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Dec 2022 07:16:44 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i1qeGqXB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p3f6g-00050v-5z; Fri, 09 Dec 2022 10:16:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p3f6a-00050H-FH for qemu-devel@nongnu.org; Fri, 09 Dec 2022 10:16:04 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p3f6Y-0008Cu-Uo for qemu-devel@nongnu.org; Fri, 09 Dec 2022 10:16:04 -0500 Received: by mail-wm1-x332.google.com with SMTP id v7so91103wmn.0 for ; Fri, 09 Dec 2022 07:16:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hLnlg0af127g44EFIKtJ/oSICYhWK5zaYVn5ekJtC5E=; b=i1qeGqXB9DZDIhw5ua7m4WaGp1ghRQnGu1Ricsq5tUaCVdwv3w5QTKlMloMukEy2AS O5OJkU2cqK029N153Nm0ceJ81gaJvbdkCpKpZ+Ivef2iLsGl9Lvpo4BTsCQuYEnl0nh7 BECqj4OTrSWBTtMAAFqk81OcWZ87j2YjuC2lp3gtDLmJyAZUvGPEb3i+Qib15Xw2jJDG WySeldXg0wfCTHwRRp48aXXwU2fDlUCVwb52wOSAi7KQHWZGMacdhipASX2rdhVctAI/ XRSX987CqOtmtmZ/JjmHcaqFy9bggSvdDyZV+fYrqubG57szaIUm4e3POfdBW4pzvqNN fvWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hLnlg0af127g44EFIKtJ/oSICYhWK5zaYVn5ekJtC5E=; b=nK/Yai5FND0WBgtrwrRf8mHnjPMsE6uEtXlwqaD9d7LWjKB0m8VMfcSviHC8HfPTwZ +UQP4b88TSu8UYOljHe3KLvOIobO3B1l0RZuVQJf85NScolhgZDEBoMXFSS4UXK0MO1X VbriU9GHlNh/NYH0NceuPmVlf7IZzuYzBHmkS5ex+sLHDg8nkW1oKVUQX+jRqeqbTWXA gadzCobgYoHRZWkTSVQiB6L2sc/EynKqeUE4JBE/4PRNCn06ZtKu3UWpp1Y3f4JjqztR drlJuy7Zd6Hycb+jXyCR2i5pcuNCGpvWTcoFPKc/oX8g+/goFNas00rnxPUBenxonbis lzkg== X-Gm-Message-State: ANoB5pn3tfwFFkYRtPa9KsImU9GJ2LW8BxdbODvomVDLUfvosrD82nS1 HYgcZufhI63AEMvycEOoitNsKuiSt323KsQTcH0= X-Received: by 2002:a05:600c:34ca:b0:3cf:88c1:3a89 with SMTP id d10-20020a05600c34ca00b003cf88c13a89mr5321822wmq.26.1670598960277; Fri, 09 Dec 2022 07:16:00 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id h67-20020a1c2146000000b003d1de805de5sm42811wmh.16.2022.12.09.07.15.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 09 Dec 2022 07:15:59 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Jiaxun Yang , Bernhard Beschow , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Thomas Huth , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno Subject: [PATCH-for-8.0 5/7] hw/mips/malta: Explicit GT64120 endianness upon device creation Date: Fri, 9 Dec 2022 16:15:31 +0100 Message-Id: <20221209151533.69516-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221209151533.69516-1-philmd@linaro.org> References: <20221209151533.69516-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Propagate the controller endianess from the machine, setting the "cpu-little-endian" property. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/mips/malta.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index ba92022f87..1f4e0c7acc 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1390,7 +1390,9 @@ void mips_malta_init(MachineState *machine) stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420); /* Northbridge */ - dev = sysbus_create_simple("gt64120", -1, NULL); + dev = qdev_new("gt64120"); + qdev_prop_set_bit(dev, "cpu-little-endian", !be); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci")); /* Southbridge */ From patchwork Fri Dec 9 15:15:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 632260 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp917076pvb; Fri, 9 Dec 2022 07:16:55 -0800 (PST) X-Google-Smtp-Source: AA0mqf5oXtomRbi5mnyqNrPuy3hwtxHektBPfCF5VKv3zQ9rOsUqlAd/Uw5mgfkAs+ioHNPAKJ6r X-Received: by 2002:a05:7500:1c9:b0:ea:6e12:8077 with SMTP id b9-20020a05750001c900b000ea6e128077mr577068gaa.15.1670599015042; Fri, 09 Dec 2022 07:16:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670599015; cv=none; d=google.com; s=arc-20160816; b=FWRi4iny+W3+oyx2Ywoen6Sl6hb593qkyWi7tI/ez+6KSv9ZJQaB3QHcAq5NEoA6lC og86IRJxOKfhyyRZrrikNX6uDU0a/X2prko7dbfa3avA/+WC5iEaR2i+PYEZ4Bdi7qPs MoHFDt7QkFKRPHtgnCTKbl9tXi/6920wScVJzftFzf8ng/Y7BIBg7ySxXYmfyHs2+GOE BG76XpfaEu5LWNhN2gVq8WvvPtPGGRZuGl50wuYCfKai9wvJretuCp3tzgnrKds2VVpv CQaq3+rLnzydubNX4OPao/lo8K+hEOdWNtmIWEvZZTm/vPkuM+dTtZ93/TbHTpjmvNvG CV1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PKYgngh5eKPOlW1JWGuhao9lgG0+kDitgT4eXHlFVxA=; b=MVLrFRqYAxOSiat1S+Pa/R7QR7zb3+opXzTD2qPEqAyAVBiZkiXVJ5WU3bUfXweK3x kkj8/riy1aONASIx5T4lIiG7MThbLHv01Bnw0ZI6CcmyQ2eA6PnAC5Ylh+xLRZwXkq1K w+GcOOTc+KCy9PdAodfQ6mqBBB+X5sxBYxFFViT296UV7jXsWYDx+ks+9DC4BrGgoc2t LiTE0QNFbh93yTA86xDS/8M+AVfHyFDBT3tbe3UanWfPQRSjL2qar6uh3LcWyha4a1tj dTt5fizHQAJwc1PGQqvqyZNUNIEj9OHjV8yZdq+TS8DoOH+MeFC1cDXz7MBZHDRDvNpA NK7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jQLcSXka; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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We don't need to set a default. This allow us to remove the target specificity from the build system. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/mips/gt64xxx_pci.c | 2 +- hw/mips/meson.build | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 9ae4953d1e..b05b2b3acd 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -1233,7 +1233,7 @@ static const TypeInfo gt64120_pci_info = { static Property gt64120_properties[] = { DEFINE_PROP_BIT("cpu-little-endian", GT64120State, - features, FEAT_CPU_LE, !TARGET_BIG_ENDIAN), + features, FEAT_CPU_LE, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/mips/meson.build b/hw/mips/meson.build index 6ccd385df0..152103f15f 100644 --- a/hw/mips/meson.build +++ b/hw/mips/meson.build @@ -3,7 +3,7 @@ mips_ss.add(files('bootloader.c', 'mips_int.c')) mips_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c')) mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 'loongson3_virt.c')) mips_ss.add(when: 'CONFIG_MALTA', if_true: files('malta.c')) -mips_ss.add(when: 'CONFIG_GT64120', if_true: files('gt64xxx_pci.c')) +softmmu_ss.add(when: 'CONFIG_GT64120', if_true: files('gt64xxx_pci.c')) mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c')) if 'CONFIG_TCG' in config_all From patchwork Fri Dec 9 15:15:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 632261 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp917822pvb; Fri, 9 Dec 2022 07:17:58 -0800 (PST) X-Google-Smtp-Source: AA0mqf4Y9vRzd0T1YfwYFHcAl8wjCZJf+kzOzlyC1IuxWm/Z7E26/6DiVZyp3n3s9lA5evXv49ZL X-Received: by 2002:a05:7500:1e96:b0:ea:5c46:73a4 with SMTP id fc22-20020a0575001e9600b000ea5c4673a4mr523934gab.58.1670599078193; Fri, 09 Dec 2022 07:17:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1670599078; cv=none; d=google.com; s=arc-20160816; b=fc9fonMWezugzsJ/NxZOkQPyAQ/sW6yrhNGnvSv1EDTgpjgnnX+soiJECeqmJH2K/p XUYKEnJmYlTG0vmttMcwz5EK7gtrpoQowugvF64eYtfzL+DTlcKfXcdPr3QjuNiqtP/q sAb1dVIxKsFpVrLXyFfpcP++dn2APxdEGjg5L8Wk5cDHlS5u2VRdUq/sWpPokhY2Lv3w 3ME1zsw/dWQTBvU4nJPewYAEuCuk7dNvh9rxGaSrpXhbSsoM3ZJCc3tEVGlSYVUeX4v0 2TwKdp7N9kHJH3+ta4VyiKIDV5mR1WJyoPwrxKMJ049W4pDasPDl+268pvJydZcwFl9+ SxeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=X94vOjJli80zkgb0fhpVEEc/w9edJfWAmH0Oey1raYk=; b=mCuZuJBYG1ofLG26MKB9/pL3rvDhNH40XNleJwJq6y0snv1E6Fr/ZbYuLUTipjsqFB g0OkFx8Q5XItQGp6CLE4EP3iWC0m25Z1f+0awpTo0zd5yQ0v9Fe+7HzaZYa5WgXCCPm1 fEVSOdQf2KwXAkALI5vvK+IBkcRDlfSF3daXCSr/rviapzmEBvDBBl7o0M/v8yr/LBEl JF4SdX2K2iPdmJQ7E5Op+URsooCZIDufTZEk/M5ufxBN4Pd6Iu/radA8iaVYCuEtq6sZ 4xfHyDEXCnBQQRQIcimaBAVO3AmOVt/zd7trfqqxsXlM3Rv6IlOh5EwXdGvqqdAsolvx 2sHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wU087Bbn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h19-20020a05620a245300b006f9faedd088si42452qkn.384.2022.12.09.07.17.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 09 Dec 2022 07:17:58 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wU087Bbn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1p3f7O-0005WJ-Ke; Fri, 09 Dec 2022 10:17:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1p3f6k-00057D-U7 for qemu-devel@nongnu.org; Fri, 09 Dec 2022 10:16:23 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1p3f6h-0008Dg-Vs for qemu-devel@nongnu.org; Fri, 09 Dec 2022 10:16:14 -0500 Received: by mail-wm1-x32b.google.com with SMTP id c65-20020a1c3544000000b003cfffd00fc0so64747wma.1 for ; Fri, 09 Dec 2022 07:16:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=X94vOjJli80zkgb0fhpVEEc/w9edJfWAmH0Oey1raYk=; b=wU087BbnXdpGzdtdBGi6yc0d98iZxJgAQvhe9Wcs1oN3zGPRxLlMS65xl4HKcR6hTG F4te2IfzT3Zkdgb3h2WFAEIP5yPNI1UlDeRrNeJ06pSGJ1HTCX9hR9JTEOHKinrL7WZj uO1uGUF2Kh8yMX8DpdgVtzC1onCCHso6mLZY9ISrbtWrbs9lYvx4KCaVPw41WFucDbwi D7HtO4QEqpDlfwoSAGTBu6YRsON1VXJjahoijVid52tczfm1ckGbnEAOgn5cYVvtQSdG Ghb5tAT1uGP5egXY1VP4sgZcEnokpxW2q80P+cXgt1g85CTfS7SsNex+URmbN3Xgj6N1 vkLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=X94vOjJli80zkgb0fhpVEEc/w9edJfWAmH0Oey1raYk=; b=LJ+k9/74Tx3RH5NQZVQBfV/twEiQFgDdo13Q1uqwJaaud2do0yAnhUCopT8hdSqfMv T2Kd1D0ucd6GjN8TVtDWCN7ETc32yOKyb6TYyVoOGwjrivlbqf1XSVoBKKc+Qa2114sd N4x6ZzZY4/UKJp4xdfbMtUPgQ4eVWWMzjc1oIQp0zK5Iuk64mXOobof4KbLCNdPMzetO GHMb8ZnHuOA9rJQpXzOAF86yjLLfO+cbxQ8XpVqubY4hh8DoJR56n5nYCvbD6/Hne6o1 3yOW6ti44Swm/iQneD/m3g5vl8nn4TGzF2h8fNZ3KhRdv6FAwgqC4kxMDW9fUrXWvD73 YqKg== X-Gm-Message-State: ANoB5plE5UTBjc4zRM8yv0YcmvbB5rhjxW+Kb50pvliDs5GKu0tLZSn3 QrBgcBBESrCw2bs2AX+ccwFtef3Dymzu5H/p9sI= X-Received: by 2002:a05:600c:4451:b0:3cf:894d:1d06 with SMTP id v17-20020a05600c445100b003cf894d1d06mr5597207wmn.30.1670598970122; Fri, 09 Dec 2022 07:16:10 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id w10-20020a05600c474a00b003c701c12a17sm54144wmo.12.2022.12.09.07.16.09 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 09 Dec 2022 07:16:09 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Jiaxun Yang , Bernhard Beschow , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Thomas Huth , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH-for-8.0 7/7] hw/mips/gt64xxx_pci: Move it to hw/pci-host/ Date: Fri, 9 Dec 2022 16:15:33 +0100 Message-Id: <20221209151533.69516-8-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221209151533.69516-1-philmd@linaro.org> References: <20221209151533.69516-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé The GT-64120 is a north-bridge, and it is not MIPS specific. Move it with the other north-bridge devices. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- MAINTAINERS | 2 +- hw/mips/Kconfig | 6 ------ hw/mips/meson.build | 1 - hw/mips/trace-events | 6 ------ hw/pci-host/Kconfig | 6 ++++++ hw/{mips/gt64xxx_pci.c => pci-host/gt64120.c} | 0 hw/pci-host/meson.build | 1 + hw/pci-host/trace-events | 7 +++++++ meson.build | 1 - 9 files changed, 15 insertions(+), 15 deletions(-) delete mode 100644 hw/mips/trace-events rename hw/{mips/gt64xxx_pci.c => pci-host/gt64120.c} (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 6966490c94..e558b53e85 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1226,7 +1226,7 @@ S: Odd Fixes F: hw/isa/piix4.c F: hw/acpi/piix4.c F: hw/mips/malta.c -F: hw/mips/gt64xxx_pci.c +F: hw/pci-host/gt64120.c F: include/hw/southbridge/piix.h F: tests/avocado/linux_ssh_mips_malta.py F: tests/avocado/machine_mips_malta.py diff --git a/hw/mips/Kconfig b/hw/mips/Kconfig index 8f7bce38fb..7a55143f8a 100644 --- a/hw/mips/Kconfig +++ b/hw/mips/Kconfig @@ -60,9 +60,3 @@ config MIPS_BOSTON config FW_CFG_MIPS bool - -config GT64120 - bool - select PCI - select EMPTY_SLOT - select I8259 diff --git a/hw/mips/meson.build b/hw/mips/meson.build index 152103f15f..900613fc08 100644 --- a/hw/mips/meson.build +++ b/hw/mips/meson.build @@ -3,7 +3,6 @@ mips_ss.add(files('bootloader.c', 'mips_int.c')) mips_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c')) mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 'loongson3_virt.c')) mips_ss.add(when: 'CONFIG_MALTA', if_true: files('malta.c')) -softmmu_ss.add(when: 'CONFIG_GT64120', if_true: files('gt64xxx_pci.c')) mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c')) if 'CONFIG_TCG' in config_all diff --git a/hw/mips/trace-events b/hw/mips/trace-events deleted file mode 100644 index 13ee731a48..0000000000 --- a/hw/mips/trace-events +++ /dev/null @@ -1,6 +0,0 @@ -# gt64xxx_pci.c -gt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64 -gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64 -gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64 -gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64 -gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64 diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig index 38fd2ee8f3..a07070eddf 100644 --- a/hw/pci-host/Kconfig +++ b/hw/pci-host/Kconfig @@ -81,3 +81,9 @@ config MV64361 config DINO bool select PCI + +config GT64120 + bool + select PCI + select EMPTY_SLOT + select I8259 diff --git a/hw/mips/gt64xxx_pci.c b/hw/pci-host/gt64120.c similarity index 100% rename from hw/mips/gt64xxx_pci.c rename to hw/pci-host/gt64120.c diff --git a/hw/pci-host/meson.build b/hw/pci-host/meson.build index e832babc9d..9a813d552e 100644 --- a/hw/pci-host/meson.build +++ b/hw/pci-host/meson.build @@ -1,6 +1,7 @@ pci_ss = ss.source_set() pci_ss.add(when: 'CONFIG_PAM', if_true: files('pam.c')) pci_ss.add(when: 'CONFIG_PCI_BONITO', if_true: files('bonito.c')) +pci_ss.add(when: 'CONFIG_GT64120', if_true: files('gt64120.c')) pci_ss.add(when: 'CONFIG_PCI_EXPRESS_DESIGNWARE', if_true: files('designware.c')) pci_ss.add(when: 'CONFIG_PCI_EXPRESS_GENERIC_BRIDGE', if_true: files('gpex.c')) pci_ss.add(when: ['CONFIG_PCI_EXPRESS_GENERIC_BRIDGE', 'CONFIG_ACPI'], if_true: files('gpex-acpi.c')) diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events index 437e66ff50..9d216bb89f 100644 --- a/hw/pci-host/trace-events +++ b/hw/pci-host/trace-events @@ -6,6 +6,13 @@ bonito_spciconf_small_access(uint64_t addr, unsigned size) "PCI config address i # grackle.c grackle_set_irq(int irq_num, int level) "set_irq num %d level %d" +# gt64120.c +gt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64 +gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64 +gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64 +gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64 +gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64 + # mv64361.c mv64361_region_map(const char *name, uint64_t poffs, uint64_t size, uint64_t moffs) "Mapping %s 0x%"PRIx64"+0x%"PRIx64" @ 0x%"PRIx64 mv64361_region_enable(const char *op, int num) "Should %s region %d" diff --git a/meson.build b/meson.build index 5c6b5a1c75..bd5774f32f 100644 --- a/meson.build +++ b/meson.build @@ -2944,7 +2944,6 @@ if have_system 'hw/intc', 'hw/isa', 'hw/mem', - 'hw/mips', 'hw/misc', 'hw/misc/macio', 'hw/net',