From patchwork Wed Dec 7 00:14:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 632395 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6439FC63708 for ; Wed, 7 Dec 2022 00:15:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229810AbiLGAPI (ORCPT ); Tue, 6 Dec 2022 19:15:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229733AbiLGAPH (ORCPT ); Tue, 6 Dec 2022 19:15:07 -0500 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 747A04AF11 for ; Tue, 6 Dec 2022 16:15:06 -0800 (PST) Received: by mail-lj1-x229.google.com with SMTP id q7so19082628ljp.9 for ; Tue, 06 Dec 2022 16:15:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b0EduR0xpzdlfEb/KiEf2wXv/qnABxojAe9ELTL5B40=; b=osefMl4ALcsRfGOKfcfwyUM+wLLmj7CSDvNH/83WZeycxgwo5cN22/qo+yyZc/2gLS XqxxLoKjGoTmWVakR96MspRwpWuM8Ja5KUUULYtVZsOG6rjSdJZEstN9K5sNYmp3OCPc cRQ5xUMdlm0wJNpr059A+9ap0bSiqYTySFNELGwF9VZbfusbP2DDfrnJA+6uDQ/xitba 0rOjK9V4OaXPaFdrks+nAYtyblOVdSFNHIUoumQx5fLphJSx6KVq61eAvoWzLnTCK79o VEQoBPS8KDyb4UskUMsHOfDO4EV/xqUf5UZINf1isxgheUPoQ2yNf6XvrOCjVrGHPMxm Y6KA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b0EduR0xpzdlfEb/KiEf2wXv/qnABxojAe9ELTL5B40=; b=5pqGZSBkAZ1cHlfxlhaI/Ui02/iGpJ6agfuLj8xktZgQOrUfKNVfMiWaaVDJpdqo0i QOrWTH8VRryb61OqbhEbyyUej8vuLQ4OsRJ+EQzgJbd27ks4G6WCe8aaJLvoP7lLUo0E Rz32RjQaQ0xLVpH5lF61/S1PYvIZTmrmvQu9OfYBmq836xhvybr7e/m2Og+SqPhm5+Ka OMqv5kZEI28lgBf57XapkPuqVrOum57WyubJ4m3/ASYHGgymcC1BVnvSprLb8/c+Ky6L 7ebMBCoyiYbmFxMPIU+1PqRJhaxcpzKw7myr0L9P2iiWlj6RMEMDkTprynjD64J2vhb1 JDTg== X-Gm-Message-State: ANoB5pnAJzEBQW2S3T2TxsROnAu4C+UZyQr8067VeTEC0DxzaeTNhlpH HhkB1KYtq6aLnrGaV3NLCGiy3Mcoqp+wwW29+c15SRpV X-Google-Smtp-Source: AA0mqf4+4hOiD6FmO8fdMuw6LlbrwVoLmkgNkuzZ9UUjfb6rAk1VF0ChRZY+tL4RBk+nsqOQxrVcbg== X-Received: by 2002:a05:651c:2388:b0:279:d60:ee7f with SMTP id bk8-20020a05651c238800b002790d60ee7fmr30013099ljb.404.1670372104846; Tue, 06 Dec 2022 16:15:04 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:04 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 01/18] clk: qcom: smd-rpm: remove duplication between MMXI and MMAXI defines Date: Wed, 7 Dec 2022 02:14:46 +0200 Message-Id: <20221207001503.93790-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The commit 644c42295592 ("clk: qcom: smd: Add SM6375 clocks") added a duplicate of the existing define QCOM_SMD_RPM_MMAXI_CLK, drop it now. Fixes: 644c42295592 ("clk: qcom: smd: Add SM6375 clocks") Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 4 ++-- include/linux/soc/qcom/smd-rpm.h | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index fea505876855..4947d5eab591 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -1120,8 +1120,8 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { }; /* SM6375 */ -DEFINE_CLK_SMD_RPM(sm6375, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMXI_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6375, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMXI_CLK, 1); +DEFINE_CLK_SMD_RPM(sm6375, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6375, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 1); DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0); DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0); DEFINE_CLK_SMD_RPM_BRANCH(sm6375, bimc_freq_log, bimc_freq_log_a, QCOM_SMD_RPM_MISC_CLK, 4, 1); diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h index 3ab8c07f71c0..82c9d489833a 100644 --- a/include/linux/soc/qcom/smd-rpm.h +++ b/include/linux/soc/qcom/smd-rpm.h @@ -41,7 +41,6 @@ struct qcom_smd_rpm; #define QCOM_SMD_RPM_HWKM_CLK 0x6d6b7768 #define QCOM_SMD_RPM_PKA_CLK 0x616b70 #define QCOM_SMD_RPM_MCFG_CLK 0x6766636d -#define QCOM_SMD_RPM_MMXI_CLK 0x69786d6d int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm, int state, From patchwork Wed Dec 7 00:14:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 632394 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86DD9C6370A for ; Wed, 7 Dec 2022 00:15:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229733AbiLGAPJ (ORCPT ); Tue, 6 Dec 2022 19:15:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229627AbiLGAPI (ORCPT ); Tue, 6 Dec 2022 19:15:08 -0500 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 618674B990 for ; Tue, 6 Dec 2022 16:15:07 -0800 (PST) Received: by mail-lj1-x22d.google.com with SMTP id l8so19067988ljh.13 for ; Tue, 06 Dec 2022 16:15:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OOcXBHzPaQhy0fwsmnckvcizCAWhntI4mIBoXMhytOw=; b=WpDsur3btGOj4DHDNyCmFOhUeUMKvdUHEm6q6KNw31cCREY2lXkepPe8t7ofDBi/Vs shACs6lAM0aTg8kj/6mS7GoZay30LQPhfGfx+VfoC/YoiSiIZi0q5nbAh1OCiMvNGX0y H1VqZyhv/WqQF4Zj1Hq/b6hiaGSYHHnKG13lQZMBkQxLIhRk8LCA62QIXD0XI/RjPOkJ DYJAbkm0V4VkS+nITMZEBT2yX5sNcbz9LvWeWKe4WgGFHmFZFzHQmoBv76X+406vw1rL WtxNMRpNn9T/q3g+QufBAg8kGwQhGFC/hslcDHSlTS1rlPWwanMbC/7tl/yLcCDXqb1r Ulnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OOcXBHzPaQhy0fwsmnckvcizCAWhntI4mIBoXMhytOw=; b=ehgnu3/CS89XZwK1ZTxj3mHpfhTZJRq9wfI+Q0Rp39s9UJ2yUh2XjoYGSIFvk6KSef iQwNWfCagzUZ46i9fhQx1dzV+loOxCZ2DktdFI7ZHJstgvfL0cMbvlIpAw5iRRd8r50/ VlhGTYyzcGfHldT++lC6EQt0lMQeqJQkWPvt2wCAJpmwbVucXi2301hLFepJDRLzjhSi K2FT3/Wzq8vvo+j7KAjqYF5BRIsHCxkEayh7giVDdoNSL6+1VvP53YojoXCANT875LFp /QA/i0K5bIS/mNrJ65JA9uc0ShQWQZY3GalTSjJIm1jGASJxxMcyxIqhN4vkk2IDzhLu 9Hxw== X-Gm-Message-State: ANoB5plseBx3ooFM791uystvVjZKm/q/j4itW/+SpOccgkzxVwIXNY6Z J2MCEoN6ByxZ2z9aIMV9QhM+UqgS/KGWCZ0CB6/iHsY/ X-Google-Smtp-Source: AA0mqf5JCCvehDiSp88ITyyaEadczHeySAJXPQ7sLnSsu/r6QGsuGVxUjSfh9z8aq2hhYLCguPisAw== X-Received: by 2002:a2e:9b4b:0:b0:27a:b66:aa7b with SMTP id o11-20020a2e9b4b000000b0027a0b66aa7bmr2011746ljj.246.1670372105760; Tue, 06 Dec 2022 16:15:05 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:05 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 02/18] clk: qcom: smd-rpm: enable pin-controlled ln_bb_clk clocks on qcs404 Date: Wed, 7 Dec 2022 02:14:47 +0200 Message-Id: <20221207001503.93790-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The commit eaeee28db289 ("clk: qcom: smd: Add support for QCS404 rpm clocks") defined the pin-controlled ln_bb_clk clocks, but didn't add them to the qcs404_clks array. Add them to make these clocks usable to platform devices. Fixes: eaeee28db289 ("clk: qcom: smd: Add support for QCS404 rpm clocks") Reviewed-by: Alex Elder Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 2 ++ include/dt-bindings/clock/qcom,rpmcc.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 4947d5eab591..ccc54913eca5 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -843,6 +843,8 @@ static struct clk_smd_rpm *qcs404_clks[] = { [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk, [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, + [RPM_SMD_LN_BB_CLK_PIN] = &qcs404_ln_bb_clk_pin, + [RPM_SMD_LN_BB_A_CLK_PIN] = &qcs404_ln_bb_clk_a_pin, }; static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index c0ad624e930e..46309c9953b2 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -168,5 +168,7 @@ #define RPM_SMD_MSS_CFG_AHB_CLK 122 #define RPM_SMD_MSS_CFG_AHB_A_CLK 123 #define RPM_SMD_BIMC_FREQ_LOG 124 +#define RPM_SMD_LN_BB_CLK_PIN 125 +#define RPM_SMD_LN_BB_A_CLK_PIN 126 #endif From patchwork Wed Dec 7 00:14:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 631626 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2C98C63709 for ; Wed, 7 Dec 2022 00:15:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229627AbiLGAPK (ORCPT ); Tue, 6 Dec 2022 19:15:10 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229812AbiLGAPI (ORCPT ); Tue, 6 Dec 2022 19:15:08 -0500 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E7714AF11 for ; Tue, 6 Dec 2022 16:15:08 -0800 (PST) Received: by mail-lf1-x12f.google.com with SMTP id bp15so26171314lfb.13 for ; Tue, 06 Dec 2022 16:15:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xVwPaQWXDnANQ48vXa4DWtI+NXMXKWbnMhAHV1xHXeo=; b=Yei/59De/qKL8IocMhOskbLNJlIvb0Ll8NC/hH13n6zu2cgtUCLuxA5ZVQKzuB6Hy6 HA2/YMVB0V3LZeHJeXrQl7iwbWahm0FEeUbhgpWSsQbMAGYnhPnNSq8zVTXLte4D73sD pQYkWY5be1wk4hi7TQB9t0XhSvzLCI6PHAFVBRdwOjylZlMKpHErRja97ukwOPielS8W sNhfSEX1HN1VMlV9F0hozICoD82mSTP+B0BpSnsbQ6IWqrb735F1fy0WOhHdMT0y7RKI 58A/Lg5ei+2xkKSZ4gxKMocOxes/c6BA6EEYKh8mXb+OBwYX5zCYZwKSJFWcFNO6cHF7 rGDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xVwPaQWXDnANQ48vXa4DWtI+NXMXKWbnMhAHV1xHXeo=; b=IWlTc0b8YFgtjJpVeyiCI9j2e35ZWml1px2Y97VuALw6Dk98wqzJxJwuK1Ntk72SXo aoPPmGEESYkLI73EFdT/iQIs2kJvAcXMlTzsAMtzpFByPRKhj5pZ+3wz8lI/isZgvtG7 WBdc3sSzLFvMGYB+4frt67KCdkLKAHJLcRteZFf9PgNZXAm12znKeQRG9aKEdzAOuD8E XhL0WC9RjUu2BWSPoPA5SR/v+HGXDO18RXHhl1Pisd5a5MgiDTZ3fuisdF04ZL5/eMk5 eEYC8Ia51a6UBAx36vo5sC6tLY+ws2Pxnms5ksCuohdcFOxlKOZPhnCON2pO0gk25X6d ECtg== X-Gm-Message-State: ANoB5pmeaPzTlMHh152esZcD07zC8yy/ZITMliIlGCpDSY1WD+IKGpON 2Fm4S7XqKQ65BYS9HVzFTljoxg== X-Google-Smtp-Source: AA0mqf4PFPjrJJTV2hXBHAl8CCrzlXyEgG2lm3ksBfOZqki5/Qs/18NDQH5Yoj3nvpmhtOJpQrXeTA== X-Received: by 2002:ac2:5f57:0:b0:4b5:8f72:d0f5 with SMTP id 23-20020ac25f57000000b004b58f72d0f5mr776473lfz.590.1670372106478; Tue, 06 Dec 2022 16:15:06 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:06 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 03/18] clk: qcom: smd-rpm: remove duplication between qcs404 and qcm2290 clocks Date: Wed, 7 Dec 2022 02:14:48 +0200 Message-Id: <20221207001503.93790-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Reuse qcs404's QPIC and BIMC_GPU clock for qcm2290. Fixes: 78b727d02815 ("clk: qcom: smd-rpm: Add QCM2290 RPM clock support") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Alex Elder --- drivers/clk/qcom/clk-smd-rpm.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index ccc54913eca5..31ef6345ff01 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -1168,11 +1168,8 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6375 = { DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, ln_bb_clk2, ln_bb_clk2_a, 0x2, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, rf_clk3_a, 6, 38400000); -DEFINE_CLK_SMD_RPM(qcm2290, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc_clk, cpuss_gnoc_a_clk, QCOM_SMD_RPM_MEM_CLK, 1); -DEFINE_CLK_SMD_RPM(qcm2290, bimc_gpu_clk, bimc_gpu_a_clk, - QCOM_SMD_RPM_MEM_CLK, 2); static struct clk_smd_rpm *qcm2290_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, @@ -1203,14 +1200,14 @@ static struct clk_smd_rpm *qcm2290_clks[] = { [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk, [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, - [RPM_SMD_QPIC_CLK] = &qcm2290_qpic_clk, - [RPM_SMD_QPIC_CLK_A] = &qcm2290_qpic_a_clk, + [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, + [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk, [RPM_SMD_HWKM_CLK] = &qcm2290_hwkm_clk, [RPM_SMD_HWKM_A_CLK] = &qcm2290_hwkm_a_clk, [RPM_SMD_PKA_CLK] = &qcm2290_pka_clk, [RPM_SMD_PKA_A_CLK] = &qcm2290_pka_a_clk, - [RPM_SMD_BIMC_GPU_CLK] = &qcm2290_bimc_gpu_clk, - [RPM_SMD_BIMC_GPU_A_CLK] = &qcm2290_bimc_gpu_a_clk, + [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk, + [RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk, [RPM_SMD_CPUSS_GNOC_CLK] = &qcm2290_cpuss_gnoc_clk, [RPM_SMD_CPUSS_GNOC_A_CLK] = &qcm2290_cpuss_gnoc_a_clk, }; From patchwork Wed Dec 7 00:14:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 631625 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02BA7C63708 for ; Wed, 7 Dec 2022 00:15:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229838AbiLGAPV (ORCPT ); Tue, 6 Dec 2022 19:15:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229728AbiLGAPK (ORCPT ); Tue, 6 Dec 2022 19:15:10 -0500 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D12D64B990 for ; Tue, 6 Dec 2022 16:15:08 -0800 (PST) Received: by mail-lj1-x22c.google.com with SMTP id f20so5919878lja.4 for ; Tue, 06 Dec 2022 16:15:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=83kG0jem/GFCi8sc/x0OqHU2E6B9xurjcMPcz8cdK+8=; b=O/OG2d2/ZOKcFk5Ypxg+oODFbp8nh7YP205kkzajCXpm+xfpOLoZcRf3MDNwM6Ga21 dd7l0g5Y7fjheFXesE3P47jD23O8bRsruocTqXESi9qF/Fz7XNO1FVho9Abq6T3DzdW8 OLrrueGUpbi3iPXz3hZrVQsaHff9Q22bIMrlK8WLcxJ1juDsNaKNsjg8E3CusH47OsyG 0z1mRLCCKxfdSPGOWQ5GUN0zDMqGH1x8z3I712Spv6zSjCnqco3ON0LyHXKfd64bhc6R R5aRpX3VSIy2rNjpEOgpprCraBmJYwGVQ1R2lv5q7TaWyFjjKa7i5YwWBI/heiRiRjKL oeSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=83kG0jem/GFCi8sc/x0OqHU2E6B9xurjcMPcz8cdK+8=; b=jCdkY7xQfB8cFwhhITaSDkRkwueYcsxyaaISCZnHps5zs9WAVLFLxmYRA1628Mm7IZ GQtx/rtKesU50FZrvqgmmUz+kgUu5G9Iy5V0V7GZ2iHBQ4HpXhw67LpEXQc6aqSCc6DF oItPbBPbgCZMCO9xUaIJkK0c96UDu/ZcqCVJ+BWkZm9Y8wvhsjps/G5NwfQvsbJNLzzJ korj6WzxTTM6Y1U0DLdDfK7fB2JW4HQRSfsit/cHcJs9DhRFtgGM8ambkVq1GlTYCKza lB5jcb+P5nA85M2e0Bwx5tzrE6u+gCQQt3BquvR0aKZljD6p4wOGGnkKPRQUVRouKoJ0 7Nzw== X-Gm-Message-State: ANoB5pm0Jy18ZYO0NkcT93OA26uXQmDuYB1t2HsWczRSQx0duh4fWijs mqJZVOE6yTKrAgLPnU4e/ZhC7g== X-Google-Smtp-Source: AA0mqf5n9B1weATYE4Gw6jHgpv7bLPVNmXdzpwf4mHKkt7N+Gg1flvSpjKgVFIHQ5tZm28P3gRZFjQ== X-Received: by 2002:a2e:5cc:0:b0:279:f969:8b1 with SMTP id 195-20020a2e05cc000000b00279f96908b1mr3804520ljf.43.1670372107157; Tue, 06 Dec 2022 16:15:07 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:06 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 04/18] clk: qcom: smd-rpm: add missing ln_bb_clkN clocks Date: Wed, 7 Dec 2022 02:14:49 +0200 Message-Id: <20221207001503.93790-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Newer platforms (msm8998, sdm660, sm6125) have low noise LN_BB_CLKn clocks. The driver already uses proper clock indices (RPM_SMD_LN_BB_CLKn). Fix clock names used by these platforms. Fixes: a0384ecfe2aa ("clk: qcom: smd-rpm: De-duplicate identical entries") Fixes: edeb2ca74716 ("clk: qcom: smd: Add support for SM6125 rpm clocks") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 44 ++++++++++++++++++---------------- 1 file changed, 24 insertions(+), 20 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 31ef6345ff01..a0bf58785921 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -852,6 +852,10 @@ static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { .num_clks = ARRAY_SIZE(qcs404_clks), }; +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk1, ln_bb_clk1_a, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk1_pin, ln_bb_clk1_a_pin, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk2, ln_bb_clk2_a, 2, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk2_pin, ln_bb_clk2_a_pin, 2, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin, 3, 19200000); DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk, @@ -882,16 +886,16 @@ static struct clk_smd_rpm *msm8998_clks[] = { [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, - [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1, - [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a, - [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2, - [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a, + [RPM_SMD_LN_BB_CLK1] = &msm8998_ln_bb_clk1, + [RPM_SMD_LN_BB_CLK1_A] = &msm8998_ln_bb_clk1_a, + [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2, + [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a, [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3, [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a, - [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, - [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, - [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, - [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, + [RPM_SMD_LN_BB_CLK1_PIN] = &msm8998_ln_bb_clk1_pin, + [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8998_ln_bb_clk1_a_pin, + [RPM_SMD_LN_BB_CLK2_PIN] = &msm8998_ln_bb_clk2_pin, + [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8998_ln_bb_clk2_a_pin, [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin, [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin, [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, @@ -946,18 +950,18 @@ static struct clk_smd_rpm *sdm660_clks[] = { [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, - [RPM_SMD_LN_BB_CLK] = &msm8916_bb_clk1, - [RPM_SMD_LN_BB_A_CLK] = &msm8916_bb_clk1_a, - [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2, - [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a, + [RPM_SMD_LN_BB_CLK] = &msm8998_ln_bb_clk1, + [RPM_SMD_LN_BB_A_CLK] = &msm8998_ln_bb_clk1_a, + [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2, + [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a, [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3, [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a, [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, - [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, - [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, - [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, - [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, + [RPM_SMD_LN_BB_CLK1_PIN] = &msm8998_ln_bb_clk1_pin, + [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8998_ln_bb_clk1_a_pin, + [RPM_SMD_LN_BB_CLK2_PIN] = &msm8998_ln_bb_clk2_pin, + [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8998_ln_bb_clk2_a_pin, [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin, [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin, }; @@ -1057,10 +1061,10 @@ static struct clk_smd_rpm *sm6125_clks[] = { [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, - [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1, - [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a, - [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2, - [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a, + [RPM_SMD_LN_BB_CLK1] = &msm8998_ln_bb_clk1, + [RPM_SMD_LN_BB_CLK1_A] = &msm8998_ln_bb_clk1_a, + [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2, + [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a, [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3, [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a, [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, From patchwork Wed Dec 7 00:14:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 632393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 112D9C3A5A7 for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:07 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 05/18] clk: qcom: smd-rpm: use msm8998_ln_bb_clk2 for qcm2290 SoC Date: Wed, 7 Dec 2022 02:14:50 +0200 Message-Id: <20221207001503.93790-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The qcm2290's ln_bb_clk2 is identical to the freshly added msm8998's ln_bb_clk2 one. Use the latter and drop the SoC-specific version. Reviewed-by: Alex Elder Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index a0bf58785921..7dffc30ddb61 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -1169,7 +1169,6 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6375 = { }; /* QCM2290 */ -DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, ln_bb_clk2, ln_bb_clk2_a, 0x2, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, rf_clk3_a, 6, 38400000); DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc_clk, cpuss_gnoc_a_clk, @@ -1184,8 +1183,8 @@ static struct clk_smd_rpm *qcm2290_clks[] = { [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk, - [RPM_SMD_LN_BB_CLK2] = &qcm2290_ln_bb_clk2, - [RPM_SMD_LN_BB_CLK2_A] = &qcm2290_ln_bb_clk2_a, + [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2, + [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a, [RPM_SMD_RF_CLK3] = &qcm2290_rf_clk3, [RPM_SMD_RF_CLK3_A] = &qcm2290_rf_clk3_a, [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk, From patchwork Wed Dec 7 00:14:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 631624 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3337C4708D for ; Wed, 7 Dec 2022 00:15:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229816AbiLGAPX (ORCPT ); Tue, 6 Dec 2022 19:15:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60326 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229821AbiLGAPU (ORCPT ); Tue, 6 Dec 2022 19:15:20 -0500 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47E634B9A4 for ; Tue, 6 Dec 2022 16:15:10 -0800 (PST) Received: by mail-lf1-x136.google.com with SMTP id y25so4014712lfa.9 for ; Tue, 06 Dec 2022 16:15:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jxHaJIeXQQoSGc51uH5qJc+u0gp2HhUHkG2li9+efwg=; b=yO4MSr1QT+5RgDmAHZLi7e37K4YnKME6s25JuBbbkiFmnQvTiMBoSh6fG7eHf+LJnY Dfqh3lHTQK7SU4BL+bgpJNmn3hPY3G8m0d8pIXwdwXHQUgADBRQJKm5fOAXsotdHQGjP 9Pqd+6M3O2bELq6F03u0Nh7jevziyV3CGdpNg/W3rheNdEjDabb+4vTY7vBno0SXMu4f dDEYgOQ2KRjatijDQ4/wbYNHiA7622+cjdZlTru++ZGZzEgsAc0pFid7YfF1r8R6gh24 Y74zI9ld0NDq5LBo0Q+Ul0437rour5AnD2qgaGla91Y4nxL5U23teuq8LDH2FG8CIEvE tB1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jxHaJIeXQQoSGc51uH5qJc+u0gp2HhUHkG2li9+efwg=; b=YkjnGSz38e/SC6i2a8RmYFBKwUEXub9Zu/BFIcqlzF7Ukya9WAV0kDxYSunfRcIFlk DLFJ8ykBpitFS7ZnVNaN48Yo21d37HFKstUooTl7pQD9a35zmZZmqFdN6l7BihAxL0wJ gE/Zma4jP3Ve7j+f1fRfpefu3qsWZ2SLNewgkzN37uckiurETsKR6k2oRKzBb5op8yQN YUipriDZ7hhn01E8C16x8R7Cjp3bZ3mRUm2PJMOzTUzfAeRMDXQaMt8W05pTyE2FuQef vzx/oJOGCE+L5KanUTuIv4EtHzoIBfoijBRW0pztT4AlvmsfpvtrHIeNVzcwP8Hhqlcv IqZA== X-Gm-Message-State: ANoB5pk9Xpd1JWRQgAhqgaQWnv1Q7JAsk8SclhN+bOMXBHGQtg7KszDH AK4mxjcBdbtNddtCvQCmhxNLjw== X-Google-Smtp-Source: AA0mqf4XQrWMVvVl7tzoYVCLGZb2dl0mNPCIHD9NXrmLHzQLCQqP3pbFapO+L+k/nsVdwvgQXITARQ== X-Received: by 2002:a05:6512:3b13:b0:4b0:efed:e3a5 with SMTP id f19-20020a0565123b1300b004b0efede3a5mr32449636lfv.75.1670372108657; Tue, 06 Dec 2022 16:15:08 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:08 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 06/18] clk: qcom: smd-rpm: rename msm8992_ln_bb_* clocks to qcs404_ln_bb_* Date: Wed, 7 Dec 2022 02:14:51 +0200 Message-Id: <20221207001503.93790-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org For each of XO_BUFFER_PINCTRL clocks there is a corresponding XO_BUFFER clock with the similar name (e.g. msm8998_ln_bb_clk3_pin vs msm8998_ln_bb_clk3). For qcs404_ln_bb_clk_pin there is no qcs404_ln_bb_clk, since the msm8992_ln_bb_clk was used instead (even for qcs404 platform). Follow the usual practice and rename msm8992_ln_bb_clk clocks to qcs404_ln_bb_clk (and rename active-only clock in a similar way). This is a preparation step for the next patch, which will merge XO_BUFFER and XO_BUFFER_PINCTRL definitions. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Alex Elder --- drivers/clk/qcom/clk-smd-rpm.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 7dffc30ddb61..add92ecd513d 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -635,7 +635,8 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { }; DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, ln_bb_clk, ln_bb_clk_a, 8, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8, 19200000); DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1); @@ -673,8 +674,8 @@ static struct clk_smd_rpm *msm8992_clks[] = { [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, - [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk, - [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, + [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, + [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_clk_a, [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk, @@ -733,8 +734,8 @@ static struct clk_smd_rpm *msm8994_clks[] = { [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, - [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk, - [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, + [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, + [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_clk_a, [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk, @@ -798,8 +799,8 @@ static struct clk_smd_rpm *msm8996_clks[] = { [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk, - [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, + [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, + [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_clk_a, [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, @@ -822,7 +823,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { }; DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8, 19200000); static struct clk_smd_rpm *qcs404_clks[] = { [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, @@ -841,8 +841,8 @@ static struct clk_smd_rpm *qcs404_clks[] = { [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, - [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk, - [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk, + [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, + [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_clk_a, [RPM_SMD_LN_BB_CLK_PIN] = &qcs404_ln_bb_clk_pin, [RPM_SMD_LN_BB_A_CLK_PIN] = &qcs404_ln_bb_clk_a_pin, }; @@ -1014,8 +1014,8 @@ static struct clk_smd_rpm *msm8953_clks[] = { [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_RF_CLK3] = &msm8992_ln_bb_clk, - [RPM_SMD_RF_CLK3_A] = &msm8992_ln_bb_a_clk, + [RPM_SMD_RF_CLK3] = &qcs404_ln_bb_clk, + [RPM_SMD_RF_CLK3_A] = &qcs404_ln_bb_clk_a, [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, From patchwork Wed Dec 7 00:14:52 2022 Content-Type: text/plain; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:08 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 07/18] clk: qcom: smd-rpm: remove duplication between sm6375 and sm6125 clocks Date: Wed, 7 Dec 2022 02:14:52 +0200 Message-Id: <20221207001503.93790-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Reuse sm6125's MMAXI clocks for sm6375. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index add92ecd513d..024665438b62 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -1126,8 +1126,6 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { }; /* SM6375 */ -DEFINE_CLK_SMD_RPM(sm6375, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6375, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 1); DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0); DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0); DEFINE_CLK_SMD_RPM_BRANCH(sm6375, bimc_freq_log, bimc_freq_log_a, QCOM_SMD_RPM_MISC_CLK, 4, 1); @@ -1146,10 +1144,10 @@ static struct clk_smd_rpm *sm6375_clks[] = { [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk, - [RPM_SMD_MMRT_CLK] = &sm6375_mmrt_clk, - [RPM_SMD_MMRT_A_CLK] = &sm6375_mmrt_a_clk, - [RPM_SMD_MMNRT_CLK] = &sm6375_mmnrt_clk, - [RPM_SMD_MMNRT_A_CLK] = &sm6375_mmnrt_a_clk, + [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk, + [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, + [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, + [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk, [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk, [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk, From patchwork Wed Dec 7 00:14:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 631623 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 791DEC352A1 for ; Wed, 7 Dec 2022 00:15:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229891AbiLGAP0 (ORCPT ); Tue, 6 Dec 2022 19:15:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229828AbiLGAPU (ORCPT ); Tue, 6 Dec 2022 19:15:20 -0500 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ACF2C4B9AA for ; Tue, 6 Dec 2022 16:15:11 -0800 (PST) Received: by mail-lj1-x232.google.com with SMTP id x6so19092754lji.10 for ; Tue, 06 Dec 2022 16:15:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5mk6Xk2qoGgC+MIBTq/7jSBPxUXyxRi1BegT2NWitd8=; b=jx3hO6dYaD9KdoOL85iM6lZJflwQzfcWRCJWEtOa24yEQNuwDxMddtqpMWFVhDIkSS quDS9dMtXfqfEjrE9tZYVmNrS5gCq1TxfT0wO+fplzT4imGZZu8wm3b1A0gBKu7wgUQB mJQQnP3d3qP9crZsfzKr7sEVbw3q5SDrfd001Cy/rt0JD1FTEg6Dc3ivCNtD0LJ2Su/i 6y2ujoQp2JHe/8/7q9tRo0YRYSljZOXgPnWsea7DSUTBlbDq0QaGsCTUBJAgPz1KVQy7 dbZB6N8T0Ue75ldxJOU0JWnsQkbjhKeII3Li1p7NYHNikuII8r7OStyl2pgY1T26+rWs 0aKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5mk6Xk2qoGgC+MIBTq/7jSBPxUXyxRi1BegT2NWitd8=; b=aW3ESgni6Je2b0gia4x3jUFOb1Ntp5yvFKYKyuf1U5HPl+5NdrLSkNuGKSBik79Ujt brBs2BcViuWTQQg7rfN1JNV8N4IsHgOVJimp5SKIInAHStdyQ33CYooglvg+LWXXc1ZR 5SxQiTlqEK81DI3ON3agtO9CSCVXQ/GhYYNFz2CzBkrJwA4TwPEm9tXnYpHhoSKt2YoN uVP+KECKtEab+QznINON25EA9pPvUeAqYuybvaCbvnvBK5KzQuTgrjLOAYOdkzAszcrZ XyPeA1shncE2YP/5GoSZFr6o7POojA+K9X05yvMpKPQbUPM++SbNHUeSRFmw5QJq5Iqm huZQ== X-Gm-Message-State: ANoB5pmIbmnovXLE+8dJKvW2Z0AFfjkiauvEvfZkLRMcNqwLxytG73Za IQUR90CPSQhM4bK8XRt+HlWhTw== X-Google-Smtp-Source: AA0mqf4eEtjYmxd17omNapWuRZSahlpYX7yQXvmcFIK0IGvBxxA76J8fmNJbLDlLoyJRDl881k/cug== X-Received: by 2002:a2e:8085:0:b0:279:d45f:cebb with SMTP id i5-20020a2e8085000000b00279d45fcebbmr7631938ljg.525.1670372110062; Tue, 06 Dec 2022 16:15:10 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:09 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 08/18] clk: qcom: smd-rpm: add XO_BUFFER clock for each XO_BUFFER_PINCTRL clock Date: Wed, 7 Dec 2022 02:14:53 +0200 Message-Id: <20221207001503.93790-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org For each XO_BUFFER_PINCTRL there is a corresponding XO_BUFFER clock. Add them automatically to drop the duplication between the clock definitions. Reviewed-by: Alex Elder Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 47 +++++++++++++--------------------- 1 file changed, 18 insertions(+), 29 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 024665438b62..f9d8382cd274 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -124,7 +124,10 @@ #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, \ r_id, r) \ - __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \ + DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, \ + r_id, r); \ + __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name##_pin, \ + _active##_pin, \ QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, r, \ QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY) @@ -419,14 +422,10 @@ DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a, 4, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a, 5, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin, 1, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1, bb_clk1_a, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2, bb_clk2_a, 2, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1, rf_clk1_a, 4, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2, rf_clk2_a, 5, 19200000); static struct clk_smd_rpm *msm8909_clks[] = { [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, @@ -534,19 +533,14 @@ DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3); DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1); DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d0, cxo_d0_a, 1, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d1, cxo_d1_a, 2, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a0, cxo_a0_a, 4, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a1, cxo_a1_a, 5, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a2, cxo_a2_a, 6, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk, 7, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1, 11, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2, 12, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0_pin, cxo_d0_a_pin, 1, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1_pin, cxo_d1_a_pin, 2, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0_pin, cxo_a0_a_pin, 4, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin, 5, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin, 6, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0, cxo_d0_a, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1, cxo_d1_a, 2, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0, cxo_a0_a, 4, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1, cxo_a1_a, 5, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2, cxo_a2_a, 6, 19200000); static struct clk_smd_rpm *msm8974_clks[] = { [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, @@ -635,8 +629,7 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { }; DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(qcs404, ln_bb_clk, ln_bb_clk_a, 8, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk, ln_bb_clk_a, 8, 19200000); DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1); @@ -852,18 +845,14 @@ static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { .num_clks = ARRAY_SIZE(qcs404_clks), }; -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk1, ln_bb_clk1_a, 1, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk1_pin, ln_bb_clk1_a_pin, 1, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk2, ln_bb_clk2_a, 2, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk2_pin, ln_bb_clk2_a_pin, 2, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin, 3, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk1, ln_bb_clk1_a, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk2, ln_bb_clk2_a, 2, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000); DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 1); DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 2); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3, rf_clk3_a, 6, 19200000); static struct clk_smd_rpm *msm8998_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, From patchwork Wed Dec 7 00:14:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 632391 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74A80C63707 for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:10 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 09/18] clk: qcom: smd-rpm: drop the rpm_status_id field Date: Wed, 7 Dec 2022 02:14:54 +0200 Message-Id: <20221207001503.93790-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The rpm_status_id field is a leftover from the non-SMD clocks. It is of no use for the SMD-RPM clock driver and is always equal to zero. Drop it completely. Reviewed-by: Konrad Dybcio Reviewed-by: Alex Elder Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index f9d8382cd274..2075cfd34f99 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -25,13 +25,11 @@ #define QCOM_RPM_SMD_KEY_STATE 0x54415453 #define QCOM_RPM_SCALING_ENABLE_ID 0x2 -#define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id, \ - key) \ +#define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, key) \ static struct clk_smd_rpm _platform##_##_active; \ static struct clk_smd_rpm _platform##_##_name = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ - .rpm_status_id = (stat_id), \ .rpm_key = (key), \ .peer = &_platform##_##_active, \ .rate = INT_MAX, \ @@ -48,7 +46,6 @@ static struct clk_smd_rpm _platform##_##_active = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ - .rpm_status_id = (stat_id), \ .active_only = true, \ .rpm_key = (key), \ .peer = &_platform##_##_name, \ @@ -65,12 +62,11 @@ } #define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, \ - stat_id, r, key) \ + r, key) \ static struct clk_smd_rpm _platform##_##_active; \ static struct clk_smd_rpm _platform##_##_name = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ - .rpm_status_id = (stat_id), \ .rpm_key = (key), \ .branch = true, \ .peer = &_platform##_##_active, \ @@ -88,7 +84,6 @@ static struct clk_smd_rpm _platform##_##_active = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ - .rpm_status_id = (stat_id), \ .active_only = true, \ .rpm_key = (key), \ .branch = true, \ @@ -107,19 +102,19 @@ #define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id) \ __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \ - 0, QCOM_RPM_SMD_KEY_RATE) + QCOM_RPM_SMD_KEY_RATE) #define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r) \ __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, \ - r_id, 0, r, QCOM_RPM_SMD_KEY_ENABLE) + r_id, r, QCOM_RPM_SMD_KEY_ENABLE) #define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id) \ __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \ - 0, QCOM_RPM_SMD_KEY_STATE) + QCOM_RPM_SMD_KEY_STATE) #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id, r) \ __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \ - QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, r, \ + QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ QCOM_RPM_KEY_SOFTWARE_ENABLE) #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, \ @@ -128,7 +123,7 @@ r_id, r); \ __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name##_pin, \ _active##_pin, \ - QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, r, \ + QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY) #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw) @@ -137,7 +132,6 @@ struct clk_smd_rpm { const int rpm_res_type; const int rpm_key; const int rpm_clk_id; - const int rpm_status_id; const bool active_only; bool enabled; bool branch; From patchwork Wed Dec 7 00:14:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 632390 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC260C63709 for ; Wed, 7 Dec 2022 00:15:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229815AbiLGAP0 (ORCPT ); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:11 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 10/18] clk: qcom: smd-rpm: fix alignment of line breaking backslashes Date: Wed, 7 Dec 2022 02:14:55 +0200 Message-Id: <20221207001503.93790-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The commit 52a436e0b7fe ("clk: qcom: smd-rpm: Switch to parent_data") introduced ragged right alignment for the line breaking backslash. Fix it to make the code look consistently. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 2075cfd34f99..7e43ecdda763 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -36,10 +36,10 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_ops, \ .name = #_name, \ - .parent_data = &(const struct clk_parent_data){ \ - .fw_name = "xo", \ - .name = "xo_board", \ - }, \ + .parent_data = &(const struct clk_parent_data){ \ + .fw_name = "xo", \ + .name = "xo_board", \ + }, \ .num_parents = 1, \ }, \ }; \ @@ -53,10 +53,10 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_ops, \ .name = #_active, \ - .parent_data = &(const struct clk_parent_data){ \ - .fw_name = "xo", \ - .name = "xo_board", \ - }, \ + .parent_data = &(const struct clk_parent_data){ \ + .fw_name = "xo", \ + .name = "xo_board", \ + }, \ .num_parents = 1, \ }, \ } @@ -74,10 +74,10 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_branch_ops, \ .name = #_name, \ - .parent_data = &(const struct clk_parent_data){ \ - .fw_name = "xo", \ - .name = "xo_board", \ - }, \ + .parent_data = &(const struct clk_parent_data){ \ + .fw_name = "xo", \ + .name = "xo_board", \ + }, \ .num_parents = 1, \ }, \ }; \ @@ -92,10 +92,10 @@ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_branch_ops, \ .name = #_active, \ - .parent_data = &(const struct clk_parent_data){ \ - .fw_name = "xo", \ - .name = "xo_board", \ - }, \ + .parent_data = &(const struct clk_parent_data){ \ + .fw_name = "xo", \ + .name = "xo_board", \ + }, \ .num_parents = 1, \ }, \ } From patchwork Wed Dec 7 00:14:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 631621 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28E49C63706 for ; Wed, 7 Dec 2022 00:15:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229640AbiLGAP3 (ORCPT ); Tue, 6 Dec 2022 19:15:29 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229844AbiLGAPW (ORCPT ); Tue, 6 Dec 2022 19:15:22 -0500 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0042A4D5C2 for ; Tue, 6 Dec 2022 16:15:13 -0800 (PST) Received: by mail-lj1-x236.google.com with SMTP id bn5so19130952ljb.2 for ; Tue, 06 Dec 2022 16:15:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FGzQyhdenSwcHEboe3rA+QyA3pqYTdrZAd8HXwWyub4=; b=pVKqUaR+C5mumvDtp0Zci8ZU0vZtoK1/4WOfX1NtkAWqzVad3vGRFIZlMdk8WmkcI/ esQTs5ZaRxe+EYnOtCJcHA29TVESRGCfBe15hmzQrCZyqsUIu9hKErgwyz3DoNF/ZIEi fN8f7X6mu4xpg6K1ZFzpCTquQ72r7scwuQEQe1lR3UoqJHXYqEjR8xmAxN2maaUTTfoY 3HTpv+j+N7GZAgQO1KwWrGopjXIcPuCclyRCpcFrF0V7/6v3/1G9aSytAXPzUeAK1MF+ F7jIyS46Z99s0A+LQhs/FiuDgL5BD/Fbe67GZ9x7yXZ1gqw/0ylRdDNz+PiFFa3WUdGg KJig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FGzQyhdenSwcHEboe3rA+QyA3pqYTdrZAd8HXwWyub4=; b=s71E68wSeNYEliLvxKrzgG/wTnP7eMW3vv7Mh1ewFYg9kmUbrcdsTEzQsbZcQ1pnSq WdOusQt92LnU/ymKuSEL+lmPG8LTcYJu8apdpnOkuVNVg5KlGy3JGDCpNdFkOvBP+iXN KzvzD5N9LTNwYPRx1IRkUSvg3yxEQ/oHGwO3FPDK+LMwZp7ZSE7z03iklAd/mkB0PQDG nuNlyMild6UaxrQjv0nfvEhxFdyR9VNIp45hPibsjuJzfJslmsfw6RN9W2G2OfJoHf4h uGjk3glRFTtupfXXP7Hg6amhZSCUp9dUjtFzGZ/Cv/88zMK0/IMxk31thUzjNOhr8mce YoJA== X-Gm-Message-State: ANoB5pnVFuD4845JqlqsgpPJwaDCieLY75ebQXKY5MJmiXYmkG/R7Pt4 bb5jhfWJzn/DsdrY31JhVLExQw== X-Google-Smtp-Source: AA0mqf7UkS0sayfFFpOAxH++j8Z+pl68/NjtGhMcOr2prh8jGf1yg0PEqbltBLaB03l2qEEkkTfrYQ== X-Received: by 2002:a2e:a5c5:0:b0:277:155d:28c4 with SMTP id n5-20020a2ea5c5000000b00277155d28c4mr24523132ljp.123.1670372112267; Tue, 06 Dec 2022 16:15:12 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:11 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 11/18] clk: qcom: smd-rpm: move clock definitions together Date: Wed, 7 Dec 2022 02:14:56 +0200 Message-Id: <20221207001503.93790-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org To ease review and reuse group all clock definitions together. Reviewed-by: Alex Elder Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 128 +++++++++++++++------------------ 1 file changed, 59 insertions(+), 69 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 7e43ecdda763..98d82d1f3a75 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -411,15 +411,73 @@ static const struct clk_ops clk_smd_rpm_branch_ops = { }; DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000); +DEFINE_CLK_SMD_RPM_BRANCH(sm6125, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1, 19200000); +DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); +DEFINE_CLK_SMD_RPM_BRANCH(sm6375, bimc_freq_log, bimc_freq_log_a, QCOM_SMD_RPM_MISC_CLK, 4, 1); + +DEFINE_CLK_SMD_RPM_BRANCH(msm8992, mss_cfg_ahb_clk, mss_cfg_ahb_a_clk, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000); + +DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 1, 1000); +DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); +DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 1); +DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 2); + DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); +DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); +DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); +DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3); +DEFINE_CLK_SMD_RPM(sm6125, snoc_periph_clk, snoc_periph_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6125, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); +DEFINE_CLK_SMD_RPM(sm6125, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); +DEFINE_CLK_SMD_RPM(sm6125, snoc_lpass_clk, snoc_lpass_a_clk, QCOM_SMD_RPM_BUS_CLK, 5); + DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); +DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc_clk, cpuss_gnoc_a_clk, QCOM_SMD_RPM_MEM_CLK, 1); +DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1); +DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); +DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); + +DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); +DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1); +DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2); + +DEFINE_CLK_SMD_RPM(msm8976, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); + +DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0); + +DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6125, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6125, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 1); + +DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0); + DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); -DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); + +DEFINE_CLK_SMD_RPM(sm6125, qup_clk, qup_a_clk, QCOM_SMD_RPM_QUP_CLK, 0); + DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1, bb_clk1_a, 1, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2, bb_clk2_a, 2, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk1, ln_bb_clk1_a, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk2, ln_bb_clk2_a, 2, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1, rf_clk1_a, 4, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2, rf_clk2_a, 5, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3, rf_clk3_a, 6, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk, ln_bb_clk_a, 8, 19200000); + +DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, rf_clk3_a, 6, 38400000); + +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0, cxo_d0_a, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1, cxo_d1_a, 2, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0, cxo_a0_a, 4, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1, cxo_a1_a, 5, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2, cxo_a2_a, 6, 19200000); + +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk, 7, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1, 11, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2, 12, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13, 19200000); static struct clk_smd_rpm *msm8909_clks[] = { [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, @@ -487,8 +545,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8916 = { .num_clks = ARRAY_SIZE(msm8916_clks), }; -DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); - static struct clk_smd_rpm *msm8936_clks[] = { [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, @@ -523,19 +579,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8936 = { .num_clks = ARRAY_SIZE(msm8936_clks), }; -DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3); -DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk, 7, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1, 11, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2, 12, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0, cxo_d0_a, 1, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1, cxo_d1_a, 2, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0, cxo_a0_a, 4, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1, cxo_a1_a, 5, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2, cxo_a2_a, 6, 19200000); - static struct clk_smd_rpm *msm8974_clks[] = { [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, @@ -586,8 +629,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { .num_clks = ARRAY_SIZE(msm8974_clks), }; -DEFINE_CLK_SMD_RPM(msm8976, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); - static struct clk_smd_rpm *msm8976_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, @@ -622,14 +663,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { .num_clks = ARRAY_SIZE(msm8976_clks), }; -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk, ln_bb_clk_a, 8, 19200000); - -DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1); - -DEFINE_CLK_SMD_RPM_BRANCH(msm8992, mss_cfg_ahb_clk, mss_cfg_ahb_a_clk, - QCOM_SMD_RPM_MCFG_CLK, 0, 19200000); static struct clk_smd_rpm *msm8992_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, @@ -688,8 +721,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { .num_clks = ARRAY_SIZE(msm8992_clks), }; -DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2); - static struct clk_smd_rpm *msm8994_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, @@ -750,13 +781,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8994 = { .num_clks = ARRAY_SIZE(msm8994_clks), }; -DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk, - QCOM_SMD_RPM_MMAXI_CLK, 0); -DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk, - QCOM_SMD_RPM_AGGR_CLK, 1, 1000); -DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk, - QCOM_SMD_RPM_AGGR_CLK, 2, 1000); - static struct clk_smd_rpm *msm8996_clks[] = { [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, @@ -809,8 +833,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { .num_clks = ARRAY_SIZE(msm8996_clks), }; -DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); - static struct clk_smd_rpm *qcs404_clks[] = { [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, @@ -839,15 +861,6 @@ static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { .num_clks = ARRAY_SIZE(qcs404_clks), }; -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk1, ln_bb_clk1_a, 1, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk2, ln_bb_clk2_a, 2, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000); -DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk, - QCOM_SMD_RPM_AGGR_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk, - QCOM_SMD_RPM_AGGR_CLK, 2); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3, rf_clk3_a, 6, 19200000); - static struct clk_smd_rpm *msm8998_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, @@ -1012,19 +1025,6 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8953 = { .num_clks = ARRAY_SIZE(msm8953_clks), }; -/* SM6125 */ -DEFINE_CLK_SMD_RPM(sm6125, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM(sm6125, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM_BRANCH(sm6125, qdss_clk, qdss_a_clk, - QCOM_SMD_RPM_MISC_CLK, 1, 19200000); -DEFINE_CLK_SMD_RPM(sm6125, qup_clk, qup_a_clk, QCOM_SMD_RPM_QUP_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6125, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6125, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 1); -DEFINE_CLK_SMD_RPM(sm6125, snoc_periph_clk, snoc_periph_a_clk, - QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6125, snoc_lpass_clk, snoc_lpass_a_clk, - QCOM_SMD_RPM_BUS_CLK, 5); - static struct clk_smd_rpm *sm6125_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, @@ -1108,10 +1108,6 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { .num_clks = ARRAY_SIZE(sm6115_clks), }; -/* SM6375 */ -DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0); -DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0); -DEFINE_CLK_SMD_RPM_BRANCH(sm6375, bimc_freq_log, bimc_freq_log_a, QCOM_SMD_RPM_MISC_CLK, 4, 1); static struct clk_smd_rpm *sm6375_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, @@ -1149,12 +1145,6 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6375 = { .num_clks = ARRAY_SIZE(sm6375_clks), }; -/* QCM2290 */ -DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, rf_clk3_a, 6, 38400000); - -DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc_clk, cpuss_gnoc_a_clk, - QCOM_SMD_RPM_MEM_CLK, 1); - static struct clk_smd_rpm *qcm2290_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, From patchwork Wed Dec 7 00:14:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 631622 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48CE4C4708D for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:12 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 12/18] clk: qcom: smd-rpm: rename some msm8974 active-only clocks Date: Wed, 7 Dec 2022 02:14:57 +0200 Message-Id: <20221207001503.93790-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rename msm8974_diff_a_clk, msm8974_div_a_clk1 and msm8974_div_a_clk2 to move the _a suffix to the end of the name. This follows the pattern used by other active-only clocks and thus makes it possible to simplify clock definitions. This changes the userspace-visible names for this clocks. Reviewed-by: Alex Elder Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 98d82d1f3a75..b32fc7cc1332 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -474,9 +474,9 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0, cxo_a0_a, 4, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1, cxo_a1_a, 5, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2, cxo_a2_a, 6, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk, 7, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1, 11, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2, 12, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_clk_a, 7, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_clk1_a, 11, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_clk2_a, 12, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13, 19200000); static struct clk_smd_rpm *msm8909_clks[] = { @@ -607,11 +607,11 @@ static struct clk_smd_rpm *msm8974_clks[] = { [RPM_SMD_CXO_A2] = &msm8974_cxo_a2, [RPM_SMD_CXO_A2_A] = &msm8974_cxo_a2_a, [RPM_SMD_DIFF_CLK] = &msm8974_diff_clk, - [RPM_SMD_DIFF_A_CLK] = &msm8974_diff_a_clk, + [RPM_SMD_DIFF_A_CLK] = &msm8974_diff_clk_a, [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, - [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, + [RPM_SMD_DIV_A_CLK1] = &msm8974_div_clk1_a, [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, + [RPM_SMD_DIV_A_CLK2] = &msm8974_div_clk2_a, [RPM_SMD_CXO_D0_PIN] = &msm8974_cxo_d0_pin, [RPM_SMD_CXO_D0_A_PIN] = &msm8974_cxo_d0_a_pin, [RPM_SMD_CXO_D1_PIN] = &msm8974_cxo_d1_pin, @@ -653,7 +653,7 @@ static struct clk_smd_rpm *msm8976_clks[] = { [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, + [RPM_SMD_DIV_A_CLK2] = &msm8974_div_clk2_a, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, }; @@ -687,9 +687,9 @@ static struct clk_smd_rpm *msm8992_clks[] = { [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, - [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, + [RPM_SMD_DIV_A_CLK1] = &msm8974_div_clk1_a, [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, + [RPM_SMD_DIV_A_CLK2] = &msm8974_div_clk2_a, [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3, [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, @@ -745,9 +745,9 @@ static struct clk_smd_rpm *msm8994_clks[] = { [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, - [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, + [RPM_SMD_DIV_A_CLK1] = &msm8974_div_clk1_a, [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, + [RPM_SMD_DIV_A_CLK2] = &msm8974_div_clk2_a, [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3, [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, @@ -813,9 +813,9 @@ static struct clk_smd_rpm *msm8996_clks[] = { [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_clk_a, [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, - [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, + [RPM_SMD_DIV_A_CLK1] = &msm8974_div_clk1_a, [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, + [RPM_SMD_DIV_A_CLK2] = &msm8974_div_clk2_a, [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3, [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, @@ -875,9 +875,9 @@ static struct clk_smd_rpm *msm8998_clks[] = { [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, - [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, + [RPM_SMD_DIV_A_CLK1] = &msm8974_div_clk1_a, [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, + [RPM_SMD_DIV_A_CLK2] = &msm8974_div_clk2_a, [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3, [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, @@ -945,7 +945,7 @@ static struct clk_smd_rpm *sdm660_clks[] = { [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, - [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1, + [RPM_SMD_DIV_A_CLK1] = &msm8974_div_clk1_a, [RPM_SMD_LN_BB_CLK] = &msm8998_ln_bb_clk1, [RPM_SMD_LN_BB_A_CLK] = &msm8998_ln_bb_clk1_a, [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2, @@ -1013,7 +1013,7 @@ static struct clk_smd_rpm *msm8953_clks[] = { [RPM_SMD_RF_CLK3] = &qcs404_ln_bb_clk, [RPM_SMD_RF_CLK3_A] = &qcs404_ln_bb_clk_a, [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2, + [RPM_SMD_DIV_A_CLK2] = &msm8974_div_clk2_a, [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, From patchwork Wed Dec 7 00:14:58 2022 Content-Type: text/plain; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:13 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 13/18] clk: qcom: smd-rpm: simplify XO_BUFFER clocks definitions Date: Wed, 7 Dec 2022 02:14:58 +0200 Message-Id: <20221207001503.93790-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove the duplication between the names of the normal and active-only XO_BUFFER and XO_BUFFER_PINCTRL clocks by using preprocessor logic to add _a suffix. Reviewed-by: Alex Elder Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 56 ++++++++++++++++------------------ 1 file changed, 27 insertions(+), 29 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index b32fc7cc1332..c5a4a648ddb1 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -112,17 +112,15 @@ __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \ QCOM_RPM_SMD_KEY_STATE) -#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id, r) \ - __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \ +#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, r_id, r) \ + __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _name##_a, \ QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ QCOM_RPM_KEY_SOFTWARE_ENABLE) -#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, \ - r_id, r) \ - DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, \ - r_id, r); \ +#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, r_id, r) \ + DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, r_id, r); \ __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name##_pin, \ - _active##_pin, \ + _name##_a##_pin, \ QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY) @@ -456,28 +454,28 @@ DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); DEFINE_CLK_SMD_RPM(sm6125, qup_clk, qup_a_clk, QCOM_SMD_RPM_QUP_CLK, 0); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1, bb_clk1_a, 1, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2, bb_clk2_a, 2, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk1, ln_bb_clk1_a, 1, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk2, ln_bb_clk2_a, 2, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1, rf_clk1_a, 4, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2, rf_clk2_a, 5, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3, rf_clk3_a, 6, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk, ln_bb_clk_a, 8, 19200000); - -DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, rf_clk3_a, 6, 38400000); - -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0, cxo_d0_a, 1, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1, cxo_d1_a, 2, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0, cxo_a0_a, 4, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1, cxo_a1_a, 5, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2, cxo_a2_a, 6, 19200000); - -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_clk_a, 7, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_clk1_a, 11, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_clk2_a, 12, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2, 2, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk1, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk2, 2, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3, 3, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1, 4, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2, 5, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3, 6, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk, 8, 19200000); + +DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, 6, 38400000); + +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1, 2, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0, 4, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1, 5, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2, 6, 19200000); + +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, 7, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, 11, 19200000); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:14 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 14/18] clk: qcom: smd-rpm: simplify SMD_RPM/_BRANCH/_QDSS clock definitions Date: Wed, 7 Dec 2022 02:14:59 +0200 Message-Id: <20221207001503.93790-15-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove the duplication between the names of the normal and active-only clocks by moving common sufixes to the clock definition macros. This simplifies adding new clock definitions and reviewing existing defs. Reviewed-by: Alex Elder Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 96 +++++++++++++++++++--------------- 1 file changed, 53 insertions(+), 43 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index c5a4a648ddb1..a3f08ebcae4e 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -100,17 +100,27 @@ }, \ } -#define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id) \ - __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \ - QCOM_RPM_SMD_KEY_RATE) - -#define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r) \ - __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, \ +#define DEFINE_CLK_SMD_RPM(_platform, _name, type, r_id) \ + __DEFINE_CLK_SMD_RPM(_platform, _name##_clk, _name##_a_clk, \ + type, r_id, QCOM_RPM_SMD_KEY_RATE) + +#define DEFINE_CLK_SMD_RPM_CLK_SRC(_platform, _name, type, r_id) \ + __DEFINE_CLK_SMD_RPM(_platform, \ + _name##_clk_src, _name##_a_clk_src, \ + type, r_id, QCOM_RPM_SMD_KEY_RATE) + +#define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, type, r_id, r) \ + __DEFINE_CLK_SMD_RPM_BRANCH(_platform, \ + _name##_clk, _name##_a_clk, \ + type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE) + +#define DEFINE_CLK_SMD_RPM_BRANCH_A(_platform, _name, type, r_id, r) \ + __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _name##_a, type,\ r_id, r, QCOM_RPM_SMD_KEY_ENABLE) -#define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id) \ - __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \ - QCOM_RPM_SMD_KEY_STATE) +#define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, type, r_id) \ + __DEFINE_CLK_SMD_RPM(_platform, _name##_clk, _name##_a_clk, \ + type, r_id, QCOM_RPM_SMD_KEY_STATE) #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, r_id, r) \ __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _name##_a, \ @@ -408,51 +418,51 @@ static const struct clk_ops clk_smd_rpm_branch_ops = { .recalc_rate = clk_smd_rpm_recalc_rate, }; -DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000); -DEFINE_CLK_SMD_RPM_BRANCH(sm6125, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1, 19200000); -DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1); -DEFINE_CLK_SMD_RPM_BRANCH(sm6375, bimc_freq_log, bimc_freq_log_a, QCOM_SMD_RPM_MISC_CLK, 4, 1); +DEFINE_CLK_SMD_RPM_BRANCH_A(sdm660, bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000); +DEFINE_CLK_SMD_RPM_BRANCH(sm6125, qdss, QCOM_SMD_RPM_MISC_CLK, 1, 19200000); +DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss, QCOM_SMD_RPM_MISC_CLK, 1); +DEFINE_CLK_SMD_RPM_BRANCH_A(sm6375, bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1); -DEFINE_CLK_SMD_RPM_BRANCH(msm8992, mss_cfg_ahb_clk, mss_cfg_ahb_a_clk, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000); +DEFINE_CLK_SMD_RPM_BRANCH(msm8992, mss_cfg_ahb, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000); -DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 1, 1000); -DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); -DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk, QCOM_SMD_RPM_AGGR_CLK, 2); +DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1, 1000); +DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); +DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1); +DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3); -DEFINE_CLK_SMD_RPM(sm6125, snoc_periph_clk, snoc_periph_a_clk, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6125, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM(sm6125, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(sm6125, snoc_lpass_clk, snoc_lpass_a_clk, QCOM_SMD_RPM_BUS_CLK, 5); +DEFINE_CLK_SMD_RPM(msm8916, pcnoc, QCOM_SMD_RPM_BUS_CLK, 0); +DEFINE_CLK_SMD_RPM(msm8916, snoc, QCOM_SMD_RPM_BUS_CLK, 1); +DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc, QCOM_SMD_RPM_BUS_CLK, 2); +DEFINE_CLK_SMD_RPM(msm8974, cnoc, QCOM_SMD_RPM_BUS_CLK, 2); +DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb, QCOM_SMD_RPM_BUS_CLK, 3); +DEFINE_CLK_SMD_RPM(sm6125, snoc_periph, QCOM_SMD_RPM_BUS_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6125, cnoc, QCOM_SMD_RPM_BUS_CLK, 1); +DEFINE_CLK_SMD_RPM(sm6125, snoc, QCOM_SMD_RPM_BUS_CLK, 2); +DEFINE_CLK_SMD_RPM(sm6125, snoc_lpass, QCOM_SMD_RPM_BUS_CLK, 5); -DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0); -DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc_clk, cpuss_gnoc_a_clk, QCOM_SMD_RPM_MEM_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); -DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2); +DEFINE_CLK_SMD_RPM(msm8916, bimc, QCOM_SMD_RPM_MEM_CLK, 0); +DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc, QCOM_SMD_RPM_MEM_CLK, 1); +DEFINE_CLK_SMD_RPM_CLK_SRC(msm8974, gfx3d, QCOM_SMD_RPM_MEM_CLK, 1); +DEFINE_CLK_SMD_RPM(msm8974, ocmemgx, QCOM_SMD_RPM_MEM_CLK, 2); +DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu, QCOM_SMD_RPM_MEM_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2); +DEFINE_CLK_SMD_RPM(msm8992, ce1, QCOM_SMD_RPM_CE_CLK, 0); +DEFINE_CLK_SMD_RPM(msm8992, ce2, QCOM_SMD_RPM_CE_CLK, 1); +DEFINE_CLK_SMD_RPM(msm8994, ce3, QCOM_SMD_RPM_CE_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8976, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0); +DEFINE_CLK_SMD_RPM(msm8976, ipa, QCOM_SMD_RPM_IPA_CLK, 0); -DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0); +DEFINE_CLK_SMD_RPM(qcm2290, hwkm, QCOM_SMD_RPM_HWKM_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6125, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6125, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 1); +DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm, QCOM_SMD_RPM_MMAXI_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6125, mmnrt, QCOM_SMD_RPM_MMAXI_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6125, mmrt, QCOM_SMD_RPM_MMAXI_CLK, 1); -DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0); +DEFINE_CLK_SMD_RPM(qcm2290, pka, QCOM_SMD_RPM_PKA_CLK, 0); -DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0); +DEFINE_CLK_SMD_RPM(qcs404, qpic, QCOM_SMD_RPM_QPIC_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6125, qup_clk, qup_a_clk, QCOM_SMD_RPM_QUP_CLK, 0); +DEFINE_CLK_SMD_RPM(sm6125, qup, QCOM_SMD_RPM_QUP_CLK, 0); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1, 1, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2, 2, 19200000); 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:14 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 15/18] clk: qcom: smd-rpm: rename SMD_RPM_BRANCH clock symbols Date: Wed, 7 Dec 2022 02:15:00 +0200 Message-Id: <20221207001503.93790-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org To ease distinguishing between branch and non-branch clocks (e.g. aggre1_noc, aggre2_noc and qdss) add '_branch' to all SMD_RPM_BRANCH* clocks. The system (and userspace) name of these clocks remains intact. Reviewed-by: Konrad Dybcio Reviewed-by: Alex Elder Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 102 +++++++++++++++++---------------- 1 file changed, 54 insertions(+), 48 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index a3f08ebcae4e..8963ade901ea 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -61,15 +61,15 @@ }, \ } -#define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, \ - r, key) \ - static struct clk_smd_rpm _platform##_##_active; \ - static struct clk_smd_rpm _platform##_##_name = { \ +#define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_platform, _prefix, _name, _active,\ + type, r_id, r, key) \ + static struct clk_smd_rpm _platform##_##_prefix##_active; \ + static struct clk_smd_rpm _platform##_##_prefix##_name = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ .rpm_key = (key), \ .branch = true, \ - .peer = &_platform##_##_active, \ + .peer = &_platform##_##_prefix##_active, \ .rate = (r), \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_branch_ops, \ @@ -81,13 +81,13 @@ .num_parents = 1, \ }, \ }; \ - static struct clk_smd_rpm _platform##_##_active = { \ + static struct clk_smd_rpm _platform##_##_prefix##_active = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ .active_only = true, \ .rpm_key = (key), \ .branch = true, \ - .peer = &_platform##_##_name, \ + .peer = &_platform##_##_prefix##_name, \ .rate = (r), \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_branch_ops, \ @@ -100,6 +100,11 @@ }, \ } +#define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, \ + r, key) \ + __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_platform, /* empty */, \ + _name, _active, type, r_id, r, key) + #define DEFINE_CLK_SMD_RPM(_platform, _name, type, r_id) \ __DEFINE_CLK_SMD_RPM(_platform, _name##_clk, _name##_a_clk, \ type, r_id, QCOM_RPM_SMD_KEY_RATE) @@ -110,12 +115,13 @@ type, r_id, QCOM_RPM_SMD_KEY_RATE) #define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, type, r_id, r) \ - __DEFINE_CLK_SMD_RPM_BRANCH(_platform, \ + __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_platform, branch_, \ _name##_clk, _name##_a_clk, \ type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE) #define DEFINE_CLK_SMD_RPM_BRANCH_A(_platform, _name, type, r_id, r) \ - __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _name##_a, type,\ + __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_platform, branch_, \ + _name, _name##_a, type, \ r_id, r, QCOM_RPM_SMD_KEY_ENABLE) #define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, type, r_id) \ @@ -638,8 +644,8 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { }; static struct clk_smd_rpm *msm8976_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, @@ -672,8 +678,8 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { }; static struct clk_smd_rpm *msm8992_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, @@ -706,8 +712,8 @@ static struct clk_smd_rpm *msm8992_clks[] = { [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_clk_a, [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, - [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk, - [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk, + [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_branch_mss_cfg_ahb_clk, + [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_branch_mss_cfg_ahb_a_clk, [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, @@ -730,8 +736,8 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { }; static struct clk_smd_rpm *msm8994_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, @@ -764,8 +770,8 @@ static struct clk_smd_rpm *msm8994_clks[] = { [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_clk_a, [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, - [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk, - [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk, + [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_branch_mss_cfg_ahb_clk, + [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_branch_mss_cfg_ahb_a_clk, [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, @@ -804,10 +810,10 @@ static struct clk_smd_rpm *msm8996_clks[] = { [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, - [RPM_SMD_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk, - [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk, - [RPM_SMD_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk, - [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk, + [RPM_SMD_AGGR1_NOC_CLK] = &msm8996_branch_aggre1_noc_clk, + [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8996_branch_aggre1_noc_a_clk, + [RPM_SMD_AGGR2_NOC_CLK] = &msm8996_branch_aggre2_noc_clk, + [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8996_branch_aggre2_noc_a_clk, [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, @@ -870,8 +876,8 @@ static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { }; static struct clk_smd_rpm *msm8998_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, @@ -930,8 +936,8 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { }; static struct clk_smd_rpm *sdm660_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, @@ -976,8 +982,8 @@ static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { }; static struct clk_smd_rpm *mdm9607_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, @@ -998,8 +1004,8 @@ static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = { }; static struct clk_smd_rpm *msm8953_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, @@ -1034,14 +1040,14 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8953 = { }; static struct clk_smd_rpm *sm6125_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk, + [RPM_SMD_QDSS_CLK] = &sm6125_branch_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &sm6125_branch_qdss_a_clk, [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, @@ -1077,14 +1083,14 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6125 = { /* SM6115 */ static struct clk_smd_rpm *sm6115_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk, + [RPM_SMD_QDSS_CLK] = &sm6125_branch_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &sm6125_branch_qdss_a_clk, [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, @@ -1117,14 +1123,14 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { }; static struct clk_smd_rpm *sm6375_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk, + [RPM_SMD_QDSS_CLK] = &sm6125_branch_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &sm6125_branch_qdss_a_clk, [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk, [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, @@ -1145,7 +1151,7 @@ static struct clk_smd_rpm *sm6375_clks[] = { [RPM_SMD_HWKM_A_CLK] = &qcm2290_hwkm_a_clk, [RPM_SMD_PKA_CLK] = &qcm2290_pka_clk, [RPM_SMD_PKA_A_CLK] = &qcm2290_pka_a_clk, - [RPM_SMD_BIMC_FREQ_LOG] = &sm6375_bimc_freq_log, + [RPM_SMD_BIMC_FREQ_LOG] = &sm6375_branch_bimc_freq_log, }; static const struct rpm_smd_clk_desc rpm_clk_sm6375 = { @@ -1154,14 +1160,14 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6375 = { }; static struct clk_smd_rpm *qcm2290_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a, + [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk, + [RPM_SMD_QDSS_CLK] = &sm6125_branch_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &sm6125_branch_qdss_a_clk, [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2, [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a, [RPM_SMD_RF_CLK3] = &qcm2290_rf_clk3, From patchwork Wed Dec 7 00:15:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 632387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37CEEC6370D for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:15 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 16/18] clk: qcom: smd-rpm: rename the qcm2290 rf_clk3 clocks Date: Wed, 7 Dec 2022 02:15:01 +0200 Message-Id: <20221207001503.93790-17-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rename the qcm2290_rf_clk3 clocks adding 38m4 prefix to distinguish it from the common (19.2 MHz) rf_clk3. The system (and userspace) name of these clocks remains intact. Reviewed-by: Konrad Dybcio Reviewed-by: Alex Elder Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 8963ade901ea..4db92d2d91b8 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -133,6 +133,12 @@ QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ QCOM_RPM_KEY_SOFTWARE_ENABLE) +#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(_platform, _prefix, _name, r_id, r) \ + __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_platform, _prefix, \ + _name, _name##_a, \ + QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ + QCOM_RPM_KEY_SOFTWARE_ENABLE) + #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, r_id, r) \ DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, r_id, r); \ __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name##_pin, \ @@ -480,7 +486,7 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2, 5, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3, 6, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk, 8, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, 6, 38400000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(qcm2290, 38m4_, rf_clk3, 6, 38400000); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0, 1, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1, 2, 19200000); @@ -1170,8 +1176,8 @@ static struct clk_smd_rpm *qcm2290_clks[] = { [RPM_SMD_QDSS_A_CLK] = &sm6125_branch_qdss_a_clk, [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2, [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a, - [RPM_SMD_RF_CLK3] = &qcm2290_rf_clk3, - [RPM_SMD_RF_CLK3_A] = &qcm2290_rf_clk3_a, + [RPM_SMD_RF_CLK3] = &qcm2290_38m4_rf_clk3, + [RPM_SMD_RF_CLK3_A] = &qcm2290_38m4_rf_clk3_a, [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk, [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, From patchwork Wed Dec 7 00:15:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 631619 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6A32C63707 for ; Wed, 7 Dec 2022 00:15:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229660AbiLGAPc (ORCPT ); Tue, 6 Dec 2022 19:15:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229822AbiLGAPZ (ORCPT ); Tue, 6 Dec 2022 19:15:25 -0500 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BD754B9B1 for ; Tue, 6 Dec 2022 16:15:17 -0800 (PST) Received: by mail-lf1-x136.google.com with SMTP id c1so26219375lfi.7 for ; Tue, 06 Dec 2022 16:15:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aXWCcgyuxb4JgpfKW7ku4WXMqbrRsTauiJ6fzFvhB7A=; b=T5+bB3WF6yRsY6GpelrElR6cpszyIyAo3NKqV+tRPFIOFn5t56jULctW/drN2//oXX wj9w0BVi90ZjU15gs7iBqQ9wMUEiafCQlQvtQY9xaO1eQ9+IofmjizqF/o1tcGZmyDBU 0NbiY0YaF7SCYmXU5DHjGXBAulG77oB6i4q7/D+XbFfBsx3ioG5btNtgFeKO0o1To/Ar 8nhgCVqCvZDuDkkndX2m/5Dk0ncZmiN3jQ700goQep/pi9JgyKWC9K0eJgMnlwLLx03b k958YptFbnZBLGjhx01EiO4T7neMwvgVHYPZFW6oqDu1S9d+paseWld9ugA2rYSFqogB gRvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aXWCcgyuxb4JgpfKW7ku4WXMqbrRsTauiJ6fzFvhB7A=; b=18oJevIsjEYY7k5qi5Br2cD/jqe7sYNP221MoTYV0je7j1nV1lxaJaplYM2WgH0ZdG PY1bQbvJndvfOhZXgYHL136SCYC67kj/AjkT0b0RymwO+fuwMisiuWTvnAjfRkCvs5FP O9U8c0BAa/iutxqzBf4+xGquA2/fS0BLm6EA3ZKzuT+j5Azfasc0TFunlcM6/UN/CnoS cEPHisDzVnVEUnF8T+f5Vp5ZJC2vtzfebs/imTg6E4O3XDfOsKg4Img8MudBsv8Hs4d1 SUWjNyzZ5sWanzORv+g66nu9NvRlGu4Z7/03GCTf9XqpDkIlNOwWJFTsJDV0n5tJ6h9W B2Qw== X-Gm-Message-State: ANoB5plSRWSd/UabD52cyWVXBGPC0UavrMrsHz7FdBcp2uFZrNMpLO+h /4Rvgtb+rifciwP/bHzeRFpXMA== X-Google-Smtp-Source: AA0mqf4r576tUpIrV4bl5FnlSLXlP8vwHhzaJ9k8xAOeE0SO9hwpXU8dnKQnjZsn38XPhyV5ivkJYQ== X-Received: by 2002:a05:6512:3d05:b0:4a2:4f6d:7963 with SMTP id d5-20020a0565123d0500b004a24f6d7963mr33129455lfv.638.1670372116976; Tue, 06 Dec 2022 16:15:16 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:16 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 17/18] clk: qcom: smd-rpm: rename SMD_RPM_BUS clocks Date: Wed, 7 Dec 2022 02:15:02 +0200 Message-Id: <20221207001503.93790-18-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add special macro for the clocks of QCOM_SMD_RPM_BUS_CLK type. Use it to insert the _bus_N part into the clock symbol name. The system (and userspace) name of these clocks remains intact. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 252 +++++++++++++++++---------------- 1 file changed, 131 insertions(+), 121 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index 4db92d2d91b8..b8e649a6a76c 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -25,13 +25,14 @@ #define QCOM_RPM_SMD_KEY_STATE 0x54415453 #define QCOM_RPM_SCALING_ENABLE_ID 0x2 -#define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, key) \ - static struct clk_smd_rpm _platform##_##_active; \ - static struct clk_smd_rpm _platform##_##_name = { \ +#define __DEFINE_CLK_SMD_RPM_PREFIX(_platform, _prefix, _name, _active, \ + type, r_id, key) \ + static struct clk_smd_rpm _platform##_##_prefix##_active; \ + static struct clk_smd_rpm _platform##_##_prefix##_name = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ .rpm_key = (key), \ - .peer = &_platform##_##_active, \ + .peer = &_platform##_##_prefix##_active, \ .rate = INT_MAX, \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_ops, \ @@ -43,12 +44,12 @@ .num_parents = 1, \ }, \ }; \ - static struct clk_smd_rpm _platform##_##_active = { \ + static struct clk_smd_rpm _platform##_##_prefix##_active = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ .active_only = true, \ .rpm_key = (key), \ - .peer = &_platform##_##_name, \ + .peer = &_platform##_##_prefix##_name, \ .rate = INT_MAX, \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_ops, \ @@ -61,6 +62,10 @@ }, \ } +#define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, key) \ + __DEFINE_CLK_SMD_RPM_PREFIX(_platform, /* empty */, _name, _active, \ + type, r_id, key) + #define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_platform, _prefix, _name, _active,\ type, r_id, r, key) \ static struct clk_smd_rpm _platform##_##_prefix##_active; \ @@ -109,6 +114,11 @@ __DEFINE_CLK_SMD_RPM(_platform, _name##_clk, _name##_a_clk, \ type, r_id, QCOM_RPM_SMD_KEY_RATE) +#define DEFINE_CLK_SMD_RPM_BUS(_platform, _name, r_id) \ + __DEFINE_CLK_SMD_RPM_PREFIX(_platform, bus_##r_id##_, \ + _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \ + QCOM_RPM_SMD_KEY_RATE) + #define DEFINE_CLK_SMD_RPM_CLK_SRC(_platform, _name, type, r_id) \ __DEFINE_CLK_SMD_RPM(_platform, \ _name##_clk_src, _name##_a_clk_src, \ @@ -442,15 +452,15 @@ DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1); DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8916, pcnoc, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8916, snoc, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8974, cnoc, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb, QCOM_SMD_RPM_BUS_CLK, 3); -DEFINE_CLK_SMD_RPM(sm6125, snoc_periph, QCOM_SMD_RPM_BUS_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6125, cnoc, QCOM_SMD_RPM_BUS_CLK, 1); -DEFINE_CLK_SMD_RPM(sm6125, snoc, QCOM_SMD_RPM_BUS_CLK, 2); -DEFINE_CLK_SMD_RPM(sm6125, snoc_lpass, QCOM_SMD_RPM_BUS_CLK, 5); +DEFINE_CLK_SMD_RPM_BUS(msm8916, pcnoc, 0); +DEFINE_CLK_SMD_RPM_BUS(msm8916, snoc, 1); +DEFINE_CLK_SMD_RPM_BUS(msm8936, sysmmnoc, 2); +DEFINE_CLK_SMD_RPM_BUS(msm8974, cnoc, 2); +DEFINE_CLK_SMD_RPM_BUS(msm8974, mmssnoc_ahb, 3); +DEFINE_CLK_SMD_RPM_BUS(sm6125, snoc_periph, 0); +DEFINE_CLK_SMD_RPM_BUS(sm6125, cnoc, 1); +DEFINE_CLK_SMD_RPM_BUS(sm6125, snoc, 2); +DEFINE_CLK_SMD_RPM_BUS(sm6125, snoc_lpass, 5); DEFINE_CLK_SMD_RPM(msm8916, bimc, QCOM_SMD_RPM_MEM_CLK, 0); DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc, QCOM_SMD_RPM_MEM_CLK, 1); @@ -500,10 +510,10 @@ DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, 12, 19200000); DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, 13, 19200000); static struct clk_smd_rpm *msm8909_clks[] = { - [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, @@ -534,10 +544,10 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8909 = { }; static struct clk_smd_rpm *msm8916_clks[] = { - [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, @@ -566,14 +576,14 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8916 = { }; static struct clk_smd_rpm *msm8936_clks[] = { - [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_SYSMMNOC_CLK] = &msm8936_sysmmnoc_clk, - [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_sysmmnoc_a_clk, + [RPM_SMD_SYSMMNOC_CLK] = &msm8936_bus_2_sysmmnoc_clk, + [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_bus_2_sysmmnoc_a_clk, [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, @@ -600,14 +610,14 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8936 = { }; static struct clk_smd_rpm *msm8974_clks[] = { - [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, - [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, - [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, + [RPM_SMD_PNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, + [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_bus_3_mmssnoc_ahb_clk, + [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_bus_3_mmssnoc_ahb_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src, [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src, @@ -652,14 +662,14 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { static struct clk_smd_rpm *msm8976_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_SYSMMNOC_CLK] = &msm8936_sysmmnoc_clk, - [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_sysmmnoc_a_clk, + [RPM_SMD_SYSMMNOC_CLK] = &msm8936_bus_2_sysmmnoc_clk, + [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_bus_2_sysmmnoc_a_clk, [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, @@ -686,18 +696,18 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { static struct clk_smd_rpm *msm8992_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, + [RPM_SMD_PNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src, [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, @@ -716,8 +726,8 @@ static struct clk_smd_rpm *msm8992_clks[] = { [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_clk_a, - [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, - [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, + [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_bus_3_mmssnoc_ahb_clk, + [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_bus_3_mmssnoc_ahb_a_clk, [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_branch_mss_cfg_ahb_clk, [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_branch_mss_cfg_ahb_a_clk, [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, @@ -744,18 +754,18 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { static struct clk_smd_rpm *msm8994_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, + [RPM_SMD_PNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src, [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, @@ -774,8 +784,8 @@ static struct clk_smd_rpm *msm8994_clks[] = { [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_clk_a, - [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk, - [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk, + [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_bus_3_mmssnoc_ahb_clk, + [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_bus_3_mmssnoc_ahb_a_clk, [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_branch_mss_cfg_ahb_clk, [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_branch_mss_cfg_ahb_a_clk, [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, @@ -802,12 +812,12 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8994 = { }; static struct clk_smd_rpm *msm8996_clks[] = { - [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, @@ -856,10 +866,10 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { static struct clk_smd_rpm *qcs404_clks[] = { [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, - [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_PNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk, @@ -886,12 +896,12 @@ static struct clk_smd_rpm *msm8998_clks[] = { [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, @@ -944,12 +954,12 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { static struct clk_smd_rpm *sdm660_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk, - [RPM_SMD_CNOC_PERIPH_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_CNOC_PERIPH_A_CLK] = &msm8916_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, + [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, + [RPM_SMD_CNOC_PERIPH_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_CNOC_PERIPH_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_MMSSNOC_AXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, @@ -990,8 +1000,8 @@ static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { static struct clk_smd_rpm *mdm9607_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, @@ -1012,16 +1022,16 @@ static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = { static struct clk_smd_rpm *msm8953_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk, + [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, - [RPM_SMD_SYSMMNOC_CLK] = &msm8936_sysmmnoc_clk, - [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_sysmmnoc_a_clk, + [RPM_SMD_SYSMMNOC_CLK] = &msm8936_bus_2_sysmmnoc_clk, + [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_bus_2_sysmmnoc_a_clk, [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, @@ -1048,8 +1058,8 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8953 = { static struct clk_smd_rpm *sm6125_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, + [RPM_SMD_SNOC_CLK] = &sm6125_bus_2_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &sm6125_bus_2_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &sm6125_branch_qdss_clk, @@ -1058,8 +1068,8 @@ static struct clk_smd_rpm *sm6125_clks[] = { [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk, + [RPM_SMD_CNOC_CLK] = &sm6125_bus_1_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &sm6125_bus_1_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, @@ -1076,10 +1086,10 @@ static struct clk_smd_rpm *sm6125_clks[] = { [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, - [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk, - [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk, - [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk, - [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk, + [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_bus_0_snoc_periph_clk, + [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_bus_0_snoc_periph_a_clk, + [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_bus_5_snoc_lpass_clk, + [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_bus_5_snoc_lpass_a_clk, }; static const struct rpm_smd_clk_desc rpm_clk_sm6125 = { @@ -1091,8 +1101,8 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6125 = { static struct clk_smd_rpm *sm6115_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, + [RPM_SMD_SNOC_CLK] = &sm6125_bus_2_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &sm6125_bus_2_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &sm6125_branch_qdss_clk, @@ -1101,8 +1111,8 @@ static struct clk_smd_rpm *sm6115_clks[] = { [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk, + [RPM_SMD_CNOC_CLK] = &sm6125_bus_1_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &sm6125_bus_1_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, @@ -1113,10 +1123,10 @@ static struct clk_smd_rpm *sm6115_clks[] = { [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, - [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk, - [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk, - [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk, - [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk, + [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_bus_0_snoc_periph_clk, + [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_bus_0_snoc_periph_a_clk, + [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_bus_5_snoc_lpass_clk, + [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_bus_5_snoc_lpass_a_clk, [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, @@ -1131,14 +1141,14 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { static struct clk_smd_rpm *sm6375_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, + [RPM_SMD_SNOC_CLK] = &sm6125_bus_2_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &sm6125_bus_2_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &sm6125_branch_qdss_clk, [RPM_SMD_QDSS_A_CLK] = &sm6125_branch_qdss_a_clk, - [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk, + [RPM_SMD_CNOC_CLK] = &sm6125_bus_1_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &sm6125_bus_1_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, @@ -1147,10 +1157,10 @@ static struct clk_smd_rpm *sm6375_clks[] = { [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, - [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk, - [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk, - [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk, - [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk, + [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_bus_0_snoc_periph_clk, + [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_bus_0_snoc_periph_a_clk, + [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_bus_5_snoc_lpass_clk, + [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_bus_5_snoc_lpass_a_clk, [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, [RPM_SMD_HWKM_CLK] = &qcm2290_hwkm_clk, @@ -1168,8 +1178,8 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6375 = { static struct clk_smd_rpm *qcm2290_clks[] = { [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk, + [RPM_SMD_SNOC_CLK] = &sm6125_bus_2_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &sm6125_bus_2_snoc_a_clk, [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, [RPM_SMD_QDSS_CLK] = &sm6125_branch_qdss_clk, @@ -1178,8 +1188,8 @@ static struct clk_smd_rpm *qcm2290_clks[] = { [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a, [RPM_SMD_RF_CLK3] = &qcm2290_38m4_rf_clk3, [RPM_SMD_RF_CLK3_A] = &qcm2290_38m4_rf_clk3_a, - [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk, + [RPM_SMD_CNOC_CLK] = &sm6125_bus_1_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &sm6125_bus_1_cnoc_a_clk, [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, @@ -1188,10 +1198,10 @@ static struct clk_smd_rpm *qcm2290_clks[] = { [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, - [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk, - [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk, - [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk, - [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk, + [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_bus_0_snoc_periph_clk, + [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_bus_0_snoc_periph_a_clk, + [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_bus_5_snoc_lpass_clk, + [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_bus_5_snoc_lpass_a_clk, [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, From patchwork Wed Dec 7 00:15:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 632386 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5ABB1C6370C for ; Wed, 7 Dec 2022 00:15:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229755AbiLGAPe (ORCPT ); Tue, 6 Dec 2022 19:15:34 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229895AbiLGAP0 (ORCPT ); Tue, 6 Dec 2022 19:15:26 -0500 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9FF2A4D5E7 for ; Tue, 6 Dec 2022 16:15:18 -0800 (PST) Received: by mail-lj1-x22c.google.com with SMTP id f20so5920251lja.4 for ; Tue, 06 Dec 2022 16:15:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eS18dDYAFlu7NH8lIu24kELjsWR0luh+6GBIKlov3hk=; b=lbs/+hjuAdNnoplTu6m5DnX3ebdCGTnen97ClhhuL0jMo5v0CzEV/cRIXkeh19Wic0 jeqa3VVm6FG6WKfkZrzFYOda+A/Rn4IynVOlIoKfvgaTY++EpL7jPJX5OvR63mwwDOly Htx+1VDM0YqR8KkbFXVZOroMtRe9m+RvXEbSYbtiUQ8ltEDDnHo1r3tNmZJovuHqfzm0 smeh/hb23CnePtdzfvYDlZZvS6Ad+lCPMFl3CzZ+sJilSGH2bPVbsf//dKAEU28nReJB 9rjH61KeeBAWOuM4pZsPf9aciVr2lMRjbDoFiWyfFuU1+fARZLsnogT912WhczZSuZPS P5Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eS18dDYAFlu7NH8lIu24kELjsWR0luh+6GBIKlov3hk=; b=nBLAQvs2iUZzxOy2wFcbLeLNjvqsJf8HovIkf0mns6QbkmAhj12pTa5hX5vy5quTJs r3Ki7E5TXYN8aUobJuJmgs7sw2tcyv22Ui5fQ1pyviWGygPAeEbLsBL7kMFssAvYoG12 Mkpd+KlmlK6P1zK9V5WfH8Rw8Gzbd+lHpYeUg9+eK9pHJt8PReu5pMz4hE6Og4XHDHhZ svMl3RBeADtDgJLk07CubDu+f07pUQPASRYTJUHBKPlB9dVOsVAdqvFEq2KVH+/ozAuJ kf70n12+E48DGRd/D07He8S5BdozcgQTdjBz0wUH0EGJgTUB8cQjfPE7j2TT3ZaICD6o bwZw== X-Gm-Message-State: ANoB5plViqIzjR19uYcTvpfoX5uhOrjDgZsqNKKrYX1FslRN9tbCHNN9 Qxgb/Re7sADxeff24dkY0Qlr1A== X-Google-Smtp-Source: AA0mqf5IhVnddi/+iFP8a2qKFGYd0BHzDCCPsqHuXSXCllHm3IznAeI+UnbPrHTg+jpf5Gow2Nc76w== X-Received: by 2002:a2e:a90b:0:b0:277:794:ae09 with SMTP id j11-20020a2ea90b000000b002770794ae09mr27365078ljq.286.1670372117954; Tue, 06 Dec 2022 16:15:17 -0800 (PST) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id 16-20020ac25f50000000b004b53eb60e3csm2308555lfz.256.2022.12.06.16.15.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Dec 2022 16:15:17 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, Alex Elder Subject: [PATCH v2 18/18] clk: qcom: smd-rpm: remove usage of platform name Date: Wed, 7 Dec 2022 02:15:03 +0200 Message-Id: <20221207001503.93790-19-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> References: <20221207001503.93790-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now that all clocks have individual names, remove the names of SoCs from the SMD RPM clock definitions. Replace it with the common clk_smd_rpm_ prefix. Reviewed-by: Alex Elder Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/clk-smd-rpm.c | 1328 ++++++++++++++++---------------- 1 file changed, 663 insertions(+), 665 deletions(-) diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c index b8e649a6a76c..8f6e274c6030 100644 --- a/drivers/clk/qcom/clk-smd-rpm.c +++ b/drivers/clk/qcom/clk-smd-rpm.c @@ -25,14 +25,14 @@ #define QCOM_RPM_SMD_KEY_STATE 0x54415453 #define QCOM_RPM_SCALING_ENABLE_ID 0x2 -#define __DEFINE_CLK_SMD_RPM_PREFIX(_platform, _prefix, _name, _active, \ +#define __DEFINE_CLK_SMD_RPM_PREFIX(_prefix, _name, _active, \ type, r_id, key) \ - static struct clk_smd_rpm _platform##_##_prefix##_active; \ - static struct clk_smd_rpm _platform##_##_prefix##_name = { \ + static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \ + static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ .rpm_key = (key), \ - .peer = &_platform##_##_prefix##_active, \ + .peer = &clk_smd_rpm_##_prefix##_active, \ .rate = INT_MAX, \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_ops, \ @@ -44,12 +44,12 @@ .num_parents = 1, \ }, \ }; \ - static struct clk_smd_rpm _platform##_##_prefix##_active = { \ + static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ .active_only = true, \ .rpm_key = (key), \ - .peer = &_platform##_##_prefix##_name, \ + .peer = &clk_smd_rpm_##_prefix##_name, \ .rate = INT_MAX, \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_ops, \ @@ -62,19 +62,19 @@ }, \ } -#define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, key) \ - __DEFINE_CLK_SMD_RPM_PREFIX(_platform, /* empty */, _name, _active, \ +#define __DEFINE_CLK_SMD_RPM(_name, _active, type, r_id, key) \ + __DEFINE_CLK_SMD_RPM_PREFIX(/* empty */, _name, _active, \ type, r_id, key) -#define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_platform, _prefix, _name, _active,\ +#define __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, _name, _active,\ type, r_id, r, key) \ - static struct clk_smd_rpm _platform##_##_prefix##_active; \ - static struct clk_smd_rpm _platform##_##_prefix##_name = { \ + static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active; \ + static struct clk_smd_rpm clk_smd_rpm_##_prefix##_name = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ .rpm_key = (key), \ .branch = true, \ - .peer = &_platform##_##_prefix##_active, \ + .peer = &clk_smd_rpm_##_prefix##_active, \ .rate = (r), \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_branch_ops, \ @@ -86,13 +86,13 @@ .num_parents = 1, \ }, \ }; \ - static struct clk_smd_rpm _platform##_##_prefix##_active = { \ + static struct clk_smd_rpm clk_smd_rpm_##_prefix##_active = { \ .rpm_res_type = (type), \ .rpm_clk_id = (r_id), \ .active_only = true, \ .rpm_key = (key), \ .branch = true, \ - .peer = &_platform##_##_prefix##_name, \ + .peer = &clk_smd_rpm_##_prefix##_name, \ .rate = (r), \ .hw.init = &(struct clk_init_data){ \ .ops = &clk_smd_rpm_branch_ops, \ @@ -105,54 +105,52 @@ }, \ } -#define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, \ - r, key) \ - __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_platform, /* empty */, \ +#define __DEFINE_CLK_SMD_RPM_BRANCH(_name, _active, type, r_id, r, key) \ + __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(/* empty */, \ _name, _active, type, r_id, r, key) -#define DEFINE_CLK_SMD_RPM(_platform, _name, type, r_id) \ - __DEFINE_CLK_SMD_RPM(_platform, _name##_clk, _name##_a_clk, \ +#define DEFINE_CLK_SMD_RPM(_name, type, r_id) \ + __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \ type, r_id, QCOM_RPM_SMD_KEY_RATE) -#define DEFINE_CLK_SMD_RPM_BUS(_platform, _name, r_id) \ - __DEFINE_CLK_SMD_RPM_PREFIX(_platform, bus_##r_id##_, \ +#define DEFINE_CLK_SMD_RPM_BUS(_name, r_id) \ + __DEFINE_CLK_SMD_RPM_PREFIX(bus_##r_id##_, \ _name##_clk, _name##_a_clk, QCOM_SMD_RPM_BUS_CLK, r_id, \ QCOM_RPM_SMD_KEY_RATE) -#define DEFINE_CLK_SMD_RPM_CLK_SRC(_platform, _name, type, r_id) \ - __DEFINE_CLK_SMD_RPM(_platform, \ +#define DEFINE_CLK_SMD_RPM_CLK_SRC(_name, type, r_id) \ + __DEFINE_CLK_SMD_RPM( \ _name##_clk_src, _name##_a_clk_src, \ type, r_id, QCOM_RPM_SMD_KEY_RATE) -#define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, type, r_id, r) \ - __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_platform, branch_, \ +#define DEFINE_CLK_SMD_RPM_BRANCH(_name, type, r_id, r) \ + __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \ _name##_clk, _name##_a_clk, \ type, r_id, r, QCOM_RPM_SMD_KEY_ENABLE) -#define DEFINE_CLK_SMD_RPM_BRANCH_A(_platform, _name, type, r_id, r) \ - __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_platform, branch_, \ +#define DEFINE_CLK_SMD_RPM_BRANCH_A(_name, type, r_id, r) \ + __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(branch_, \ _name, _name##_a, type, \ r_id, r, QCOM_RPM_SMD_KEY_ENABLE) -#define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, type, r_id) \ - __DEFINE_CLK_SMD_RPM(_platform, _name##_clk, _name##_a_clk, \ +#define DEFINE_CLK_SMD_RPM_QDSS(_name, type, r_id) \ + __DEFINE_CLK_SMD_RPM(_name##_clk, _name##_a_clk, \ type, r_id, QCOM_RPM_SMD_KEY_STATE) -#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, r_id, r) \ - __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _name##_a, \ +#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r) \ + __DEFINE_CLK_SMD_RPM_BRANCH(_name, _name##_a, \ QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ QCOM_RPM_KEY_SOFTWARE_ENABLE) -#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(_platform, _prefix, _name, r_id, r) \ - __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_platform, _prefix, \ +#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(_prefix, _name, r_id, r) \ + __DEFINE_CLK_SMD_RPM_BRANCH_PREFIX(_prefix, \ _name, _name##_a, \ QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ QCOM_RPM_KEY_SOFTWARE_ENABLE) -#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, r_id, r) \ - DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, r_id, r); \ - __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name##_pin, \ - _name##_a##_pin, \ +#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_name, r_id, r) \ + DEFINE_CLK_SMD_RPM_XO_BUFFER(_name, r_id, r); \ + __DEFINE_CLK_SMD_RPM_BRANCH(_name##_pin, _name##_a##_pin, \ QCOM_SMD_RPM_CLK_BUF_A, r_id, r, \ QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY) @@ -440,102 +438,102 @@ static const struct clk_ops clk_smd_rpm_branch_ops = { .recalc_rate = clk_smd_rpm_recalc_rate, }; -DEFINE_CLK_SMD_RPM_BRANCH_A(sdm660, bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000); -DEFINE_CLK_SMD_RPM_BRANCH(sm6125, qdss, QCOM_SMD_RPM_MISC_CLK, 1, 19200000); -DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss, QCOM_SMD_RPM_MISC_CLK, 1); -DEFINE_CLK_SMD_RPM_BRANCH_A(sm6375, bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1); +DEFINE_CLK_SMD_RPM_BRANCH_A(bi_tcxo, QCOM_SMD_RPM_MISC_CLK, 0, 19200000); +DEFINE_CLK_SMD_RPM_BRANCH(qdss, QCOM_SMD_RPM_MISC_CLK, 1, 19200000); +DEFINE_CLK_SMD_RPM_QDSS(qdss, QCOM_SMD_RPM_MISC_CLK, 1); +DEFINE_CLK_SMD_RPM_BRANCH_A(bimc_freq_log, QCOM_SMD_RPM_MISC_CLK, 4, 1); -DEFINE_CLK_SMD_RPM_BRANCH(msm8992, mss_cfg_ahb, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000); +DEFINE_CLK_SMD_RPM_BRANCH(mss_cfg_ahb, QCOM_SMD_RPM_MCFG_CLK, 0, 19200000); -DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1, 1000); -DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); -DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2); +DEFINE_CLK_SMD_RPM_BRANCH(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1, 1000); +DEFINE_CLK_SMD_RPM_BRANCH(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2, 1000); +DEFINE_CLK_SMD_RPM(aggre1_noc, QCOM_SMD_RPM_AGGR_CLK, 1); +DEFINE_CLK_SMD_RPM(aggre2_noc, QCOM_SMD_RPM_AGGR_CLK, 2); -DEFINE_CLK_SMD_RPM_BUS(msm8916, pcnoc, 0); -DEFINE_CLK_SMD_RPM_BUS(msm8916, snoc, 1); -DEFINE_CLK_SMD_RPM_BUS(msm8936, sysmmnoc, 2); -DEFINE_CLK_SMD_RPM_BUS(msm8974, cnoc, 2); -DEFINE_CLK_SMD_RPM_BUS(msm8974, mmssnoc_ahb, 3); -DEFINE_CLK_SMD_RPM_BUS(sm6125, snoc_periph, 0); -DEFINE_CLK_SMD_RPM_BUS(sm6125, cnoc, 1); -DEFINE_CLK_SMD_RPM_BUS(sm6125, snoc, 2); -DEFINE_CLK_SMD_RPM_BUS(sm6125, snoc_lpass, 5); +DEFINE_CLK_SMD_RPM_BUS(pcnoc, 0); +DEFINE_CLK_SMD_RPM_BUS(snoc, 1); +DEFINE_CLK_SMD_RPM_BUS(sysmmnoc, 2); +DEFINE_CLK_SMD_RPM_BUS(cnoc, 2); +DEFINE_CLK_SMD_RPM_BUS(mmssnoc_ahb, 3); +DEFINE_CLK_SMD_RPM_BUS(snoc_periph, 0); +DEFINE_CLK_SMD_RPM_BUS(cnoc, 1); +DEFINE_CLK_SMD_RPM_BUS(snoc, 2); +DEFINE_CLK_SMD_RPM_BUS(snoc_lpass, 5); -DEFINE_CLK_SMD_RPM(msm8916, bimc, QCOM_SMD_RPM_MEM_CLK, 0); -DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc, QCOM_SMD_RPM_MEM_CLK, 1); -DEFINE_CLK_SMD_RPM_CLK_SRC(msm8974, gfx3d, QCOM_SMD_RPM_MEM_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8974, ocmemgx, QCOM_SMD_RPM_MEM_CLK, 2); -DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu, QCOM_SMD_RPM_MEM_CLK, 2); +DEFINE_CLK_SMD_RPM(bimc, QCOM_SMD_RPM_MEM_CLK, 0); +DEFINE_CLK_SMD_RPM(cpuss_gnoc, QCOM_SMD_RPM_MEM_CLK, 1); +DEFINE_CLK_SMD_RPM_CLK_SRC(gfx3d, QCOM_SMD_RPM_MEM_CLK, 1); +DEFINE_CLK_SMD_RPM(ocmemgx, QCOM_SMD_RPM_MEM_CLK, 2); +DEFINE_CLK_SMD_RPM(bimc_gpu, QCOM_SMD_RPM_MEM_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8992, ce1, QCOM_SMD_RPM_CE_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8992, ce2, QCOM_SMD_RPM_CE_CLK, 1); -DEFINE_CLK_SMD_RPM(msm8994, ce3, QCOM_SMD_RPM_CE_CLK, 2); +DEFINE_CLK_SMD_RPM(ce1, QCOM_SMD_RPM_CE_CLK, 0); +DEFINE_CLK_SMD_RPM(ce2, QCOM_SMD_RPM_CE_CLK, 1); +DEFINE_CLK_SMD_RPM(ce3, QCOM_SMD_RPM_CE_CLK, 2); -DEFINE_CLK_SMD_RPM(msm8976, ipa, QCOM_SMD_RPM_IPA_CLK, 0); +DEFINE_CLK_SMD_RPM(ipa, QCOM_SMD_RPM_IPA_CLK, 0); -DEFINE_CLK_SMD_RPM(qcm2290, hwkm, QCOM_SMD_RPM_HWKM_CLK, 0); +DEFINE_CLK_SMD_RPM(hwkm, QCOM_SMD_RPM_HWKM_CLK, 0); -DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm, QCOM_SMD_RPM_MMAXI_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6125, mmnrt, QCOM_SMD_RPM_MMAXI_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6125, mmrt, QCOM_SMD_RPM_MMAXI_CLK, 1); +DEFINE_CLK_SMD_RPM(mmssnoc_axi_rpm, QCOM_SMD_RPM_MMAXI_CLK, 0); +DEFINE_CLK_SMD_RPM(mmnrt, QCOM_SMD_RPM_MMAXI_CLK, 0); +DEFINE_CLK_SMD_RPM(mmrt, QCOM_SMD_RPM_MMAXI_CLK, 1); -DEFINE_CLK_SMD_RPM(qcm2290, pka, QCOM_SMD_RPM_PKA_CLK, 0); +DEFINE_CLK_SMD_RPM(pka, QCOM_SMD_RPM_PKA_CLK, 0); -DEFINE_CLK_SMD_RPM(qcs404, qpic, QCOM_SMD_RPM_QPIC_CLK, 0); +DEFINE_CLK_SMD_RPM(qpic, QCOM_SMD_RPM_QPIC_CLK, 0); -DEFINE_CLK_SMD_RPM(sm6125, qup, QCOM_SMD_RPM_QUP_CLK, 0); +DEFINE_CLK_SMD_RPM(qup, QCOM_SMD_RPM_QUP_CLK, 0); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1, 1, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2, 2, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk1, 1, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk2, 2, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3, 3, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1, 4, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2, 5, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3, 6, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk, 8, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk1, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(bb_clk2, 2, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk1, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk2, 2, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk3, 3, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk1, 4, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk2, 5, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(rf_clk3, 6, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(ln_bb_clk, 8, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(qcm2290, 38m4_, rf_clk3, 6, 38400000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PREFIX(38m4_, rf_clk3, 6, 38400000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0, 1, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1, 2, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0, 4, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1, 5, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2, 6, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d0, 1, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_d1, 2, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a0, 4, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a1, 5, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(cxo_a2, 6, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, 7, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, 11, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, 12, 19200000); -DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, 13, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(diff_clk, 7, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk1, 11, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk2, 12, 19200000); +DEFINE_CLK_SMD_RPM_XO_BUFFER(div_clk3, 13, 19200000); static struct clk_smd_rpm *msm8909_clks[] = { - [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, - [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, - [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, - [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, - [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, - [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, - [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, - [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, - [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, - [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, - [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, - [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, - [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, - [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, - [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, - [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, + [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, + [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, + [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, + [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, + [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, + [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, + [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, + [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, + [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, + [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, + [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, + [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, + [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, + [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, + [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, + [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, }; static const struct rpm_smd_clk_desc rpm_clk_msm8909 = { @@ -544,30 +542,30 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8909 = { }; static struct clk_smd_rpm *msm8916_clks[] = { - [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, - [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, - [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, - [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, - [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, - [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, - [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, - [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, - [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, - [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, - [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, - [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, - [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, - [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, - [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, + [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, + [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, + [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, + [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, + [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, + [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, + [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, + [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, + [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, + [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, + [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, + [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, + [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, + [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, }; static const struct rpm_smd_clk_desc rpm_clk_msm8916 = { @@ -576,32 +574,32 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8916 = { }; static struct clk_smd_rpm *msm8936_clks[] = { - [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_SYSMMNOC_CLK] = &msm8936_bus_2_sysmmnoc_clk, - [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_bus_2_sysmmnoc_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, - [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, - [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, - [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, - [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, - [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, - [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, - [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, - [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, - [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, - [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, - [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, - [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, - [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, - [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, + [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, + [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, + [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, + [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, + [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, + [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, + [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, + [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, + [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, + [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, + [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, + [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, + [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, + [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, + [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, + [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, }; static const struct rpm_smd_clk_desc rpm_clk_msm8936 = { @@ -610,48 +608,48 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8936 = { }; static struct clk_smd_rpm *msm8974_clks[] = { - [RPM_SMD_PNOC_CLK] = &msm8916_bus_0_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, - [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_bus_3_mmssnoc_ahb_clk, - [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_bus_3_mmssnoc_ahb_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src, - [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, - [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, - [RPM_SMD_CXO_D0] = &msm8974_cxo_d0, - [RPM_SMD_CXO_D0_A] = &msm8974_cxo_d0_a, - [RPM_SMD_CXO_D1] = &msm8974_cxo_d1, - [RPM_SMD_CXO_D1_A] = &msm8974_cxo_d1_a, - [RPM_SMD_CXO_A0] = &msm8974_cxo_a0, - [RPM_SMD_CXO_A0_A] = &msm8974_cxo_a0_a, - [RPM_SMD_CXO_A1] = &msm8974_cxo_a1, - [RPM_SMD_CXO_A1_A] = &msm8974_cxo_a1_a, - [RPM_SMD_CXO_A2] = &msm8974_cxo_a2, - [RPM_SMD_CXO_A2_A] = &msm8974_cxo_a2_a, - [RPM_SMD_DIFF_CLK] = &msm8974_diff_clk, - [RPM_SMD_DIFF_A_CLK] = &msm8974_diff_clk_a, - [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, - [RPM_SMD_DIV_A_CLK1] = &msm8974_div_clk1_a, - [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8974_div_clk2_a, - [RPM_SMD_CXO_D0_PIN] = &msm8974_cxo_d0_pin, - [RPM_SMD_CXO_D0_A_PIN] = &msm8974_cxo_d0_a_pin, - [RPM_SMD_CXO_D1_PIN] = &msm8974_cxo_d1_pin, - [RPM_SMD_CXO_D1_A_PIN] = &msm8974_cxo_d1_a_pin, - [RPM_SMD_CXO_A0_PIN] = &msm8974_cxo_a0_pin, - [RPM_SMD_CXO_A0_A_PIN] = &msm8974_cxo_a0_a_pin, - [RPM_SMD_CXO_A1_PIN] = &msm8974_cxo_a1_pin, - [RPM_SMD_CXO_A1_A_PIN] = &msm8974_cxo_a1_a_pin, - [RPM_SMD_CXO_A2_PIN] = &msm8974_cxo_a2_pin, - [RPM_SMD_CXO_A2_A_PIN] = &msm8974_cxo_a2_a_pin, + [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, + [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, + [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, + [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, + [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, + [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, + [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, + [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, + [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, + [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, + [RPM_SMD_CXO_D0] = &clk_smd_rpm_cxo_d0, + [RPM_SMD_CXO_D0_A] = &clk_smd_rpm_cxo_d0_a, + [RPM_SMD_CXO_D1] = &clk_smd_rpm_cxo_d1, + [RPM_SMD_CXO_D1_A] = &clk_smd_rpm_cxo_d1_a, + [RPM_SMD_CXO_A0] = &clk_smd_rpm_cxo_a0, + [RPM_SMD_CXO_A0_A] = &clk_smd_rpm_cxo_a0_a, + [RPM_SMD_CXO_A1] = &clk_smd_rpm_cxo_a1, + [RPM_SMD_CXO_A1_A] = &clk_smd_rpm_cxo_a1_a, + [RPM_SMD_CXO_A2] = &clk_smd_rpm_cxo_a2, + [RPM_SMD_CXO_A2_A] = &clk_smd_rpm_cxo_a2_a, + [RPM_SMD_DIFF_CLK] = &clk_smd_rpm_diff_clk, + [RPM_SMD_DIFF_A_CLK] = &clk_smd_rpm_diff_clk_a, + [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, + [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, + [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, + [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, + [RPM_SMD_CXO_D0_PIN] = &clk_smd_rpm_cxo_d0_pin, + [RPM_SMD_CXO_D0_A_PIN] = &clk_smd_rpm_cxo_d0_a_pin, + [RPM_SMD_CXO_D1_PIN] = &clk_smd_rpm_cxo_d1_pin, + [RPM_SMD_CXO_D1_A_PIN] = &clk_smd_rpm_cxo_d1_a_pin, + [RPM_SMD_CXO_A0_PIN] = &clk_smd_rpm_cxo_a0_pin, + [RPM_SMD_CXO_A0_A_PIN] = &clk_smd_rpm_cxo_a0_a_pin, + [RPM_SMD_CXO_A1_PIN] = &clk_smd_rpm_cxo_a1_pin, + [RPM_SMD_CXO_A1_A_PIN] = &clk_smd_rpm_cxo_a1_a_pin, + [RPM_SMD_CXO_A2_PIN] = &clk_smd_rpm_cxo_a2_pin, + [RPM_SMD_CXO_A2_A_PIN] = &clk_smd_rpm_cxo_a2_a_pin, }; static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { @@ -660,32 +658,32 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8974 = { }; static struct clk_smd_rpm *msm8976_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_SYSMMNOC_CLK] = &msm8936_bus_2_sysmmnoc_clk, - [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_bus_2_sysmmnoc_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, - [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, - [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, - [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, - [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, - [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, - [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, - [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, - [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, - [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, - [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8974_div_clk2_a, - [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, - [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, + [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, + [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, + [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, + [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, + [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, + [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, + [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, + [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, + [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, + [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, + [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, + [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, + [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, + [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, + [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, + [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, }; static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { @@ -694,56 +692,56 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8976 = { }; static struct clk_smd_rpm *msm8992_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_PNOC_CLK] = &msm8916_bus_0_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, - [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, - [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, - [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src, - [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src, - [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, - [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, - [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, - [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, - [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, - [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, - [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, - [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, - [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, - [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, - [RPM_SMD_DIV_A_CLK1] = &msm8974_div_clk1_a, - [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8974_div_clk2_a, - [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3, - [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, - [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, - [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, - [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, - [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_clk_a, - [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_bus_3_mmssnoc_ahb_clk, - [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_bus_3_mmssnoc_ahb_a_clk, - [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_branch_mss_cfg_ahb_clk, - [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_branch_mss_cfg_ahb_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, - [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, - [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, - [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, - [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, - [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, - [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, - [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, - [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, - [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk, - [RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk, + [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, + [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, + [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, + [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, + [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, + [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, + [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, + [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, + [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, + [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, + [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, + [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, + [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, + [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, + [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, + [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, + [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, + [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, + [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, + [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, + [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, + [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, + [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, + [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, + [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, + [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, + [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, + [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, + [RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk, + [RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, + [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, + [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, + [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, + [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, + [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, + [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, + [RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk, + [RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk, }; static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { @@ -752,58 +750,58 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8992 = { }; static struct clk_smd_rpm *msm8994_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_PNOC_CLK] = &msm8916_bus_0_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, - [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk, - [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, - [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src, - [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src, - [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, - [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, - [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, - [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, - [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, - [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, - [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, - [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, - [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, - [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, - [RPM_SMD_DIV_A_CLK1] = &msm8974_div_clk1_a, - [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8974_div_clk2_a, - [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3, - [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, - [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, - [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, - [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, - [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_clk_a, - [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_bus_3_mmssnoc_ahb_clk, - [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_bus_3_mmssnoc_ahb_a_clk, - [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_branch_mss_cfg_ahb_clk, - [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_branch_mss_cfg_ahb_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, - [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, - [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, - [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, - [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, - [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, - [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, - [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, - [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, - [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk, - [RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk, - [RPM_SMD_CE3_CLK] = &msm8994_ce3_clk, - [RPM_SMD_CE3_A_CLK] = &msm8994_ce3_a_clk, + [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, + [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, + [RPM_SMD_OCMEMGX_CLK] = &clk_smd_rpm_ocmemgx_clk, + [RPM_SMD_OCMEMGX_A_CLK] = &clk_smd_rpm_ocmemgx_a_clk, + [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, + [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, + [RPM_SMD_GFX3D_CLK_SRC] = &clk_smd_rpm_gfx3d_clk_src, + [RPM_SMD_GFX3D_A_CLK_SRC] = &clk_smd_rpm_gfx3d_a_clk_src, + [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, + [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, + [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, + [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, + [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, + [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, + [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, + [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, + [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, + [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, + [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, + [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, + [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, + [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, + [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, + [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, + [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, + [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, + [RPM_SMD_MMSSNOC_AHB_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_clk, + [RPM_SMD_MMSSNOC_AHB_A_CLK] = &clk_smd_rpm_bus_3_mmssnoc_ahb_a_clk, + [RPM_SMD_MSS_CFG_AHB_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_clk, + [RPM_SMD_MSS_CFG_AHB_A_CLK] = &clk_smd_rpm_branch_mss_cfg_ahb_a_clk, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, + [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, + [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, + [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, + [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, + [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, + [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, + [RPM_SMD_CE2_CLK] = &clk_smd_rpm_ce2_clk, + [RPM_SMD_CE2_A_CLK] = &clk_smd_rpm_ce2_a_clk, + [RPM_SMD_CE3_CLK] = &clk_smd_rpm_ce3_clk, + [RPM_SMD_CE3_A_CLK] = &clk_smd_rpm_ce3_a_clk, }; static const struct rpm_smd_clk_desc rpm_clk_msm8994 = { @@ -812,50 +810,50 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8994 = { }; static struct clk_smd_rpm *msm8996_clks[] = { - [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, - [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk, - [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, - [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, - [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, - [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, - [RPM_SMD_AGGR1_NOC_CLK] = &msm8996_branch_aggre1_noc_clk, - [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8996_branch_aggre1_noc_a_clk, - [RPM_SMD_AGGR2_NOC_CLK] = &msm8996_branch_aggre2_noc_clk, - [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8996_branch_aggre2_noc_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, - [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, - [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, - [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, - [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, - [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, - [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, - [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, - [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_clk_a, - [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, - [RPM_SMD_DIV_A_CLK1] = &msm8974_div_clk1_a, - [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8974_div_clk2_a, - [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3, - [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, - [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, - [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, - [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, - [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, - [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, - [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, - [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, - [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, + [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, + [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, + [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, + [RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, + [RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, + [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, + [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, + [RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_branch_aggre1_noc_clk, + [RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_branch_aggre1_noc_a_clk, + [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_branch_aggre2_noc_clk, + [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_branch_aggre2_noc_a_clk, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, + [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, + [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, + [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, + [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, + [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, + [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, + [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, + [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, + [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, + [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, + [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, + [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, + [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, + [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, + [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, + [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, + [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, + [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, + [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, + [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, + [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, }; static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { @@ -864,26 +862,26 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8996 = { }; static struct clk_smd_rpm *qcs404_clks[] = { - [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, - [RPM_SMD_PNOC_CLK] = &msm8916_bus_0_pcnoc_clk, - [RPM_SMD_PNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk, - [RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk, - [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, - [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk, - [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, - [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, - [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, - [RPM_SMD_LN_BB_CLK] = &qcs404_ln_bb_clk, - [RPM_SMD_LN_BB_A_CLK] = &qcs404_ln_bb_clk_a, - [RPM_SMD_LN_BB_CLK_PIN] = &qcs404_ln_bb_clk_pin, - [RPM_SMD_LN_BB_A_CLK_PIN] = &qcs404_ln_bb_clk_a_pin, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, + [RPM_SMD_PNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, + [RPM_SMD_PNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, + [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, + [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, + [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, + [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, + [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, + [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, + [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk, + [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk_a, + [RPM_SMD_LN_BB_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_pin, + [RPM_SMD_LN_BB_A_CLK_PIN] = &clk_smd_rpm_ln_bb_clk_a_pin, }; static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { @@ -892,58 +890,58 @@ static const struct rpm_smd_clk_desc rpm_clk_qcs404 = { }; static struct clk_smd_rpm *msm8998_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, - [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, - [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, - [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, - [RPM_SMD_DIV_A_CLK1] = &msm8974_div_clk1_a, - [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8974_div_clk2_a, - [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3, - [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a, - [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, - [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, - [RPM_SMD_LN_BB_CLK1] = &msm8998_ln_bb_clk1, - [RPM_SMD_LN_BB_CLK1_A] = &msm8998_ln_bb_clk1_a, - [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2, - [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a, - [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3, - [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a, - [RPM_SMD_LN_BB_CLK1_PIN] = &msm8998_ln_bb_clk1_pin, - [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8998_ln_bb_clk1_a_pin, - [RPM_SMD_LN_BB_CLK2_PIN] = &msm8998_ln_bb_clk2_pin, - [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8998_ln_bb_clk2_a_pin, - [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin, - [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin, - [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, - [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk, - [RPM_SMD_AGGR1_NOC_CLK] = &msm8998_aggre1_noc_clk, - [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8998_aggre1_noc_a_clk, - [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk, - [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, - [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, - [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, - [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_RF_CLK3] = &msm8998_rf_clk3, - [RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a, - [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, - [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, - [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, - [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, - [RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin, - [RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin, + [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, + [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, + [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, + [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, + [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, + [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, + [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, + [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, + [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, + [RPM_SMD_DIV_CLK3] = &clk_smd_rpm_div_clk3, + [RPM_SMD_DIV_A_CLK3] = &clk_smd_rpm_div_clk3_a, + [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, + [RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1, + [RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a, + [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, + [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, + [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, + [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, + [RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin, + [RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin, + [RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin, + [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin, + [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin, + [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin, + [RPM_SMD_MMAXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, + [RPM_SMD_MMAXI_A_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, + [RPM_SMD_AGGR1_NOC_CLK] = &clk_smd_rpm_aggre1_noc_clk, + [RPM_SMD_AGGR1_NOC_A_CLK] = &clk_smd_rpm_aggre1_noc_a_clk, + [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk, + [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, + [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, + [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, + [RPM_SMD_RF_CLK3] = &clk_smd_rpm_rf_clk3, + [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_rf_clk3_a, + [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, + [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, + [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, + [RPM_SMD_RF_CLK3_PIN] = &clk_smd_rpm_rf_clk3_pin, + [RPM_SMD_RF_CLK3_A_PIN] = &clk_smd_rpm_rf_clk3_a_pin, }; static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { @@ -952,44 +950,44 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8998 = { }; static struct clk_smd_rpm *sdm660_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, - [RPM_SMD_CNOC_CLK] = &msm8974_bus_2_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &msm8974_bus_2_cnoc_a_clk, - [RPM_SMD_CNOC_PERIPH_CLK] = &msm8916_bus_0_pcnoc_clk, - [RPM_SMD_CNOC_PERIPH_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_MMSSNOC_AXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk, - [RPM_SMD_MMSSNOC_AXI_CLK_A] = &msm8996_mmssnoc_axi_rpm_a_clk, - [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, - [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, - [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, - [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, - [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk, - [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, - [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, - [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1, - [RPM_SMD_DIV_A_CLK1] = &msm8974_div_clk1_a, - [RPM_SMD_LN_BB_CLK] = &msm8998_ln_bb_clk1, - [RPM_SMD_LN_BB_A_CLK] = &msm8998_ln_bb_clk1_a, - [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2, - [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a, - [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3, - [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a, - [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, - [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, - [RPM_SMD_LN_BB_CLK1_PIN] = &msm8998_ln_bb_clk1_pin, - [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8998_ln_bb_clk1_a_pin, - [RPM_SMD_LN_BB_CLK2_PIN] = &msm8998_ln_bb_clk2_pin, - [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8998_ln_bb_clk2_a_pin, - [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin, - [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin, + [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, + [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, + [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_2_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_2_cnoc_a_clk, + [RPM_SMD_CNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, + [RPM_SMD_CNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, + [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, + [RPM_SMD_MMSSNOC_AXI_CLK] = &clk_smd_rpm_mmssnoc_axi_rpm_clk, + [RPM_SMD_MMSSNOC_AXI_CLK_A] = &clk_smd_rpm_mmssnoc_axi_rpm_a_clk, + [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, + [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, + [RPM_SMD_AGGR2_NOC_CLK] = &clk_smd_rpm_aggre2_noc_clk, + [RPM_SMD_AGGR2_NOC_A_CLK] = &clk_smd_rpm_aggre2_noc_a_clk, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, + [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, + [RPM_SMD_DIV_CLK1] = &clk_smd_rpm_div_clk1, + [RPM_SMD_DIV_A_CLK1] = &clk_smd_rpm_div_clk1_a, + [RPM_SMD_LN_BB_CLK] = &clk_smd_rpm_ln_bb_clk1, + [RPM_SMD_LN_BB_A_CLK] = &clk_smd_rpm_ln_bb_clk1_a, + [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, + [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, + [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, + [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, + [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, + [RPM_SMD_LN_BB_CLK1_PIN] = &clk_smd_rpm_ln_bb_clk1_pin, + [RPM_SMD_LN_BB_CLK1_A_PIN] = &clk_smd_rpm_ln_bb_clk1_a_pin, + [RPM_SMD_LN_BB_CLK2_PIN] = &clk_smd_rpm_ln_bb_clk2_pin, + [RPM_SMD_LN_BB_CLK2_A_PIN] = &clk_smd_rpm_ln_bb_clk2_a_pin, + [RPM_SMD_LN_BB_CLK3_PIN] = &clk_smd_rpm_ln_bb_clk3_pin, + [RPM_SMD_LN_BB_CLK3_A_PIN] = &clk_smd_rpm_ln_bb_clk3_a_pin, }; static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { @@ -998,20 +996,20 @@ static const struct rpm_smd_clk_desc rpm_clk_sdm660 = { }; static struct clk_smd_rpm *mdm9607_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, - [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, - [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, - [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, - [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, - [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, + [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, + [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, + [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, + [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, + [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, + [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, + [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, + [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, + [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, }; static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = { @@ -1020,34 +1018,34 @@ static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = { }; static struct clk_smd_rpm *msm8953_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_PCNOC_CLK] = &msm8916_bus_0_pcnoc_clk, - [RPM_SMD_PCNOC_A_CLK] = &msm8916_bus_0_pcnoc_a_clk, - [RPM_SMD_SNOC_CLK] = &msm8916_bus_1_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &msm8916_bus_1_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, - [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, - [RPM_SMD_SYSMMNOC_CLK] = &msm8936_bus_2_sysmmnoc_clk, - [RPM_SMD_SYSMMNOC_A_CLK] = &msm8936_bus_2_sysmmnoc_a_clk, - [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk, - [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1, - [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a, - [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2, - [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a, - [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, - [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_RF_CLK3] = &qcs404_ln_bb_clk, - [RPM_SMD_RF_CLK3_A] = &qcs404_ln_bb_clk_a, - [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2, - [RPM_SMD_DIV_A_CLK2] = &msm8974_div_clk2_a, - [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin, - [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin, - [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin, - [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin, + [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, + [RPM_SMD_PCNOC_CLK] = &clk_smd_rpm_bus_0_pcnoc_clk, + [RPM_SMD_PCNOC_A_CLK] = &clk_smd_rpm_bus_0_pcnoc_a_clk, + [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_1_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_1_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, + [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, + [RPM_SMD_SYSMMNOC_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_clk, + [RPM_SMD_SYSMMNOC_A_CLK] = &clk_smd_rpm_bus_2_sysmmnoc_a_clk, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_qdss_a_clk, + [RPM_SMD_BB_CLK1] = &clk_smd_rpm_bb_clk1, + [RPM_SMD_BB_CLK1_A] = &clk_smd_rpm_bb_clk1_a, + [RPM_SMD_BB_CLK2] = &clk_smd_rpm_bb_clk2, + [RPM_SMD_BB_CLK2_A] = &clk_smd_rpm_bb_clk2_a, + [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, + [RPM_SMD_RF_CLK3] = &clk_smd_rpm_ln_bb_clk, + [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_ln_bb_clk_a, + [RPM_SMD_DIV_CLK2] = &clk_smd_rpm_div_clk2, + [RPM_SMD_DIV_A_CLK2] = &clk_smd_rpm_div_clk2_a, + [RPM_SMD_BB_CLK1_PIN] = &clk_smd_rpm_bb_clk1_pin, + [RPM_SMD_BB_CLK1_A_PIN] = &clk_smd_rpm_bb_clk1_a_pin, + [RPM_SMD_BB_CLK2_PIN] = &clk_smd_rpm_bb_clk2_pin, + [RPM_SMD_BB_CLK2_A_PIN] = &clk_smd_rpm_bb_clk2_a_pin, }; static const struct rpm_smd_clk_desc rpm_clk_msm8953 = { @@ -1056,40 +1054,40 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8953 = { }; static struct clk_smd_rpm *sm6125_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &sm6125_bus_2_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &sm6125_bus_2_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_QDSS_CLK] = &sm6125_branch_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &sm6125_branch_qdss_a_clk, - [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, - [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, - [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_CNOC_CLK] = &sm6125_bus_1_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &sm6125_bus_1_cnoc_a_clk, - [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, - [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, - [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, - [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, - [RPM_SMD_LN_BB_CLK1] = &msm8998_ln_bb_clk1, - [RPM_SMD_LN_BB_CLK1_A] = &msm8998_ln_bb_clk1_a, - [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2, - [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a, - [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3, - [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a, - [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, - [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk, - [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk, - [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, - [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, - [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, - [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_bus_0_snoc_periph_clk, - [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_bus_0_snoc_periph_a_clk, - [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_bus_5_snoc_lpass_clk, - [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_bus_5_snoc_lpass_a_clk, + [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, + [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, + [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, + [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, + [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, + [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, + [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, + [RPM_SMD_LN_BB_CLK1] = &clk_smd_rpm_ln_bb_clk1, + [RPM_SMD_LN_BB_CLK1_A] = &clk_smd_rpm_ln_bb_clk1_a, + [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, + [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, + [RPM_SMD_LN_BB_CLK3] = &clk_smd_rpm_ln_bb_clk3, + [RPM_SMD_LN_BB_CLK3_A] = &clk_smd_rpm_ln_bb_clk3_a, + [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, + [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, + [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, + [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, + [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, + [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, + [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, + [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, + [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, + [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, }; static const struct rpm_smd_clk_desc rpm_clk_sm6125 = { @@ -1099,38 +1097,38 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6125 = { /* SM6115 */ static struct clk_smd_rpm *sm6115_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &sm6125_bus_2_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &sm6125_bus_2_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_QDSS_CLK] = &sm6125_branch_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &sm6125_branch_qdss_a_clk, - [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1, - [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a, - [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2, - [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a, - [RPM_SMD_CNOC_CLK] = &sm6125_bus_1_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &sm6125_bus_1_cnoc_a_clk, - [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, - [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, - [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, - [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, - [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, - [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk, - [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk, - [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, - [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, - [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, - [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_bus_0_snoc_periph_clk, - [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_bus_0_snoc_periph_a_clk, - [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_bus_5_snoc_lpass_clk, - [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_bus_5_snoc_lpass_a_clk, - [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin, - [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin, - [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin, - [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin, + [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, + [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, + [RPM_SMD_RF_CLK1] = &clk_smd_rpm_rf_clk1, + [RPM_SMD_RF_CLK1_A] = &clk_smd_rpm_rf_clk1_a, + [RPM_SMD_RF_CLK2] = &clk_smd_rpm_rf_clk2, + [RPM_SMD_RF_CLK2_A] = &clk_smd_rpm_rf_clk2_a, + [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, + [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, + [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, + [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, + [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, + [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, + [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, + [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, + [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, + [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, + [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, + [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, + [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, + [RPM_SMD_RF_CLK1_PIN] = &clk_smd_rpm_rf_clk1_pin, + [RPM_SMD_RF_CLK1_A_PIN] = &clk_smd_rpm_rf_clk1_a_pin, + [RPM_SMD_RF_CLK2_PIN] = &clk_smd_rpm_rf_clk2_pin, + [RPM_SMD_RF_CLK2_A_PIN] = &clk_smd_rpm_rf_clk2_a_pin, }; static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { @@ -1139,35 +1137,35 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6115 = { }; static struct clk_smd_rpm *sm6375_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &sm6125_bus_2_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &sm6125_bus_2_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_QDSS_CLK] = &sm6125_branch_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &sm6125_branch_qdss_a_clk, - [RPM_SMD_CNOC_CLK] = &sm6125_bus_1_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &sm6125_bus_1_cnoc_a_clk, - [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, - [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, - [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, - [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk, - [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk, - [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, - [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, - [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, - [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_bus_0_snoc_periph_clk, - [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_bus_0_snoc_periph_a_clk, - [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_bus_5_snoc_lpass_clk, - [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_bus_5_snoc_lpass_a_clk, - [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, - [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, - [RPM_SMD_HWKM_CLK] = &qcm2290_hwkm_clk, - [RPM_SMD_HWKM_A_CLK] = &qcm2290_hwkm_a_clk, - [RPM_SMD_PKA_CLK] = &qcm2290_pka_clk, - [RPM_SMD_PKA_A_CLK] = &qcm2290_pka_a_clk, - [RPM_SMD_BIMC_FREQ_LOG] = &sm6375_branch_bimc_freq_log, + [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, + [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, + [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, + [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, + [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, + [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, + [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, + [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, + [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, + [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, + [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, + [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, + [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, + [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, + [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, + [RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk, + [RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk, + [RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk, + [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk, + [RPM_SMD_BIMC_FREQ_LOG] = &clk_smd_rpm_branch_bimc_freq_log, }; static const struct rpm_smd_clk_desc rpm_clk_sm6375 = { @@ -1176,44 +1174,44 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6375 = { }; static struct clk_smd_rpm *qcm2290_clks[] = { - [RPM_SMD_XO_CLK_SRC] = &sdm660_branch_bi_tcxo, - [RPM_SMD_XO_A_CLK_SRC] = &sdm660_branch_bi_tcxo_a, - [RPM_SMD_SNOC_CLK] = &sm6125_bus_2_snoc_clk, - [RPM_SMD_SNOC_A_CLK] = &sm6125_bus_2_snoc_a_clk, - [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk, - [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk, - [RPM_SMD_QDSS_CLK] = &sm6125_branch_qdss_clk, - [RPM_SMD_QDSS_A_CLK] = &sm6125_branch_qdss_a_clk, - [RPM_SMD_LN_BB_CLK2] = &msm8998_ln_bb_clk2, - [RPM_SMD_LN_BB_CLK2_A] = &msm8998_ln_bb_clk2_a, - [RPM_SMD_RF_CLK3] = &qcm2290_38m4_rf_clk3, - [RPM_SMD_RF_CLK3_A] = &qcm2290_38m4_rf_clk3_a, - [RPM_SMD_CNOC_CLK] = &sm6125_bus_1_cnoc_clk, - [RPM_SMD_CNOC_A_CLK] = &sm6125_bus_1_cnoc_a_clk, - [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk, - [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk, - [RPM_SMD_QUP_CLK] = &sm6125_qup_clk, - [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk, - [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk, - [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk, - [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk, - [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk, - [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_bus_0_snoc_periph_clk, - [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_bus_0_snoc_periph_a_clk, - [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_bus_5_snoc_lpass_clk, - [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_bus_5_snoc_lpass_a_clk, - [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk, - [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk, - [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk, - [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk, - [RPM_SMD_HWKM_CLK] = &qcm2290_hwkm_clk, - [RPM_SMD_HWKM_A_CLK] = &qcm2290_hwkm_a_clk, - [RPM_SMD_PKA_CLK] = &qcm2290_pka_clk, - [RPM_SMD_PKA_A_CLK] = &qcm2290_pka_a_clk, - [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk, - [RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk, - [RPM_SMD_CPUSS_GNOC_CLK] = &qcm2290_cpuss_gnoc_clk, - [RPM_SMD_CPUSS_GNOC_A_CLK] = &qcm2290_cpuss_gnoc_a_clk, + [RPM_SMD_XO_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo, + [RPM_SMD_XO_A_CLK_SRC] = &clk_smd_rpm_branch_bi_tcxo_a, + [RPM_SMD_SNOC_CLK] = &clk_smd_rpm_bus_2_snoc_clk, + [RPM_SMD_SNOC_A_CLK] = &clk_smd_rpm_bus_2_snoc_a_clk, + [RPM_SMD_BIMC_CLK] = &clk_smd_rpm_bimc_clk, + [RPM_SMD_BIMC_A_CLK] = &clk_smd_rpm_bimc_a_clk, + [RPM_SMD_QDSS_CLK] = &clk_smd_rpm_branch_qdss_clk, + [RPM_SMD_QDSS_A_CLK] = &clk_smd_rpm_branch_qdss_a_clk, + [RPM_SMD_LN_BB_CLK2] = &clk_smd_rpm_ln_bb_clk2, + [RPM_SMD_LN_BB_CLK2_A] = &clk_smd_rpm_ln_bb_clk2_a, + [RPM_SMD_RF_CLK3] = &clk_smd_rpm_38m4_rf_clk3, + [RPM_SMD_RF_CLK3_A] = &clk_smd_rpm_38m4_rf_clk3_a, + [RPM_SMD_CNOC_CLK] = &clk_smd_rpm_bus_1_cnoc_clk, + [RPM_SMD_CNOC_A_CLK] = &clk_smd_rpm_bus_1_cnoc_a_clk, + [RPM_SMD_IPA_CLK] = &clk_smd_rpm_ipa_clk, + [RPM_SMD_IPA_A_CLK] = &clk_smd_rpm_ipa_a_clk, + [RPM_SMD_QUP_CLK] = &clk_smd_rpm_qup_clk, + [RPM_SMD_QUP_A_CLK] = &clk_smd_rpm_qup_a_clk, + [RPM_SMD_MMRT_CLK] = &clk_smd_rpm_mmrt_clk, + [RPM_SMD_MMRT_A_CLK] = &clk_smd_rpm_mmrt_a_clk, + [RPM_SMD_MMNRT_CLK] = &clk_smd_rpm_mmnrt_clk, + [RPM_SMD_MMNRT_A_CLK] = &clk_smd_rpm_mmnrt_a_clk, + [RPM_SMD_SNOC_PERIPH_CLK] = &clk_smd_rpm_bus_0_snoc_periph_clk, + [RPM_SMD_SNOC_PERIPH_A_CLK] = &clk_smd_rpm_bus_0_snoc_periph_a_clk, + [RPM_SMD_SNOC_LPASS_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_clk, + [RPM_SMD_SNOC_LPASS_A_CLK] = &clk_smd_rpm_bus_5_snoc_lpass_a_clk, + [RPM_SMD_CE1_CLK] = &clk_smd_rpm_ce1_clk, + [RPM_SMD_CE1_A_CLK] = &clk_smd_rpm_ce1_a_clk, + [RPM_SMD_QPIC_CLK] = &clk_smd_rpm_qpic_clk, + [RPM_SMD_QPIC_CLK_A] = &clk_smd_rpm_qpic_a_clk, + [RPM_SMD_HWKM_CLK] = &clk_smd_rpm_hwkm_clk, + [RPM_SMD_HWKM_A_CLK] = &clk_smd_rpm_hwkm_a_clk, + [RPM_SMD_PKA_CLK] = &clk_smd_rpm_pka_clk, + [RPM_SMD_PKA_A_CLK] = &clk_smd_rpm_pka_a_clk, + [RPM_SMD_BIMC_GPU_CLK] = &clk_smd_rpm_bimc_gpu_clk, + [RPM_SMD_BIMC_GPU_A_CLK] = &clk_smd_rpm_bimc_gpu_a_clk, + [RPM_SMD_CPUSS_GNOC_CLK] = &clk_smd_rpm_cpuss_gnoc_clk, + [RPM_SMD_CPUSS_GNOC_A_CLK] = &clk_smd_rpm_cpuss_gnoc_a_clk, }; static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = {