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[209.132.180.67]) by mx.google.com with ESMTP id n25si12926031pgv.283.2019.03.25.02.46.29; Mon, 25 Mar 2019 02:46:29 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=QuJMHL7R; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730264AbfCYJq2 (ORCPT + 7 others); Mon, 25 Mar 2019 05:46:28 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:45478 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730250AbfCYJq2 (ORCPT ); Mon, 25 Mar 2019 05:46:28 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9kL6U069629; Mon, 25 Mar 2019 04:46:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553507181; bh=ZFL1v7W0f8FRNIserxain0y5goGb0LOJ5rhl2jKOP68=; h=From:To:CC:Subject:Date; b=QuJMHL7RFN+SHxr6oU7RoNCydfd680wsTAy5UToEKk1SnEVo+Hdv2ECHOZBhHcYON VLejSH73xwyOToy+/kzWFvFCUmB/gFupJ7on3MCd9S7+fEMcjKBrq4DKJcubiv+ZyH 9pT89dM49Mq8x1Pm9PeGnYB5KjyFazWSyUzYiacM= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9kLbU115677 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:46:21 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:46:21 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:46:21 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9kI29002645; Mon, 25 Mar 2019 04:46:18 -0500 From: Kishon Vijay Abraham I To: Tony Lindgren , Rob Herring CC: =?utf-8?q?Beno=C3=AEt_Cousson?= , Mark Rutland , , , , Kishon Vijay Abraham I , Sekhar Nori Subject: [PATCH] ARM: dts: dra7: Add properties to enable PCIe x2 lane mode Date: Mon, 25 Mar 2019 15:15:25 +0530 Message-ID: <20190325094525.362-1-kishon@ti.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable PCIe x2 lane mode are added here. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/dra7.dtsi | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 2bc9add8b7a5..d87e932f45bd 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -193,6 +193,7 @@ ti,hwmods = "pcie1"; phys = <&pcie1_phy>; phy-names = "pcie-phy0"; + ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie1_intc 1>, <0 0 0 2 &pcie1_intc 2>, @@ -218,6 +219,7 @@ phys = <&pcie1_phy>; phy-names = "pcie-phy0"; ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; + ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; status = "disabled"; }; };