From patchwork Mon Mar 25 09:39:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161058 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3749856jan; Mon, 25 Mar 2019 02:42:49 -0700 (PDT) X-Google-Smtp-Source: APXvYqzbwWTk+GLbpSMHCBn2gGHWsz3CXvXInJP7EX4ezFaA6OldShCBFwm/OGRafKY5ccgz8Er5 X-Received: by 2002:a62:458a:: with SMTP id n10mr23632952pfi.136.1553506969661; Mon, 25 Mar 2019 02:42:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553506969; cv=none; d=google.com; s=arc-20160816; b=Pf+NgN8NcLUmTa/MIlkxx3/8ihb8ZWEjIEkmqhOW56b3+P+coSNZw4eG3a8K8Fk/as zRWgGR6AWhGEtOGEKBej6oTV+crbDSiQy8J+NjbQjI1v55ToHIYBzp7+tJA6dAfvs3aU C9yTCmAC6mjq+vPhV7Is6NnIN+XMcOE6weohkvgaCb/xbNBZKvLaKix5TWOvhMrwbvWl GmIOsi2eBBm/NQkczxMWjSQWN7lrOQJ3HdoNS4XKujysERYJ6ygz6AQyJXMLLFgZ8tHY 2N+398lXj+JoJu8jka1m3mq1VilKuEJc6whigZrPNxLgyRuUXLpoQWNJoldnXVrULIFC y9GQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=m/r4pmfH/rvhmKXLXqhFDQ96qk6ri3w13xsKwUvy1hk=; b=F2mMv8W23RAZQESwPKJtD1OzK2JkHhPvIUxDxo6GscWXpzzB6US7q2bhJiIOcG2HtG am+1iyl20hY81jbXmZxnXnk+bURSNFJ5EgWv/ww2FBwh4Cbwo4MVPXztyzomTiELKDxX 4h38bsRkvRN5mfmaqQyH5OxAcdgLx5SgNxnQFxZWwbLb5ZhnATtJxMwuSL93haJAq29a woUrsD2plhS0+jAOXFArAQttISd9oGzJCFgBLXAnoahQIZEZTMCMLOP/ab9GjuftNhIL 1guyCn9U1ETA8SdrEK7KIqmscVUHOMho2L417KRSDtOwBOTkvAC9K46xkGAqWyiVSbqr ysvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="iJaLiP/5"; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f7si4253111pfa.50.2019.03.25.02.42.49; Mon, 25 Mar 2019 02:42:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="iJaLiP/5"; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730335AbfCYJms (ORCPT + 5 others); Mon, 25 Mar 2019 05:42:48 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33344 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730363AbfCYJmm (ORCPT ); Mon, 25 Mar 2019 05:42:42 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9fpV9010312; Mon, 25 Mar 2019 04:41:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553506912; bh=m/r4pmfH/rvhmKXLXqhFDQ96qk6ri3w13xsKwUvy1hk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=iJaLiP/5/uP4Xejk94DcX6gByF8IzMSXFDvfmtZM7MEtmc9AbrEb7/An1Di80yRJ5 iUXTtJr/Ykm09GDJzLbQCkEWqI88Rc8cf/0RCwvgv8+pORFuJhxzPUD8Tq2zxMccGK bBEDW7EJwAKekL+wVW6ThD2qugHpje0FEowi8Adg= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9fpLC052349 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:41:51 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:41:51 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:41:51 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feaG028077; Mon, 25 Mar 2019 04:41:46 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 01/26] PCI: keystone: Add start_link/stop_link dw_pcie_ops Date: Mon, 25 Mar 2019 15:09:22 +0530 Message-ID: <20190325093947.32633-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Add start_link/stop_link dw_pcie_ops and invoke ks_pcie_start_link directly from host_init. start_link/stop_link ops is required for adding EP mode support. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 44 +++++++++++------------ 1 file changed, 22 insertions(+), 22 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index b757692e2848..07f55b355d75 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -460,18 +460,33 @@ static int ks_pcie_link_up(struct dw_pcie *pci) return (val == PORT_LOGIC_LTSSM_STATE_L0); } -static void ks_pcie_initiate_link_train(struct keystone_pcie *ks_pcie) +static void ks_pcie_stop_link(struct dw_pcie *pci) { + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); u32 val; /* Disable Link training */ val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); val &= ~LTSSM_EN_VAL; ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); +} + +static int ks_pcie_start_link(struct dw_pcie *pci) +{ + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + struct device *dev = pci->dev; + u32 val; + + if (dw_pcie_link_up(pci)) { + dev_dbg(dev, "link is already up\n"); + return 0; + } /* Initiate Link Training */ val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); + + return 0; } /** @@ -556,26 +571,6 @@ static void ks_pcie_quirk(struct pci_dev *dev) } DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); -static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct device *dev = pci->dev; - - if (dw_pcie_link_up(pci)) { - dev_info(dev, "Link already up\n"); - return 0; - } - - ks_pcie_initiate_link_train(ks_pcie); - - /* check if the link is up or not */ - if (!dw_pcie_wait_for_link(pci)) - return 0; - - dev_err(dev, "phy link never came up\n"); - return -ETIMEDOUT; -} - static void ks_pcie_msi_irq_handler(struct irq_desc *desc) { unsigned int irq = desc->irq_data.hwirq; @@ -813,7 +808,7 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); - ks_pcie_establish_link(ks_pcie); + ks_pcie_stop_link(pci); ks_pcie_setup_rc_app_regs(ks_pcie); ks_pcie_setup_interrupts(ks_pcie); writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), @@ -830,6 +825,9 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, "Asynchronous external abort"); + ks_pcie_start_link(pci); + dw_pcie_wait_for_link(pci); + return 0; } @@ -892,6 +890,8 @@ static const struct of_device_id ks_pcie_of_match[] = { }; static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { + .start_link = ks_pcie_start_link, + .stop_link = ks_pcie_stop_link, .link_up = ks_pcie_link_up, }; From patchwork Mon Mar 25 09:39:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161054 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3749399jan; Mon, 25 Mar 2019 02:42:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqwrH+yyhtcdQcAA2WBJyg1rt2Tvekw9wONRofciZavwx7PCSFT8Q3PzSV/UihOaKnkVGlN6 X-Received: by 2002:a17:902:e709:: with SMTP id co9mr1250061plb.86.1553506938631; Mon, 25 Mar 2019 02:42:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553506938; cv=none; d=google.com; s=arc-20160816; b=LDP4KIsO/fOYN+4t7wpCZ0COnLxqwtuOu/gGf/iREjOjImgtCgNAmerdqFQwQ82kxV cYsjSFHzhfyWLudP5M96G8Tj3A9UvRMD51knBg3+5C/0AbHb32EUuf631IvFMe2n3XeQ w2zequ/U0wy1Jxh0NxYxXLBsArUN0uEOxHcgEYbaaOIVcKVizYn0bFBPzajXEgglkhyh mgg7VbUrYBie0Ojj52xwQ/ffPPHKvTJoYUZZugM44aX1Mz42hdyC1KMfm9lDTqjAnKNm g31fCTyaTZ6touulCZJ39+ZO9iD8hHZyWSv4O6ir0i2VEqezSG7bu+War8+a721Muk+y cIzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=HfjjoKmsDgZT6jDC5T6H72l2yvWvnghjKzXKSseYIoU=; b=EN4+2fE3DeuURCnLtKQ458HRjFswJsfUvMLG/Nr7d7YZ9Jg3YrxL2fm59CxBvYE6g6 IGnyzgJYG2SUhpdwS7EdmUMMPXD1ce8LFhS0folqpQoHy+q1PujEnxKYwj1KrK6y9yWn rqVONb+WD5n82olUwZYzXXDCpkQ1zR6+cKc4+D01oeuzlg6lbv326yvBstALLe7zyZaZ ZIwUdBlzKwQZQxoEFs+zeAswIJ2OgtbLM5RFv6ti7I6BZ/EzFzUvgulDXZ10wUZ0iSsq +DqMlc/mQWx0hHbGwsJJrmKc93BuMx/0O5gs3qtElLfvuBAVt6GadLb3VvFtIAkTyyl2 jabw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="f3DsT/1l"; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id i18si12695129pfa.205.2019.03.25.02.42.18; Mon, 25 Mar 2019 02:42:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="f3DsT/1l"; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730243AbfCYJmR (ORCPT + 5 others); Mon, 25 Mar 2019 05:42:17 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:37400 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730399AbfCYJmR (ORCPT ); Mon, 25 Mar 2019 05:42:17 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9fvuV012556; Mon, 25 Mar 2019 04:41:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553506917; bh=HfjjoKmsDgZT6jDC5T6H72l2yvWvnghjKzXKSseYIoU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=f3DsT/1lr7cjO7CpXgVsetyb6Z1Uk3vtX+jlHTF8JCyt5KtMdZsRJoigCzC5UmBrK Aa3vIVojViV3r4Z6gmznBMT7ZSQF0E8xCDcn8/FWIaXt4BC0lydmkaqUm9pbmBPdFi cgx+Lz0KlPZ4GpdzQpVF16+7w6f7xhFHtS4jsuvA= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9fvNN013838 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:41:57 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:41:56 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:41:56 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feaH028077; Mon, 25 Mar 2019 04:41:51 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 02/26] PCI: keystone: Cleanup error_irq configuration Date: Mon, 25 Mar 2019 15:09:23 +0530 Message-ID: <20190325093947.32633-3-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org pci-keystone driver uses irq_of_parse_and_map to get irq number of error_irq. Use platform_get_irq instead and move platform_get_irq() and request_irq() of error_irq from ks_pcie_add_pcie_port to ks_pcie_probe since error_irq is common to both RC mode and EP mode. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 43 +++++++++-------------- 1 file changed, 17 insertions(+), 26 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 07f55b355d75..e50f8773e768 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -98,8 +98,6 @@ struct keystone_pcie { struct irq_domain *legacy_irq_domain; struct device_node *np; - int error_irq; - /* Application register space */ void __iomem *va_app_base; /* DT 1st resource */ struct resource app; @@ -743,12 +741,6 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) return ret; } -static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie) -{ - if (ks_pcie->error_irq > 0) - ks_pcie_enable_error_irq(ks_pcie); -} - /* * When a PCI device does not exist during config cycles, keystone host gets a * bus error instead of returning 0xffffffff. This handler always returns 0 @@ -810,7 +802,6 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) ks_pcie_stop_link(pci); ks_pcie_setup_rc_app_regs(ks_pcie); - ks_pcie_setup_interrupts(ks_pcie); writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), pci->dbi_base + PCI_IO_BASE); @@ -854,23 +845,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct device *dev = &pdev->dev; int ret; - /* - * Index 0 is the platform interrupt for error interrupt - * from RC. This is optional. - */ - ks_pcie->error_irq = irq_of_parse_and_map(ks_pcie->np, 0); - if (ks_pcie->error_irq <= 0) - dev_info(dev, "no error IRQ defined\n"); - else { - ret = request_irq(ks_pcie->error_irq, ks_pcie_err_irq_handler, - IRQF_SHARED, "pcie-error-irq", ks_pcie); - if (ret < 0) { - dev_err(dev, "failed to request error IRQ %d\n", - ks_pcie->error_irq); - return ret; - } - } - pp->ops = &ks_pcie_host_ops; ret = ks_pcie_dw_host_init(ks_pcie); if (ret) { @@ -946,6 +920,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) u32 num_lanes; char name[10]; int ret; + int irq; int i; ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); @@ -965,6 +940,20 @@ static int __init ks_pcie_probe(struct platform_device *pdev) return ret; } + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + dev_err(dev, "missing IRQ resource: %d\n", irq); + return irq; + } + + ret = request_irq(irq, ks_pcie_err_irq_handler, IRQF_SHARED, + "ks-pcie-error-irq", ks_pcie); + if (ret < 0) { + dev_err(dev, "failed to request error IRQ %d\n", + irq); + return ret; + } + ret = of_property_read_u32(np, "num-lanes", &num_lanes); if (ret) num_lanes = 1; @@ -1020,6 +1009,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev) if (ret < 0) goto err_get_sync; + ks_pcie_enable_error_irq(ks_pcie); + return 0; err_get_sync: From patchwork Mon Mar 25 09:39:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161060 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3749977jan; Mon, 25 Mar 2019 02:42:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqzUZYh4vpAsodc89kH7FB8wObrh3E+MOJ3usaKBJ7IiMzJjIrybv152gRkBKzAswJh+2DSf X-Received: by 2002:a63:5b64:: with SMTP id l36mr22912953pgm.182.1553506978150; Mon, 25 Mar 2019 02:42:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553506978; cv=none; d=google.com; s=arc-20160816; b=wwAY2Dcf8Z+mzY/413VtCYovcaL/mB7tKLXpXOCeFmTvWxPqYjbEkzCKGsBYwaacDG BfvYQJN0eTmM5Y4LIL+wUPoBVMjXuElPTotwx6Tv0NDoV3Fw5GUbUEmjz5QbHc87IZdL BeC7cuufU4EUmDMfSQWJL8qmKV79KIjO1q5BiSMPO9FdvRzxCi1HiAFrLp2DhabcOoZX p34ByfRv/QL4YNAGLtecZKW84CZHfhf1VZYgh2958FIWcit2lJJi4iGEylXHQ1DrF7uJ KAkW8RTteIbZL5cl+AullHywBsmVDrgamnhCoZ9IA8j88pp5jhV6eywSEPAKY7fng7QV 7X+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=8ftV+tyeP19Er0Uqruzv3Zjv2HvQTzbCletDFZ3afkE=; b=Y3OHGzbSgtzjHoaEQXyM5z1Xuu4o6iPmHcLVScQhUOf+So7iJUIsZrA1cFGo7lrloS roGWaAu49Z7UFPAazAHAhW1mWkZehq66lvte7djE1nFpTSt9Wt2MnaHdN86WTPZvZfVq 6MZ7dKbO+xFFAnBXP1Yk5RGBTFPhoflcZgvgt7T4NEo+L1wYxRGN/itOnpNASFNkqy4/ 7+gv36+OOJoGBjo3f8CPPv0vJjaVJhWSf6e5b0RRaa+X7omFw4kmQv8OzZul1OTggYwk jiyt6t3eMi79Ua5UdOWZFnXRllljdQYQcaGycpeExo36qiCgoizQ6tMxH4IzuleDzRXl QZtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jOq4s48v; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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While at that get the memory resource defined specifically for configuration space instead of deriving the configuration space address from dbics address space. Since pci-keystone driver has never worked out of the box in mainline kernel, dt backward compatibility is ignored. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 566718ea7ebf..5eebef9b9ada 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -44,7 +44,6 @@ #define CFG_TYPE1 BIT(24) #define OB_SIZE 0x030 -#define SPACE0_REMOTE_CFG_OFFSET 0x1000 #define OB_OFFSET_INDEX(n) (0x200 + (8 * (n))) #define OB_OFFSET_HI(n) (0x204 + (8 * (n))) #define OB_ENABLEN BIT(0) @@ -807,21 +806,19 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct resource *res; int ret; - /* Index 0 is the config reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); - /* - * We set these same and is used in pcie rd/wr_other_conf - * functions - */ - pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); + pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pp->va_cfg0_base)) + return PTR_ERR(pp->va_cfg0_base); + pp->va_cfg1_base = pp->va_cfg0_base; - /* Index 1 is the application reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); ks_pcie->va_app_base = devm_ioremap_resource(dev, res); if (IS_ERR(ks_pcie->va_app_base)) return PTR_ERR(ks_pcie->va_app_base); From patchwork Mon Mar 25 09:39:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161057 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3749756jan; Mon, 25 Mar 2019 02:42:43 -0700 (PDT) X-Google-Smtp-Source: APXvYqx79R2lYqHFUbSLkUiisG11N8S+4d34vjPg+jXrVk6p5xNS4jlbfep9bWdRolp5nfV4qpg4 X-Received: by 2002:a17:902:6b08:: with SMTP id o8mr24392394plk.105.1553506963609; Mon, 25 Mar 2019 02:42:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553506963; cv=none; d=google.com; s=arc-20160816; b=rk8UY7v49IHludyVEL3BBvNjwIrh/uoG76d/QfQ9DUNWjsyU5oNi8GGlv9/7qA3/Zm j/e3mGWxnpQQSoHgAr7g0rbGnl6vwgUcHQPIt46FT2fMyrkOZTVbV73DPYjpbhWXvEWx 3li0iYypU7Abv2bSkkRee7uds9+7qtAx8k93wZlXfyLKCsKNUR/HQwpR9w9iT3D1imQ3 OLbeIcy0YogWS8gTXp2rd/x57OO1F5Hza2WNMo2csDtEI56f1mtEI52jEezl0l6QOnvj a+H3W8rWotNj4NAqMyIzeBa4wwGKMeJHwmc2lYiddav2dWEhD8jPJkrin9MA16Cp0jyF 6WXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=oAuFemY1UD35AldoLImxdd3vpDxKgsYr+M4wvx9YL3g=; b=DKbTvrTXfdnaTgLCpXNWrJX3RlvrcU4rzUSboUpkDaag8zF5WC1MQ4+QZhhy5X/lgo V/c6Ma3xidTlCsCyTrCbgnoqlxelX9Upj195KVXed8tpFIOzQoJUSmaB5EUDz+yEd7h9 JMACEelnZHbWJ936Oa9631u2Jpcy+LHPAtvHPLk7itIQyv+Vi1sA28tQbpFPDkW9O2nh 0KaNvf6SbERnlDMBFroXm0vrOyru4+izjOavCobLNvRjCerw52ysOv8HareOfvwX3X8O KduraW5Kf4V5Ag1lGYzWoE5Nk8Dlg997KLS/0zTSH3U/eJM6Y+1Wze7tfTYyY7LJ+RM7 4aGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=P7nxuX70; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 3a551687cfa2..8ee07197a063 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -23,6 +23,8 @@ pcie_msi_intc : Interrupt controller device node for MSI IRQ chip ti,syscon-pcie-id : phandle to the device control module required to set device id and vendor id. +ti,syscon-pcie-mode : phandle to the device control module required to configure + PCI in either RC mode or EP mode. Example: pcie_msi_intc: msi-interrupt-controller { From patchwork Mon Mar 25 09:39:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161061 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3750180jan; Mon, 25 Mar 2019 02:43:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqyNjObq4CYM1o0Bggz3hOgxrMQojd3rWOStRe2mViuul8QvH/BoHWFTwtW84v3lwl9p5Kgi X-Received: by 2002:a62:70c9:: with SMTP id l192mr23211410pfc.207.1553506989678; Mon, 25 Mar 2019 02:43:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553506989; cv=none; d=google.com; s=arc-20160816; b=ddZzlcPoeuGPLmMlf8yaNzrX8VS6wCotuJBlt6Zdd01DVSckJXS3+bX0ku2ic+re7U FmIWcFo/OVVYeMAWx6E8nRmxR5nSGE07mIioDVIUIgu1Ze4UeYu0IOE43hynBJDPFgnG hVy4Gje+mG+i58NkiIp9Bs6lAd236O8/XcuyATk7+ie3J26KyLohyrhYHGIEs6gOUxbb Z9AElK1NHz1tM6p8NkdFu4czPIfVcIUqPKIw9yZ7wuUOwpLdMzHSbLN4AYxEXnZuIoan 6vtjqnEbg0QMMaOcuPXYTlfNMZIHDJL/axnr+abzHsRSBiZhZHJjYSHntrOGNqwUQhvU kjfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=1lGjasujhkFf/3ytOeLr0WSkR7aiRJac7oOtRyOLFg4=; b=aftPrXTz6R2Cx07g0STiMoLfVPNwpCYQhn+nqACicqnQAx7dmvs21PHd7miv/HsRlM txV6Wl//01914xnWmmEXUeZz+JFCl/E14Dijz7S1MtoJZdOmGBOb5mm0ULsbNfD2Sral pOXn98BHqHn7uTGH7kLOy7gbXbaBAJfRe7NZSSb0rrNyJA+KASGQ79kQcFv3xGrxRKKQ 3wZtsJiQaLMU7HD+fVKrwfpCkwTZH+gCUzZsAf15xo+AdDfwmHFbFEyadZnWwr/5Qzl0 m82JZxn2Mdb6igw93RJW3SDG1o5UyT+a4tXHvBCbLeJnwdXS91foa4Oved5eVXfXythU 7Myw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=iV9eDIFf; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id z4si12870402pgu.375.2019.03.25.02.43.09; Mon, 25 Mar 2019 02:43:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=iV9eDIFf; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730423AbfCYJnI (ORCPT + 5 others); Mon, 25 Mar 2019 05:43:08 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33380 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730387AbfCYJnI (ORCPT ); Mon, 25 Mar 2019 05:43:08 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9gUIM010585; Mon, 25 Mar 2019 04:42:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553506950; bh=1lGjasujhkFf/3ytOeLr0WSkR7aiRJac7oOtRyOLFg4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=iV9eDIFfRaymmCx+e9840Cb4kWsWCsSqXSZ6eAPwSzS0BCCVfcMN2Gy+pAsVy1XCE vIZbZKmu8tzLEL+iNZKD3X+2I+U+EoBCTwzP9NcM0uzRwnwAf3VxNXzRiGCq2ZinMd 7JWBVBG3bYzBSowxiLlK+dLwwbEBqnxpsNzS9l8Y= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9gUci053184 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:42:30 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:42:29 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:42:29 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feaN028077; Mon, 25 Mar 2019 04:42:24 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 08/26] PCI: keystone: Explicitly set the PCIe mode Date: Mon, 25 Mar 2019 15:09:29 +0530 Message-ID: <20190325093947.32633-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Explicitly set the PCIe mode to BOOTCFG_DEVCFG instead of always relying on the default values. This is required when EP mode has to be explicitly written to BOOTCFG_DEVCFG register. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 37 +++++++++++++++++++++++ 1 file changed, 37 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 95997885a05c..dfe54553d832 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -79,6 +79,15 @@ #define PCIE_RC_K2L 0xb00a #define PCIE_RC_K2G 0xb00b +#define KS_PCIE_DEV_TYPE_MASK (0x3 << 1) +#define KS_PCIE_DEV_TYPE(mode) ((mode) << 1) + +#define EP 0x0 +#define LEG_EP 0x1 +#define RC 0x2 + +#define KS_PCIE_SYSCLOCKOUTEN BIT(0) + #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) struct keystone_pcie { @@ -876,6 +885,30 @@ static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) return ret; } +static int ks_pcie_set_mode(struct device *dev) +{ + struct device_node *np = dev->of_node; + struct regmap *syscon; + u32 val; + u32 mask; + int ret = 0; + + syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); + if (IS_ERR(syscon)) + return 0; + + mask = KS_PCIE_DEV_TYPE_MASK | KS_PCIE_SYSCLOCKOUTEN; + val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN; + + ret = regmap_update_bits(syscon, 0, mask, val); + if (ret) { + dev_err(dev, "failed to set pcie mode\n"); + return ret; + } + + return 0; +} + static int __init ks_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -988,6 +1021,10 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } + ret = ks_pcie_set_mode(dev); + if (ret < 0) + goto err_get_sync; + ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) goto err_get_sync; From patchwork Mon Mar 25 09:39:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161063 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3750262jan; Mon, 25 Mar 2019 02:43:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqx/H9CeOreLaAumv3NuqNutrww5FFQk5mhjMYpPC+UUN+7JuLG+2/l4SlT+jY9e9LfgGzPe X-Received: by 2002:a17:902:7786:: with SMTP id o6mr24075666pll.206.1553506996698; Mon, 25 Mar 2019 02:43:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553506996; cv=none; d=google.com; s=arc-20160816; b=mk5qzat6EtpbjXuXWccsRRwMQ/fzhV2zMKcIrtBfG34FB+uXqs1VC89PIk9IV9vPjw ETID91OvzwwWYNLRKyyCIy+JHuXUHquhciveA4EjavKvnj0Ogt+VJFjgBKjcskF/A2Ve 0GwzWBvnipSLCf9B5kPPKkK3GuTXytc1b850HN5OyKsLwuM2pGlEj9WjHY/1nFEA6HW9 CK+K1rA4tM+L3dTIte1Lq0smdIpubOn+F3gv9rTUi6U5crF3QR5Qsna/bC1nf0RoKIYC 08bODIusvz6yQmNGQVjBYTHxF5CJGDo1CSt3z23Xn/jLaTUTLHXlOvz5XQW8tzMOStzv T3QQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Z5FsYHz2+eCaWuP/Fr5+/R+9oCvd7mzmcItqNVxbMQU=; b=rBAlrKYkMh92ixWXnlUwJI4+Zdlr/VarWqEP9ynIhA7XLbjmdhB1p+gR9DQt6yXomR Fgw4K/b3PdrXp0cyuiM0gAovaD4jD+QwJBbUaTpVyEYQKLIuzzU0oCO7iUMqb38dvT53 +VBRn7T16aTk0jQw9K2O580nKpK/oY4jzTfSqrpuJuTd+WRF2oU4qMMo0VZ0maFbCO0g wXWYZ+yyPWkkNYCAQx9o8xgh9nzeIrloWXPquwakaKcIm23BlD3wKzrtt+D2EF8yMeJ8 exiTmYyFibHrxgY2YnR/rfcWZfUoUM+dlqRK8maDwRYvDW1/yZPqurOv6Jn9ctjnRwyo 8v+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=EsuxLzUm; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 193si13081900pgc.365.2019.03.25.02.43.16; Mon, 25 Mar 2019 02:43:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=EsuxLzUm; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730597AbfCYJnO (ORCPT + 5 others); Mon, 25 Mar 2019 05:43:14 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:44982 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730593AbfCYJnN (ORCPT ); Mon, 25 Mar 2019 05:43:13 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9gkkm067924; Mon, 25 Mar 2019 04:42:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553506966; bh=Z5FsYHz2+eCaWuP/Fr5+/R+9oCvd7mzmcItqNVxbMQU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EsuxLzUmb3c+iIHmKZxkVrXL7iwFXghWiPWvextA9NH0F/wxiYKWGApgH90rG7faD oZGrREqi86ksXdQqhCUXCiqc4zB4nsiNd5maXdX9tU4KXndvsxZgdQYEUYMoBZo+b7 k/b6d6JbuouqMFu1ZctJ7FlCEDsp5xgjxWwBxiFU= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9gk5E109867 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:42:46 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:42:45 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:42:45 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feaQ028077; Mon, 25 Mar 2019 04:42:40 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 11/26] PCI: dwc: Fix ATU identification for designware version >= 4.80 Date: Mon, 25 Mar 2019 15:09:32 +0530 Message-ID: <20190325093947.32633-12-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Synopsys designware version >= 4.80 uses a separate register space for programming ATU. The current code identifies if there exists a separate register space by accessing the register address of ATUs in designware version < 4.80. Accessing this address results in abort in the case of K2G. Fix it here by adding "version" member to struct dw_pcie. This should be set by platform specific drivers and designware core will use it to identify if the platform has a separate ATU space. For platforms which hasn't populated the version member, the old method of identification will still be used. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware.c | 14 ++++++++------ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 9 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index a14ca00f72aa..4e2f7946da89 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -358,13 +358,15 @@ void dw_pcie_setup(struct dw_pcie *pci) struct device *dev = pci->dev; struct device_node *np = dev->of_node; - /* Get iATU unroll support */ - pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); - dev_dbg(pci->dev, "iATU unroll: %s\n", - pci->iatu_unroll_enabled ? "enabled" : "disabled"); + if (pci->version >= 0x480A || (!pci->version && + dw_pcie_iatu_unroll_enabled(pci))) { + pci->iatu_unroll_enabled = true; + if (!pci->atu_base) + pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; + } + dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? + "enabled" : "disabled"); - if (pci->iatu_unroll_enabled && !pci->atu_base) - pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; ret = of_property_read_u32(np, "num-lanes", &lanes); if (ret) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index ca3a3190a6f5..90a5b1215344 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -234,6 +234,7 @@ struct dw_pcie { struct pcie_port pp; struct dw_pcie_ep ep; const struct dw_pcie_ops *ops; + unsigned int version; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) From patchwork Mon Mar 25 09:39:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161075 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3751555jan; Mon, 25 Mar 2019 02:44:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqyQaUIWgzL/S5GpNT3Vvkz/bPFTtN+jYD1oJF7gPn/Gme69QJTOLzS7L4are9i7GUKwFAjY X-Received: by 2002:a17:902:7794:: with SMTP id o20mr25068710pll.28.1553507090760; Mon, 25 Mar 2019 02:44:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553507090; cv=none; d=google.com; s=arc-20160816; b=FA0fHnaWS2WeZmnkTlKX81EL30/VdAvBcS5bqU447+Wak6p4h9t0w0Z/7WTgbYxAtr LDoa3rHWotnvV7eU1qvFHRBU+AVQeE1tYdhpSrSpF/soNfI0KWcE/XueNNh77ApsEleQ PHlMfewIO7viE/OpXnj9mg6WmU20P4f5CZ07DC3wtF+DV+vDRGLDXa8hG9OD0ABulShD 7Nr6uHgCxtzG3OnCt0rVBw65KihohNGZoUq0KHUsAJ6/CpX6+8A3lIwKW/fSwvu1CpM/ LnatOTVv1VGLxG6yQ8bTxc9QGBFVyrF+jTb1fwA3P0AZy/6x8U6Nf8cdAfb49qsevHxP +qjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=mRZ/N3tIORcVcdf8U0MRLHXGRFmU8jONue5muhGax30=; b=ZyzV+mmDfZv+yubgOqXyOgDf1AQ0kXbZQo2SDT74zvgEtrq243d964ex4ZKxcWigQa 8GZ55J1PDTEXkJBTZhJL63AWHBaCwLNVpH4KwSgXjOc2g2qdYCLE+X7fOY0vGP3x9mlr eIqatyqeICVkosqpItfNsX4Xuk2eZE/uc9zFexLaqavuvKSm0/p80DGNmVgpsSodLxKW IKz+gLf+fcYBXhAiMctXmMAgXLWVcHZWuCBTT0U89ZnwLixcHUWS/N8XLjNFvD84LGEo RSzHV1sDVr3CvgJ6tVLvWwfb67ZDqDUi0wn3lRwqOVqGz2B/WKN+3iQRzWRRuZFd6hkI u7bA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=IQph3MKj; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id k30si13435688pgb.587.2019.03.25.02.44.50; Mon, 25 Mar 2019 02:44:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=IQph3MKj; spf=pass (google.com: best guess record for domain of linux-omap-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-omap-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730405AbfCYJot (ORCPT + 5 others); Mon, 25 Mar 2019 05:44:49 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:33566 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730367AbfCYJn6 (ORCPT ); Mon, 25 Mar 2019 05:43:58 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P9hfQl011167; Mon, 25 Mar 2019 04:43:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553507021; bh=mRZ/N3tIORcVcdf8U0MRLHXGRFmU8jONue5muhGax30=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IQph3MKj0FFIVKxRrdWpqnWE6Cbht0FZaHh/8sOKp5hdax6RXlg9LxsPZs1bvDoTP ZvOzv2Xkiadn9RpJMh1mNBOOB0Yidkk2Rox3/m2JGgTcom2f7cHef+D3IF7sy9aWD+ LkgPT0qaXWQzU8yQF/yI2bisZXCR0Jowjts2KnjE= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P9hfbE111505 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 04:43:41 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 04:43:40 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 04:43:40 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P9feaa028077; Mon, 25 Mar 2019 04:43:36 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Minghuan Lian , Mingkai Hu , Roy Zang , Jesper Nilsson Subject: [PATCH v3 21/26] PCI: dwc: Add callbacks for accessing dbi2 address space Date: Mon, 25 Mar 2019 15:09:42 +0530 Message-ID: <20190325093947.32633-22-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325093947.32633-1-kishon@ti.com> References: <20190325093947.32633-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org Certain platforms like TI's AM654 doesn't have separate address space for dbi2 instead they are accessed using the same address space as dbi with some configuration bit set. In order to support such platforms, add callbacks for accessing dbi2 address space. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware.c | 31 ++++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 12 ++++++-- 2 files changed, 41 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 4e2f7946da89..d7cc1a0c1de6 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -89,6 +89,37 @@ void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, dev_err(pci->dev, "Write DBI address failed\n"); } +u32 __dw_pcie_read_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size) +{ + int ret; + u32 val; + + if (pci->ops->read_dbi2) + return pci->ops->read_dbi2(pci, base, reg, size); + + ret = dw_pcie_read(base + reg, size, &val); + if (ret) + dev_err(pci->dev, "read DBI address failed\n"); + + return val; +} + +void __dw_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size, u32 val) +{ + int ret; + + if (pci->ops->write_dbi2) { + pci->ops->write_dbi2(pci, base, reg, size, val); + return; + } + + ret = dw_pcie_write(base + reg, size, val); + if (ret) + dev_err(pci->dev, "write DBI address failed\n"); +} + static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index e36941ff7cf6..7abca9eb00bf 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -218,6 +218,10 @@ struct dw_pcie_ops { size_t size); void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, size_t size, u32 val); + u32 (*read_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, + size_t size); + void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, + size_t size, u32 val); int (*link_up)(struct dw_pcie *pcie); int (*start_link)(struct dw_pcie *pcie); void (*stop_link)(struct dw_pcie *pcie); @@ -249,6 +253,10 @@ u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size); void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size, u32 val); +u32 __dw_pcie_read_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size); +void __dw_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size, u32 val); int dw_pcie_link_up(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, @@ -292,12 +300,12 @@ static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg) static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val) { - __dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, val); + __dw_pcie_write_dbi2(pci, pci->dbi_base2, reg, 0x4, val); } static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg) { - return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4); + return __dw_pcie_read_dbi2(pci, pci->dbi_base2, reg, 0x4); } static inline void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val)