From patchwork Mon Mar 25 08:34:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161032 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696207jan; Mon, 25 Mar 2019 01:36:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqxNxBTX9ntjWoWwo98XPUuyrA57hTh2wXQTYE8IkWPne3wjeBh+K0Egf8SUImchWva0894O X-Received: by 2002:a65:6389:: with SMTP id h9mr4245614pgv.398.1553503006140; Mon, 25 Mar 2019 01:36:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503006; cv=none; d=google.com; s=arc-20160816; b=WEmj1b4Y9xX05Mqu80c0tZrwjxvT2ecinrdh/j33hqmVXtMMXhmq0u1kqCyWAbvMus rtt1busyAIC3Zc+WMjmQEiBo6azbiFfwaKA40Xi7OqAFlZfEc10SU8qUE/HGdMBV1s9J u41UqtK9Grn3AWeOzCRuY0P07Wh4SVL5/yQPfoOKBlJwJX3fKrEud4YncYD/GVbt0cLZ OkzBji3+si6MAKSFT/t1cXtPiSmvnQUq5k49vqFR0vaIFWfZfEAg8+0O8/OFA2mBB7gU IxsHKy/Js5n2xQMi44Gp+6Nh4vZDz007EjpZfp7RzxFEK/TsUMkTkTQuMyUHkNNQhNRV /maQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Wx7Yx/QA57xsICcriJ4mx2XFfp/NPcRkGKsQ4ow3LF0=; b=pvp5yvCxiBMGxvQ9y2rS6JYc+A2Fd+IzEL3ZvhIKqygHQjJEc6ACXMug3tSNC/L6OV Dq2xPUP5J4hXi9QVkpLYCVjIwN8GDZw9Lcnu74beNYN/E+S11/jsh0Fmg/m9aeuLsxz5 5GizlTxAlpZ0RKi1A5g2TtteofCEgjz+2xEW8+xbc4UncjaTnRSmBD3Gne/aA6WiKeIE /j6oQex2Xw7uG+Fr4IaBo9tquWkcOU5HVcq9aInV7iHiv50yfls5TKK/SOKggFajKdI1 wqrFeub/0aaEdowMWF+hs79ir4cVTmu2RNdytuRVWa11G+s1yMMbQwhihhEWrIeIQT9L I8kA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RpZhgdcI; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l4si12082288pgp.169.2019.03.25.01.36.45; Mon, 25 Mar 2019 01:36:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RpZhgdcI; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730198AbfCYIgo (ORCPT + 7 others); Mon, 25 Mar 2019 04:36:44 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:33866 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730175AbfCYIgo (ORCPT ); Mon, 25 Mar 2019 04:36:44 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8aOK1030728; Mon, 25 Mar 2019 03:36:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553502984; bh=Wx7Yx/QA57xsICcriJ4mx2XFfp/NPcRkGKsQ4ow3LF0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RpZhgdcIh9GESuhQjBLGrARoKFT8uLTABCPEPOcNeym31O19xBQdDs0YyXtrCisSR HK8VqUPJ8LfL/fbxiL8Nj4sW17IDxP5DD7Fmh8HcCPBLUQhfJf/fGed1y3qw/WLlcg /XSuo88ewHWFIHeJBXKei7ChA9XVSYTDg+FoZ6Ow= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8aODI088620 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:36:24 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:36:24 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:36:24 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFm006534; Mon, 25 Mar 2019 03:36:20 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 06/26] PCI: keystone: Move initializations to appropriate places Date: Mon, 25 Mar 2019 14:04:41 +0530 Message-ID: <20190325083501.8088-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org No functional change. Move host specific platform_get_resource to ks_add_pcie_port and the common platform_get_resource (applicable to both host and endpoint) to probe. This is in preparation for adding endpoint support to pci-keystone driver. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 27 +++++++++++++---------- 1 file changed, 15 insertions(+), 12 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 5eebef9b9ada..95997885a05c 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -806,11 +806,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct resource *res; int ret; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); - pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pci->dbi_base)) - return PTR_ERR(pci->dbi_base); - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pp->va_cfg0_base)) @@ -818,13 +813,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, pp->va_cfg1_base = pp->va_cfg0_base; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); - ks_pcie->va_app_base = devm_ioremap_resource(dev, res); - if (IS_ERR(ks_pcie->va_app_base)) - return PTR_ERR(ks_pcie->va_app_base); - - ks_pcie->app = *res; - pp->ops = &ks_pcie_host_ops; ret = dw_pcie_host_init(pp); if (ret) { @@ -895,6 +883,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev) struct dw_pcie *pci; struct keystone_pcie *ks_pcie; struct device_link **link; + struct resource *res; + void __iomem *base; u32 num_viewport; struct phy **phy; u32 num_lanes; @@ -911,6 +901,19 @@ static int __init ks_pcie_probe(struct platform_device *pdev) if (!pci) return -ENOMEM; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); + ks_pcie->va_app_base = devm_ioremap_resource(dev, res); + if (IS_ERR(ks_pcie->va_app_base)) + return PTR_ERR(ks_pcie->va_app_base); + + ks_pcie->app = *res; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); + base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + + pci->dbi_base = base; pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops; From patchwork Mon Mar 25 08:34:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161042 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696845jan; Mon, 25 Mar 2019 01:37:36 -0700 (PDT) X-Google-Smtp-Source: APXvYqwNTLliX7kSocn8XpnkayESUmcCjse1B9YC3A89WG+zRyHrr4axs+oSVMoFegLzxAwfsn5X X-Received: by 2002:a63:6949:: with SMTP id e70mr22044167pgc.89.1553503056693; Mon, 25 Mar 2019 01:37:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503056; cv=none; d=google.com; s=arc-20160816; b=eUWtrgvu3k7C3U4mNcNyYppn/p0jGw2N579kO829pg2/WrxgCQyIKo4U816dzm8RAt wUcTd5VncB0io7rwtSDm5aaLkVuAw5m4SGjt8/CoSEJc5aQTUEFY6I/ME5yG/p136H+O sjShsoDhWGK21OQ0EMorEGBfo1JDh5vsRVhk1wg3Omner+djXVbSkXk+RgN7uHLhWz67 eycDrrVreAnPSd0FuQ91e6vm9LLQC1W0yIAgEZ2nTOWbETad1RGcYIssrnQO4J4uTg+6 PxTBmMBmDZBmkBfKi7xkw42Bi8ZzgKAOG2RideL40QY6iIX58ULkYyG6VeIGQebiLIT3 +AMw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=FFBI81IHUSwFB45pqKhYDbRxN16ADNIUFkLN5k6S3dE=; b=YE4SH0m/6QlwYTP962kH4Fqdzqeb3E4+snJmKzoNPgYBnBgS/GITSGocA35QgJX6Gw oleV5gXjaxBRNAmV+/DFzAA64gIVNO83x8xGBYpbOLWSDkRT9DfTTIy0oDva8Q/CJ2XI AKIvVDT8cnYpjr94fYxRXv1jAtSa0TFxteE3B/dceMW/XrO1eBKKBPXtKcqIbEMxOMCD Vh2U6CizVXVOTX3TgZ/qHurvJAT52csNfYbN15lR6GVxulicsApvXvJ/y67iY96OV2Pa tcKwGO3RZupRNpebAyTXWpPNVKJX5TCSxpZqg1o/p6jl7UFlxvnNrCS8KSmpgntL4u/4 6B5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=G9yVLeaJ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u18si3014560pgk.469.2019.03.25.01.37.36; Mon, 25 Mar 2019 01:37:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=G9yVLeaJ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730049AbfCYIhf (ORCPT + 7 others); Mon, 25 Mar 2019 04:37:35 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:34048 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729929AbfCYIhf (ORCPT ); Mon, 25 Mar 2019 04:37:35 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8bKZd031107; Mon, 25 Mar 2019 03:37:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553503040; bh=FFBI81IHUSwFB45pqKhYDbRxN16ADNIUFkLN5k6S3dE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=G9yVLeaJ1feWrZZP/o/42jlczvAF/UnU6BxyruGqEWTKaQkkIVxdd39I8YTS7qAdJ +UN8xUUj2qVi4JMzTYVcyhyFUuCOHsrb9wgbaOmqFxuK5P9yVgCZoQQh1lv9zUlIVo iTmPRmTOUMygakwOPKg+LRGspOzSRuDSjiw5heOg= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8bKlA089711 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:37:20 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:37:19 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:37:19 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsG1006534; Mon, 25 Mar 2019 03:37:15 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 19/26] PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops Date: Mon, 25 Mar 2019 14:04:54 +0530 Message-ID: <20190325083501.8088-20-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add const qualifier to struct dw_pcie_ep_ops member of struct dw_pcie_ep. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-dra7xx.c | 2 +- drivers/pci/controller/dwc/pcie-artpec6.c | 2 +- drivers/pci/controller/dwc/pcie-designware-plat.c | 2 +- drivers/pci/controller/dwc/pcie-designware.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c index ae84a69ae63a..b287dbf6914c 100644 --- a/drivers/pci/controller/dwc/pci-dra7xx.c +++ b/drivers/pci/controller/dwc/pci-dra7xx.c @@ -406,7 +406,7 @@ dra7xx_pcie_get_features(struct dw_pcie_ep *ep) return &dra7xx_pcie_epc_features; } -static struct dw_pcie_ep_ops pcie_ep_ops = { +static const struct dw_pcie_ep_ops pcie_ep_ops = { .ep_init = dra7xx_pcie_ep_init, .raise_irq = dra7xx_pcie_raise_irq, .get_features = dra7xx_pcie_get_features, diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c index dba83abfe764..d00252bd8fae 100644 --- a/drivers/pci/controller/dwc/pcie-artpec6.c +++ b/drivers/pci/controller/dwc/pcie-artpec6.c @@ -444,7 +444,7 @@ static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, return 0; } -static struct dw_pcie_ep_ops pcie_ep_ops = { +static const struct dw_pcie_ep_ops pcie_ep_ops = { .ep_init = artpec6_pcie_ep_init, .raise_irq = artpec6_pcie_raise_irq, }; diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index 932dbd0b34b6..b58fdcbc664b 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -106,7 +106,7 @@ dw_plat_pcie_get_features(struct dw_pcie_ep *ep) return &dw_plat_pcie_epc_features; } -static struct dw_pcie_ep_ops pcie_ep_ops = { +static const struct dw_pcie_ep_ops pcie_ep_ops = { .ep_init = dw_plat_pcie_ep_init, .raise_irq = dw_plat_pcie_ep_raise_irq, .get_features = dw_plat_pcie_get_features, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 90a5b1215344..e36941ff7cf6 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -196,7 +196,7 @@ struct dw_pcie_ep_ops { struct dw_pcie_ep { struct pci_epc *epc; - struct dw_pcie_ep_ops *ops; + const struct dw_pcie_ep_ops *ops; phys_addr_t phys_base; size_t addr_size; size_t page_size; From patchwork Mon Mar 25 08:34:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161043 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696902jan; Mon, 25 Mar 2019 01:37:40 -0700 (PDT) X-Google-Smtp-Source: APXvYqzV0SIHcWGK2DglVFa6k7OUMKArgK+aXccgTJwMPq5KuaJCoScS8UPs8XpW95HjxZgnZZxX X-Received: by 2002:a17:902:9a0b:: with SMTP id v11mr23919851plp.194.1553503060510; Mon, 25 Mar 2019 01:37:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503060; cv=none; d=google.com; s=arc-20160816; b=l+RzsQfUGUbAltmTmKhSodviushbbc0VkwQeAiFCrI7cuRvzcSqzL//zJLZFA5C8Us rLH0NzfsJzwv4lyT4oqj8AXiDgakiAt9xRXWO9+kYCp534KoKvwKfcfKf224QMSVsCkS zwumb5OhUAnwW64OIvc9+gldi/XV1mIc3pLv8XcmPcyw2XSyH2DpugqkX6WcRdCHGy5F 6t7xjqENHDIgLusneTZeSHJ03g1uMY2fTb5dmxseHL5Q5f53zXdMLPJMVhch4xzupWIN m5EMOo6bV5sj4Uj2gk7RP7yByX1OiHnNKKXuPSljatg5RtdvVYjzgtDoTzvzrZ5xcJBH 0kmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=F1vNw6974A4SxeLsowTyiNZ0yV33iVQDSJNdrli8b/8=; b=jq2J5c3ygpXS0auqCeNEarDgEwFdjIRXXi+fBWgX8rAtdznUrJahTEndpzIZ83x79Z tNG7/Qm+Re5PdRGFTmfQm+6OvB9TmyTOrCbpqtVBeBnu1Bzin36Y0c2LQs1CyC0iyT9R OP+l3CpjStpKRfXIf5KAxYUApup1vMSsDhL8766rj2wTzpDaudf3bP4aAS1Ddg1819FI k7SqYpFYcE0Z1I8qIeKK23/3N+ZrWxr5yONz2FTLn24rur2wgOPfQpSJE1IkdIr/WBSf uMYaUyNhptRMErhNpRZnuBTG356eU4ztTu+1cEU4rCxt2XuZ0dJpYGS8O++6g/R9EqQy Fk9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=y3kNCOz8; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 16si13502314pga.351.2019.03.25.01.37.40; Mon, 25 Mar 2019 01:37:40 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=y3kNCOz8; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730369AbfCYIhj (ORCPT + 7 others); Mon, 25 Mar 2019 04:37:39 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:54964 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729929AbfCYIhi (ORCPT ); Mon, 25 Mar 2019 04:37:38 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8bOBu106956; Mon, 25 Mar 2019 03:37:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553503044; bh=F1vNw6974A4SxeLsowTyiNZ0yV33iVQDSJNdrli8b/8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=y3kNCOz8dBIRp1kJky4rjbnokoiNeMhg9+CX8D4GZ3jb/M1ISn0gUgVyujyYT0E6t 25GX4h/rYcc/ioIfebB/cBLCBCIwRL3PCKN8DtoB2wWHVLjx3fwOAEXoP+5sJIJ5ID 3ohoWPVJxiWiNHx6TCJUTJ+vKCoh+6WC0EYGFuxU= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8bOqM017802 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:37:24 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:37:23 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:37:24 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsG2006534; Mon, 25 Mar 2019 03:37:20 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 20/26] PCI: dwc: Fix dw_pcie_ep_find_capability to return correct capability offset Date: Mon, 25 Mar 2019 14:04:55 +0530 Message-ID: <20190325083501.8088-21-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org commit beb4641a787df79a ("PCI: dwc: Add MSI-X callbacks handler") while adding MSI-X callback handler, introduced dw_pcie_ep_find_capability and __dw_pcie_ep_find_next_cap for finding the MSI and MSIX capability. However if MSI or MSIX capability is the last capability (i.e there are no additional items in the capabilities list and the Next Capability Pointer is set to '0'), __dw_pcie_ep_find_next_cap will return '0' even though MSI or MSIX capability may be present. This is because of incorrect ordering of "next_cap_ptr" check. Fix it here. Fixes: beb4641a787df79a142 ("PCI: dwc: Add MSI-X callbacks handler") Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-ep.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index dc6a4bbd3ace..74477ad7467f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -46,16 +46,19 @@ static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr, u8 cap_id, next_cap_ptr; u16 reg; + if (!cap_ptr) + return 0; + reg = dw_pcie_readw_dbi(pci, cap_ptr); - next_cap_ptr = (reg & 0xff00) >> 8; cap_id = (reg & 0x00ff); - if (!next_cap_ptr || cap_id > PCI_CAP_ID_MAX) + if (cap_id > PCI_CAP_ID_MAX) return 0; if (cap_id == cap) return cap_ptr; + next_cap_ptr = (reg & 0xff00) >> 8; return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); } @@ -67,9 +70,6 @@ static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap) reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST); next_cap_ptr = (reg & 0x00ff); - if (!next_cap_ptr) - return 0; - return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap); }