From patchwork Mon Mar 25 08:34:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161029 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696099jan; Mon, 25 Mar 2019 01:36:37 -0700 (PDT) X-Google-Smtp-Source: APXvYqzzVV6dUWp2tcCaz/GaaKQ1fgXni28CXTjTkqMpgNZEWEKvUF14FDDooswwewUtNXhWwT18 X-Received: by 2002:a65:47cb:: with SMTP id f11mr22207894pgs.18.1553502997839; Mon, 25 Mar 2019 01:36:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553502997; cv=none; d=google.com; s=arc-20160816; b=a9FFI6y/xnLf4re02mQnTNRL7rXnwmvZnp67g/phtmwXrnV7OCuk7uL4o3aFVlquSV VxsDbWkKar5wp8exmg4bWdfMDWGucZHRBQKwva4TphTak5jqyHFSiKsogiNltcdaDkcY I+ImIhFPBky7shHkaiAcCM3HJjPy9PFTfGMD2CJeG2yixfZGFf2yBrSwA7VReu/VNj1q XIH2T9mRC8a6Jq2WyvKbGva7RJrSCgH0rt5lt8g4/nZh0X5ukc9TIDLEopPPWMxo1K1K FY9Lr+XEcWAEiVqNCdD/RthraD9Z0jY5+g0xJEMWuINNRbXuOqwNf+5aFcDQF2dZh6RA Ftfg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=m/r4pmfH/rvhmKXLXqhFDQ96qk6ri3w13xsKwUvy1hk=; b=DZ/tw9bN4WPnATAAXtjhjnDwaw/2Xlzs6YJJE9UWWhlJ9Fm2YsoCJ7r38+HzAqnqT/ yuOqM1pwbupKSgKOI81aDRvHFhn3dzZNix8WONhQtGmletXX17XOKwrhN8KUpQOwHNmz bPo27LzaM8SWaXlozPmoNMol0XBhFLiMRLr7I4KNppw19tc6OXuPlLAP0Xtt7J7ZD85j jzHDgaOrAE+IaWhOSUOVyy7ptl+jFA0DoY5soRr6RTNj3f/F869bsFvE4la4JJmnUcZb ui19K+a6yDPUeWxdiUJKg7UZxVF1ShFt1GAdQS+gIC2s3zunLtD5CCxru7jxcSq5NGec kPMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RREiOKaa; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u65si13960318pfj.218.2019.03.25.01.36.37; Mon, 25 Mar 2019 01:36:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RREiOKaa; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730157AbfCYIgg (ORCPT + 31 others); Mon, 25 Mar 2019 04:36:36 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:54832 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730134AbfCYIgc (ORCPT ); Mon, 25 Mar 2019 04:36:32 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8a4x7106345; Mon, 25 Mar 2019 03:36:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553502964; bh=m/r4pmfH/rvhmKXLXqhFDQ96qk6ri3w13xsKwUvy1hk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RREiOKaaBZjueDGcax1cuROorFpY98z3sXH9V65ZpCDRN7ICv8hND/zKnq6vF+RWT GnZbuLG0EwYXFvlLjy2zthlW0dqvS40Lbu2Pamb7rRyTcEa6yYsYsqnt6bHT047+6r xrkASv4Jj9QU1z+xgv1kzn3kvBQBhFBjhIxawi4g= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8a3YD090923 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:36:04 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:36:02 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:36:02 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFh006534; Mon, 25 Mar 2019 03:35:59 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 01/26] PCI: keystone: Add start_link/stop_link dw_pcie_ops Date: Mon, 25 Mar 2019 14:04:36 +0530 Message-ID: <20190325083501.8088-2-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add start_link/stop_link dw_pcie_ops and invoke ks_pcie_start_link directly from host_init. start_link/stop_link ops is required for adding EP mode support. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 44 +++++++++++------------ 1 file changed, 22 insertions(+), 22 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index b757692e2848..07f55b355d75 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -460,18 +460,33 @@ static int ks_pcie_link_up(struct dw_pcie *pci) return (val == PORT_LOGIC_LTSSM_STATE_L0); } -static void ks_pcie_initiate_link_train(struct keystone_pcie *ks_pcie) +static void ks_pcie_stop_link(struct dw_pcie *pci) { + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); u32 val; /* Disable Link training */ val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); val &= ~LTSSM_EN_VAL; ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); +} + +static int ks_pcie_start_link(struct dw_pcie *pci) +{ + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + struct device *dev = pci->dev; + u32 val; + + if (dw_pcie_link_up(pci)) { + dev_dbg(dev, "link is already up\n"); + return 0; + } /* Initiate Link Training */ val = ks_pcie_app_readl(ks_pcie, CMD_STATUS); ks_pcie_app_writel(ks_pcie, CMD_STATUS, LTSSM_EN_VAL | val); + + return 0; } /** @@ -556,26 +571,6 @@ static void ks_pcie_quirk(struct pci_dev *dev) } DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, ks_pcie_quirk); -static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct device *dev = pci->dev; - - if (dw_pcie_link_up(pci)) { - dev_info(dev, "Link already up\n"); - return 0; - } - - ks_pcie_initiate_link_train(ks_pcie); - - /* check if the link is up or not */ - if (!dw_pcie_wait_for_link(pci)) - return 0; - - dev_err(dev, "phy link never came up\n"); - return -ETIMEDOUT; -} - static void ks_pcie_msi_irq_handler(struct irq_desc *desc) { unsigned int irq = desc->irq_data.hwirq; @@ -813,7 +808,7 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) dw_pcie_setup_rc(pp); - ks_pcie_establish_link(ks_pcie); + ks_pcie_stop_link(pci); ks_pcie_setup_rc_app_regs(ks_pcie); ks_pcie_setup_interrupts(ks_pcie); writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8), @@ -830,6 +825,9 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, "Asynchronous external abort"); + ks_pcie_start_link(pci); + dw_pcie_wait_for_link(pci); + return 0; } @@ -892,6 +890,8 @@ static const struct of_device_id ks_pcie_of_match[] = { }; static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { + .start_link = ks_pcie_start_link, + .stop_link = ks_pcie_stop_link, .link_up = ks_pcie_link_up, }; From patchwork Mon Mar 25 08:34:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161052 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3697995jan; Mon, 25 Mar 2019 01:39:09 -0700 (PDT) X-Google-Smtp-Source: APXvYqwap1eeuyz4DC9Haxd/y19wrjj2KwZIHfd3SV9HJeKAMjTIOpReB7unmbORfuJ4481Dg5sX X-Received: by 2002:a17:902:aa5:: with SMTP id 34mr23011172plp.302.1553503149160; Mon, 25 Mar 2019 01:39:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503149; cv=none; d=google.com; s=arc-20160816; b=Q6G8qsqiddQQNzD7rii5Twz7XlkoYA7pe9ybECEanXAcCp3L+ffV4t7bKTwkXJ95TL IiY79ePYiu1MJsnBR/6ldm+jPEWA90g0Ce3M12lwDOnTnJaQy5K5Y9dljFJyqtcSU8sU sAXc0VSSh3eJkcdrseBilaDdwDQkKAAaVBsdFTdRZcHxtNzS5soBJk5eeCYnsy8nzbhS 4slcjIi20pWpHaj7YBNzCS8/YvzGmuK43tEy6wGK2CKZJ/jmjvJNsZo4FAsERFy9Iyfn 5V0f3Cae29KDyQiC9BorxDPPThgcPONVxAC/JWNEJMUCCWTfWNYQc0fdCht1E5FNJSXR fifQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=TXLdx2SAosMFqyOjlSQie8ZcUaPTkakA6by1/PgLXHo=; b=NbELVD+2GZH8gUD4CsRLURVE7Ki6OUNoq+OdT8lLtLUYmZvqIy/4vmUOhL0PB4dFMp Q64f9pcFyonwkOrc0kHiFPBqvfgW7DCjDDABNTnjLQ3n6lbZtYI8xYrZMtwkj8DFVXLK 648IIxx/0dcDzkiz8SehC69WHuibrOD8ds84peXqVVZRhPacB6UaG2ysZ0moTjn/ejor 4Dx6URkHdnHFqw5TOsJ/mLuTvf+D6N9rQxHuNXhhZ/YLxxZm8TaQSpNZ4fI5Ra39vPMk h8Ko1QoEmhg824BjGnM3vSlldLKEVkQM/W+ZsULGidBGlln8TbiT+2BIERiOhcNp0RhC fquQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=azTQ0AGm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id be11si13340668plb.355.2019.03.25.01.39.08; Mon, 25 Mar 2019 01:39:09 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=azTQ0AGm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730109AbfCYIg3 (ORCPT + 31 others); Mon, 25 Mar 2019 04:36:29 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:54822 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729965AbfCYIg1 (ORCPT ); Mon, 25 Mar 2019 04:36:27 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8aCpZ106411; Mon, 25 Mar 2019 03:36:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553502972; bh=TXLdx2SAosMFqyOjlSQie8ZcUaPTkakA6by1/PgLXHo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=azTQ0AGmsp4+BAkPd/6ewSMKH63GZ0o5P4D6DseFRL5X6k7/6OK84uARHwhUGvdM9 GNrFSEWe+s+zEKD3utzivbVQQDYQF/I615Q+dDOmZyWnimnOIqkqyJ2D+1cwVoabV3 3rVetJZ8kBOnVeVUSXpbQiArpNw2S3Y47XQYVbOg= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8aBWu091356 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:36:11 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:36:11 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:36:11 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFj006534; Mon, 25 Mar 2019 03:36:07 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 03/26] dt-bindings: PCI: keystone: Add "reg-names" binding information Date: Mon, 25 Mar 2019 14:04:38 +0530 Message-ID: <20190325083501.8088-4-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add "reg-names" binding information in order for device tree node to be populated with the correct register strings. This will break old dt compatibility. However Keystone PCI has never worked in upstream kernel due to lack of SERDES support. Before SERDES support is added, cleanup the Keystone PCI dt-bindngs. This new binding will also be used by PCI in AM654 platform. Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 2030ee0dc4f9..3a551687cfa2 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -12,8 +12,10 @@ described here as well as properties that are not applicable. Required Properties:- compatibility: "ti,keystone-pcie" -reg: index 1 is the base address and length of DW application registers. - index 2 is the base address and length of PCI device ID register. +reg: Three register ranges as listed in the reg-names property +reg-names: "dbics" for the DesignWare PCIe registers, "app" for the + TI specific application registers, "config" for the + configuration space address pcie_msi_intc : Interrupt controller device node for MSI IRQ chip interrupt-cells: should be set to 1 From patchwork Mon Mar 25 08:34:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161028 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696053jan; Mon, 25 Mar 2019 01:36:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqyXlqDLPeGuuU2VMXLPVgsA7j0Nu6y+88uQeGaW4ecIDeULSUrAOYxde2HuDh+nbUi11KIQ X-Received: by 2002:a17:902:7044:: with SMTP id h4mr17069467plt.274.1553502994637; Mon, 25 Mar 2019 01:36:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553502994; cv=none; d=google.com; s=arc-20160816; b=Zz4e5gbyOT5nsbnvZyMdgTMwsWTTJ+rBMaL3Z+vcULUXBGx0mVh9GzkWqj2gW8kCwr VSqwst/CMhsaHixN7WJwOPylcNKuMs8Sj/zwiYDVy6NMmeF7HRjRgDCoC8emxQ2Zp+RE LCdT2icdAuY8qvkknu67MHNgBYoFRm+KT+AGUpsiWLgwLMll4acPFYuP0/p6bsa42X5Y SVX3V4k4TkzCIW3f6wnzF5RzO80I7m3AEqJNliPulOZfdPbtMWMUMe/7kG19hmebnnhD 45vJ1FwUvl4PbceABz5Y6zwDquGRmSlwLz/Kfy5gNjTLdvL9TKDDzh3ePSFyMuYQylGH DkkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=eZWnPPDbFVKunrhBYSdXwEOnltBVdXDnI/Xd180x+sM=; b=iqUE6dWPR1ZazwEHOKox5RgnLj3GuFtCezsLUPhlczNaW1gKStXw2fJGZ5NLqxGxIE imCOF5nTU4DVMbhM5mdbBuNBY+Va1s1XwElghWcSN6P8+zmlK1VODEN2Kd+PSqwgEnDd +ugHU+8LXtkAza6GA9BXdsBjtwhsCBlOnG6OL/df6w7O3h+bp7A9a4DoGObZ4f93czqB v0KM2iNrNibfazF9CYEiuAFYSmBiM9C2q4yNDFpGn/6OV7FK/Lzz6kyP7HAWw/sru7s4 2cS6a8oEkkoAXoOcW/b6B3lFvUgwgtvjdzuH/B8mIt8o/otQWABbyx3ekmtHuuW+w+TL 9KIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=sRly1gdd; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u65si13960318pfj.218.2019.03.25.01.36.34; Mon, 25 Mar 2019 01:36:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=sRly1gdd; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730139AbfCYIgc (ORCPT + 31 others); Mon, 25 Mar 2019 04:36:32 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:54828 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730113AbfCYIga (ORCPT ); Mon, 25 Mar 2019 04:36:30 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8aGwQ106444; Mon, 25 Mar 2019 03:36:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553502976; bh=eZWnPPDbFVKunrhBYSdXwEOnltBVdXDnI/Xd180x+sM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=sRly1gddcGmuCaHVueEAMWtAFRCdaHGFZvQJLbzFN+I1TTgNkEYuZE13LiOY93CWf f42gO4IyelV013lb3EeEt+bVPDhogYkD8H1sD6rULYBtpju1oATR7Caw13uAU9Rj/5 L8AHi1l1560BgVltxPKjnWwCiSWNOr4A4qU4+A8E= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8aFl0091521 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:36:15 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:36:15 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:36:15 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFk006534; Mon, 25 Mar 2019 03:36:11 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 04/26] PCI: keystone: Perform host initialization in a single function Date: Mon, 25 Mar 2019 14:04:39 +0530 Message-ID: <20190325083501.8088-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org No functional change. Instead of having two functions ks_pcie_add_pcie_port and ks_pcie_dw_host_init for initializing host, have a single function to perform all the host initialization. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 63 +++++++++-------------- 1 file changed, 23 insertions(+), 40 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index e50f8773e768..566718ea7ebf 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -487,45 +487,6 @@ static int ks_pcie_start_link(struct dw_pcie *pci) return 0; } -/** - * ks_pcie_dw_host_init() - initialize host for v3_65 dw hardware - * - * Ioremap the register resources, initialize legacy irq domain - * and call dw_pcie_v3_65_host_init() API to initialize the Keystone - * PCI host controller. - */ -static int __init ks_pcie_dw_host_init(struct keystone_pcie *ks_pcie) -{ - struct dw_pcie *pci = ks_pcie->pci; - struct pcie_port *pp = &pci->pp; - struct device *dev = pci->dev; - struct platform_device *pdev = to_platform_device(dev); - struct resource *res; - - /* Index 0 is the config reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pci->dbi_base)) - return PTR_ERR(pci->dbi_base); - - /* - * We set these same and is used in pcie rd/wr_other_conf - * functions - */ - pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET; - pp->va_cfg1_base = pp->va_cfg0_base; - - /* Index 1 is the application reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - ks_pcie->va_app_base = devm_ioremap_resource(dev, res); - if (IS_ERR(ks_pcie->va_app_base)) - return PTR_ERR(ks_pcie->va_app_base); - - ks_pcie->app = *res; - - return dw_pcie_host_init(pp); -} - static void ks_pcie_quirk(struct pci_dev *dev) { struct pci_bus *bus = dev->bus; @@ -843,10 +804,32 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct dw_pcie *pci = ks_pcie->pci; struct pcie_port *pp = &pci->pp; struct device *dev = &pdev->dev; + struct resource *res; int ret; + /* Index 0 is the config reg. space address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pci->dbi_base)) + return PTR_ERR(pci->dbi_base); + + /* + * We set these same and is used in pcie rd/wr_other_conf + * functions + */ + pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET; + pp->va_cfg1_base = pp->va_cfg0_base; + + /* Index 1 is the application reg. space address */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + ks_pcie->va_app_base = devm_ioremap_resource(dev, res); + if (IS_ERR(ks_pcie->va_app_base)) + return PTR_ERR(ks_pcie->va_app_base); + + ks_pcie->app = *res; + pp->ops = &ks_pcie_host_ops; - ret = ks_pcie_dw_host_init(ks_pcie); + ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "failed to initialize host\n"); return ret; From patchwork Mon Mar 25 08:34:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161030 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696151jan; Mon, 25 Mar 2019 01:36:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqzTb2bAvhJ0Bq/fiCYteahGRhop/O5CCXKirhb8P8H2TRda+IcU8YfDnd+H5af+VrCAx3Dl X-Received: by 2002:a62:29c6:: with SMTP id p189mr23462007pfp.194.1553503002124; Mon, 25 Mar 2019 01:36:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503002; cv=none; d=google.com; s=arc-20160816; b=rhgl0sisSVe6KqptfZnFYTzwRGtDSJFPdDLSKsU1tTCO7Hz2ZflIW5xX+gyapBX40z w59PJYuENQKMGpgM7gyPM515R+ha4g7Ic8ZhjhbWCpS4IrJeYpwhk/e9jb6rsSweZ2C/ 2+1NMFOur46FBJdH4ffmbD9l6d7t4eA1SEFTcEqoIOQIF/sgTm9Tu8Zld33vGwt0t9ui iuYi7eAOWqm7736A3uxGlM2lKMKTNI0bZdX9xMK/RsQS7vLL63gkuHp7B3XFoiVCRPgK pQpy4VB4UpXWBmoYuCfT0XVeo59o5PmG6nMx9ioOhNMFcTnUIw6NboEQRpGbD6xz+Pvw R0Bg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=8ftV+tyeP19Er0Uqruzv3Zjv2HvQTzbCletDFZ3afkE=; b=bBqf9m2f+K8lnwOCakgpSIVy2c/3wJzfunYPDn4MW1twsyvn+cw5bCW06G6R/7ILfF WaxkEmd335i49uKeUT+5L+QFQSQrQAEZp8Ha1bdpSoMdjQoXl45iZjbmyOJ5uay5mCYN 7SvRjSq7Y8WqUxeDJNSQSb1bPblwsDsdCnDgGF+J9aagIvEkkMpAFNkM5VoUs0qZ6TG1 84YXDEYkwgBfdlhA3EKK0Ndb250TNdXXrQtiWDP/dlwuGyV1MN13NUzJry4+dyWK6k5C psjahZluLzQpIOxTA47zH2CSo2hg0nAlxSlLQ5Vq8rVCPOIlNbRvRXfEzBNMjhoPWtMo oNfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=g1F8xUgE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id l4si12082288pgp.169.2019.03.25.01.36.41; Mon, 25 Mar 2019 01:36:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=g1F8xUgE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730174AbfCYIgk (ORCPT + 31 others); Mon, 25 Mar 2019 04:36:40 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:52224 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730134AbfCYIgi (ORCPT ); Mon, 25 Mar 2019 04:36:38 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8aKsl106108; Mon, 25 Mar 2019 03:36:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553502980; bh=8ftV+tyeP19Er0Uqruzv3Zjv2HvQTzbCletDFZ3afkE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=g1F8xUgElVpNW9N2HFrxlKj+YXeJOYXNCm3GfUArEQMngr/Bc1z0YSVfwQeNPdMmg o8brTMdPFxDDhgB+ZIcZF8x8flfiERBoLzxSJZlGPasdaebG4T2tNwbSrNl+zmu9Jq eQEtM9KAgYIql0uLA+JxLuZAwVLz7X5pObUo7ChU= Received: from DLEE106.ent.ti.com (dlee106.ent.ti.com [157.170.170.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8aKtj016379 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:36:20 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE106.ent.ti.com (157.170.170.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:36:19 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:36:19 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFl006534; Mon, 25 Mar 2019 03:36:16 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 05/26] PCI: keystone: Use platform_get_resource_byname to get memory resources Date: Mon, 25 Mar 2019 14:04:40 +0530 Message-ID: <20190325083501.8088-6-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Use platform_get_resource_byname() instead of platform_get_resource() which uses index to get memory resources. While at that get the memory resource defined specifically for configuration space instead of deriving the configuration space address from dbics address space. Since pci-keystone driver has never worked out of the box in mainline kernel, dt backward compatibility is ignored. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 566718ea7ebf..5eebef9b9ada 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -44,7 +44,6 @@ #define CFG_TYPE1 BIT(24) #define OB_SIZE 0x030 -#define SPACE0_REMOTE_CFG_OFFSET 0x1000 #define OB_OFFSET_INDEX(n) (0x200 + (8 * (n))) #define OB_OFFSET_HI(n) (0x204 + (8 * (n))) #define OB_ENABLEN BIT(0) @@ -807,21 +806,19 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, struct resource *res; int ret; - /* Index 0 is the config reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbics"); pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); - /* - * We set these same and is used in pcie rd/wr_other_conf - * functions - */ - pp->va_cfg0_base = pci->dbi_base + SPACE0_REMOTE_CFG_OFFSET; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); + pp->va_cfg0_base = devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pp->va_cfg0_base)) + return PTR_ERR(pp->va_cfg0_base); + pp->va_cfg1_base = pp->va_cfg0_base; - /* Index 1 is the application reg. space address */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app"); ks_pcie->va_app_base = devm_ioremap_resource(dev, res); if (IS_ERR(ks_pcie->va_app_base)) return PTR_ERR(ks_pcie->va_app_base); From patchwork Mon Mar 25 08:34:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161031 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696198jan; Mon, 25 Mar 2019 01:36:45 -0700 (PDT) X-Google-Smtp-Source: APXvYqxpcIcCfFseuBlzgPC6IRJxHqAaA778bmbh5qKsIxUmo3aFyyHY97frCY76KpEIGf0DSd+x X-Received: by 2002:a63:f74c:: with SMTP id f12mr21933327pgk.124.1553503005553; Mon, 25 Mar 2019 01:36:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503005; cv=none; d=google.com; s=arc-20160816; b=e7gIaBY1saKB3b9LlubcuPkmIS3sRzWeBv10cFAGADK5mhlAkC/c0ZgNMi5vFPEN76 erqBqR2sepbeg7jeVppPhW+LMCgUDtb0f3XH9nTVS/R8hrrf4X/qoqMuddFzbhcUPv/b 9WShk9R+P/3sJ6yeezyB3AgvWOmUUxiWtc/BZMqUnmpCNU/tRzmoZbu5oGa+rypaKosX YSIcygwSevOQ+9cEpIp5TgZARdWfxsAfRG/AMYllsrxAB6XuScTYckeuuJ994h/dBdF7 KdPZLNyY6rUMa33vbg5J+aG36+GGUxqiqJoNgWH5oKJLTY2IxrlF4CvTHzP32e2vK46T n5Ag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Oy9h1kP8jbCXe+8kD93AkYommSwhxCLq/ir/s6HONHk=; b=jpfebaEd9OWpIs+HQJO72y5vn1T9x/WjxtAXUhi94l06JkNt8cNY1vFGgM0DRLV8VU WO2huHD2jPiZBcpbiWRYBNH62p22zTAm678odyzOkH4ciwUTO5f5KljzbeylHJ+EHpnc UeQT0sHEPzpSWINJODEadWs7iaT8SW665uIcCuWCPwSJ6YmLCC43qUb4cZQTByo+hcOo jOsOCtireUPk/XZdB/Ya02QugTwM3LL/E7Di9a3tNPHBl/0tYn9FvZolp+IhUCyqirpa n78JFi0aubwgPDoZx4a4Tft1GpSinyFnNrOrxbSpIqtuCMo/njC6PSlBMH2LKgRCCnOe HTAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=U1BIFWrX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 3a551687cfa2..8ee07197a063 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -23,6 +23,8 @@ pcie_msi_intc : Interrupt controller device node for MSI IRQ chip ti,syscon-pcie-id : phandle to the device control module required to set device id and vendor id. +ti,syscon-pcie-mode : phandle to the device control module required to configure + PCI in either RC mode or EP mode. Example: pcie_msi_intc: msi-interrupt-controller { From patchwork Mon Mar 25 08:34:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161033 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696294jan; Mon, 25 Mar 2019 01:36:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqzke8+P8vUcfec5Gd1c7eJHgz7zTYpxxtHBQexO+UsCpMTyrIo4Y876VendtsOy3R8hPk/A X-Received: by 2002:a62:4602:: with SMTP id t2mr9140225pfa.26.1553503012131; Mon, 25 Mar 2019 01:36:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503012; cv=none; d=google.com; s=arc-20160816; b=EhMTdduCjB/vzh9rtM0wqZDnAu9mgUshd+7p/8VSplPHFgoJzKjDfmna/fvN9taF4V BNBqjqHwe63e1Jgi6DL9JvpJ//NCK7iBANlGD5O+xfjSHDLQJ5JUf+J2aZLJ5T1rRH4v j6JI6lsfv9WZRU2IqIPjPYMnRoUMpMHakBirbvMyOfXOVm+QT5dMbJuLucgCxDKiS+il kSobdyNky8oExmYHPyqxCh0Ut9X3tTO7SM2CHrJTyRPhlrJD09SsN6kmG0rDLqJs22us 7/jolEeHX3L5MUUailuJkSVrc7dp4aTZ+6fQi1LCchCzgp7iW/928dSvRrFSY7r8P5qT SDqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=1lGjasujhkFf/3ytOeLr0WSkR7aiRJac7oOtRyOLFg4=; b=gfqcxioJIhptjN97OBMiiVLmkNWyWw6PVefC6yc38ypntwnGwGIbsZj45IAwLMiotz oJwTRbQ8u62LPjQ+czCbyAmDnyPt5RpPPlvFirnED26VKiO4kBSIwGSNDpsdK9tEvRZH ORBtSrq7T3/FM9dX1wBZr36XzaPBkPpPX8Nv0s2XnGl3mbu7aZDjsvxTc7LgQA0PoamZ 4k/NcaXthpT9SVCgctuOHoK+asPnM3mxd2jm7oTFMzalwkttRuQ+2XbDUgx2vc9FAReX zZvB+3WsY/Ab/xp0P5SagHNK6APxAPBPJIcoTDAr57jd7GxQ0arOuWIHVLP63+7qEp85 6Nvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=epy4Z63n; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id c12si13405643pgk.202.2019.03.25.01.36.51; Mon, 25 Mar 2019 01:36:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=epy4Z63n; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730224AbfCYIgu (ORCPT + 31 others); Mon, 25 Mar 2019 04:36:50 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:36560 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730175AbfCYIgr (ORCPT ); Mon, 25 Mar 2019 04:36:47 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8aXQn039514; Mon, 25 Mar 2019 03:36:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553502993; bh=1lGjasujhkFf/3ytOeLr0WSkR7aiRJac7oOtRyOLFg4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=epy4Z63nyt5E+dqN+5r+2drcrY+NjfxfliFb5nSQRUpqtPKXxxWv/OtGjgZ+XnL8a SoqpZb7W4qxOp3QuoUBqRArJvYnAADeGQxJvWex//LdNjgSk5Rxay9bA52oAf5iNCD a6HbAFE3Xaq52AvwGKvbPOrYa1wNZFuzUxh3ZUYc= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8aXxc091871 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:36:33 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:36:32 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:36:32 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFo006534; Mon, 25 Mar 2019 03:36:28 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 08/26] PCI: keystone: Explicitly set the PCIe mode Date: Mon, 25 Mar 2019 14:04:43 +0530 Message-ID: <20190325083501.8088-9-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Explicitly set the PCIe mode to BOOTCFG_DEVCFG instead of always relying on the default values. This is required when EP mode has to be explicitly written to BOOTCFG_DEVCFG register. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 37 +++++++++++++++++++++++ 1 file changed, 37 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 95997885a05c..dfe54553d832 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -79,6 +79,15 @@ #define PCIE_RC_K2L 0xb00a #define PCIE_RC_K2G 0xb00b +#define KS_PCIE_DEV_TYPE_MASK (0x3 << 1) +#define KS_PCIE_DEV_TYPE(mode) ((mode) << 1) + +#define EP 0x0 +#define LEG_EP 0x1 +#define RC 0x2 + +#define KS_PCIE_SYSCLOCKOUTEN BIT(0) + #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) struct keystone_pcie { @@ -876,6 +885,30 @@ static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) return ret; } +static int ks_pcie_set_mode(struct device *dev) +{ + struct device_node *np = dev->of_node; + struct regmap *syscon; + u32 val; + u32 mask; + int ret = 0; + + syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); + if (IS_ERR(syscon)) + return 0; + + mask = KS_PCIE_DEV_TYPE_MASK | KS_PCIE_SYSCLOCKOUTEN; + val = KS_PCIE_DEV_TYPE(RC) | KS_PCIE_SYSCLOCKOUTEN; + + ret = regmap_update_bits(syscon, 0, mask, val); + if (ret) { + dev_err(dev, "failed to set pcie mode\n"); + return ret; + } + + return 0; +} + static int __init ks_pcie_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -988,6 +1021,10 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } + ret = ks_pcie_set_mode(dev); + if (ret < 0) + goto err_get_sync; + ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) goto err_get_sync; From patchwork Mon Mar 25 08:34:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161036 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696558jan; Mon, 25 Mar 2019 01:37:14 -0700 (PDT) X-Google-Smtp-Source: APXvYqzh85Rjg2+DJRDA/+2V/6o0/ZMggJtrtyP8QKcXDJQqwRxvNlbo95lvWzgou/wAOQ33i3oT X-Received: by 2002:a62:4e8a:: with SMTP id c132mr22346074pfb.24.1553503034299; Mon, 25 Mar 2019 01:37:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503034; cv=none; d=google.com; s=arc-20160816; b=CrbPC5wUe/Irl1HDIShWMlIxDwy7wHaYwjzkoB8npBMMQG8IJbmE8APjbtO17d5vSa 3Bzgd8j4x45976As+Tg99CzSpsmR2dJIQHGxgRMzuyMLaXuCGhndAcgxwqpye0Awf1oD VLrxRVZ0HDwOvRmZsF0Ik01YbKkCbC/kQwbSMbx0lFSjzPJ5sluEyPI1DMtVeBF/4D2K pv3/dmxJnDW4a8iY1tSKKoUy5/rIQch4aWjoTBpZ1OjozR+h4OZNOG3NJcoAM+3S2OZ1 9NIoL/t728c8ByKjnebY3evO7ZHW/lUMJ+LDPQ7l4IEaP29STnq5AsMqRkaabNIBhf0y l6BA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=opMCiGPkYZm6/8E3Wl0dThxDMvrUVywCg5P4fMf+/IA=; b=UJlPCXnhwtb4GpJu4aEPWdjvKxyHfv0mS7E59vCd6w5/CN106ogc3beepBxcWwCatr ScYqHaRwXib4SeCVqP/54jGEvFNPn2cen5Ihn6uUSN8q0lG0XLzQWUOfsDd4kV5ZDCl7 PW70CMhVDNQd7q2JED/T9MC+B9tbEkIoK5OYZvJTPo8S7WZsi79r84qwRkIcArMGa+xe AGgJ3jhN0jjhzRnm/YLfGL9TEwVQXYxoCyi800+IbVrrOXVNcXQFZOuqBNj4Po+wPEuq +T71cH/awAQs9pL0IrPRzXu6ioCrlXfBUGUPXJjHoVHUk80xSDNukiLx31/O2cERkGXh jobA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="kPQIPx/U"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u5si13080602pgi.162.2019.03.25.01.37.14; Mon, 25 Mar 2019 01:37:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="kPQIPx/U"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730277AbfCYIhN (ORCPT + 31 others); Mon, 25 Mar 2019 04:37:13 -0400 Received: from lelv0142.ext.ti.com ([198.47.23.249]:54906 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730246AbfCYIhI (ORCPT ); Mon, 25 Mar 2019 04:37:08 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8afY8106641; Mon, 25 Mar 2019 03:36:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553503001; bh=opMCiGPkYZm6/8E3Wl0dThxDMvrUVywCg5P4fMf+/IA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kPQIPx/UDDci6RiYgjXPaKVdYpLX5WScnkwFrs4fuBVhsCYgSkWKT4RqnIUqBFZCn Rf2KUjQ8BgWH1VI9v1VetbYcwWjOjYlVl8LW8IllCLIqDWTpBmwbgfh/2HfF1rZom7 9/klJkdyMB+3DEPh4mRmjHp571yjUA6OiMBjkaMY= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8afOL092022 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:36:41 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:36:41 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:36:41 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFq006534; Mon, 25 Mar 2019 03:36:37 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 10/26] PCI: dwc: Enable iATU unroll for endpoint too Date: Mon, 25 Mar 2019 14:04:45 +0530 Message-ID: <20190325083501.8088-11-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org iatu_unroll_enabled flag is set only for Designware in host mode. However iATU unroll can be applicable for endpoint mode too. Set iatu_unroll_enabled flag in dw_pcie_setup which is common for both host mode and endpoint mode. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/dwc/pcie-designware-ep.c | 4 ---- .../pci/controller/dwc/pcie-designware-host.c | 19 ------------------- drivers/pci/controller/dwc/pcie-designware.c | 19 +++++++++++++++++++ 3 files changed, 19 insertions(+), 23 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 24f5a775ad34..dc6a4bbd3ace 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -517,10 +517,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) dev_err(dev, "dbi_base/dbi_base2 is not populated\n"); return -EINVAL; } - if (pci->iatu_unroll_enabled && !pci->atu_base) { - dev_err(dev, "atu_base is not populated\n"); - return -EINVAL; - } ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows); if (ret < 0) { diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 7e0ff7d428a9..7bf6558341b6 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -608,17 +608,6 @@ static struct pci_ops dw_pcie_ops = { .write = dw_pcie_wr_conf, }; -static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) -{ - u32 val; - - val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); - if (val == 0xffffffff) - return 1; - - return 0; -} - void dw_pcie_setup_rc(struct pcie_port *pp) { u32 val, ctrl, num_ctrls; @@ -672,14 +661,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp) * we should not program the ATU here. */ if (!pp->ops->rd_other_conf) { - /* Get iATU unroll support */ - pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); - dev_dbg(pci->dev, "iATU unroll: %s\n", - pci->iatu_unroll_enabled ? "enabled" : "disabled"); - - if (pci->iatu_unroll_enabled && !pci->atu_base) - pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; - dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0, PCIE_ATU_TYPE_MEM, pp->mem_base, pp->mem_bus_addr, pp->mem_size); diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 31f6331ca46f..a14ca00f72aa 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -339,6 +339,17 @@ int dw_pcie_link_up(struct dw_pcie *pci) (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING))); } +static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci) +{ + u32 val; + + val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT); + if (val == 0xffffffff) + return 1; + + return 0; +} + void dw_pcie_setup(struct dw_pcie *pci) { int ret; @@ -347,6 +358,14 @@ void dw_pcie_setup(struct dw_pcie *pci) struct device *dev = pci->dev; struct device_node *np = dev->of_node; + /* Get iATU unroll support */ + pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); + dev_dbg(pci->dev, "iATU unroll: %s\n", + pci->iatu_unroll_enabled ? "enabled" : "disabled"); + + if (pci->iatu_unroll_enabled && !pci->atu_base) + pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; + ret = of_property_read_u32(np, "num-lanes", &lanes); if (ret) lanes = 0; From patchwork Mon Mar 25 08:34:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161039 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696709jan; Mon, 25 Mar 2019 01:37:26 -0700 (PDT) X-Google-Smtp-Source: APXvYqxaXymuEuXZbqnpOvQ0ceOwKjBT9r9FbdneXXJX6HMi/Db9mlJHUSP37V+IOOTyTR9eSBpe X-Received: by 2002:a17:902:d715:: with SMTP id w21mr22836856ply.14.1553503046396; Mon, 25 Mar 2019 01:37:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503046; cv=none; d=google.com; s=arc-20160816; b=mqYu5+2sYXedo4pYVwj8E+YKaOYsbJEaJj/gENkfJTw9KOoN6b0+T4wWetN+pZw9fn bm1vjoBatEKFja8HGhurNFvetII3ekRaD+nuKULymmTvlzHa6fdYDCf83GuVvxQRWnQk 1qlB9cIczaYv/dG4+0rT3iiRMmOFKgJ64TrOPTKcspAo5om+QIzopexScTYBgb1QfX3Y /NO1H6b7aF+SI/dqhbcDxjBmpUhXca01v3emBB8iPcGFTr9twxCoFaBR58G5uxgbICZd r7B+gDpJ5KgG5CgnKp1qP3ysr/FAWKjU55bOXJFp8XucOnFRw54GacndUmHce9gMxbMe J5hQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=Z5FsYHz2+eCaWuP/Fr5+/R+9oCvd7mzmcItqNVxbMQU=; b=Fuec3iSFfJnr2d20XkAr49f4plxUIAs6NqS0t76o+LgGuodVIWJI2OmIZKnb2c+S7h Lt6hbWMi9ERTw0oIqg4HkHfkNRi7Ca28bHBdPGNd5tEo48ag0bocfDbf2KHuBQKb8ZYW 2nVCH75dKy3fwAmQIEVLERk8aC6e9biqlUbbfpdZ0Knu6+0tWvIV1WSy85J+/jSeEmHP yp/etnon6k5QMInM5GdZHVfFfF8MFgEErAojdNAR4IBxF0NEzLITNDV1nLrLSBPzSd/A Nm1ZXWmO8SS6K2i5TI3Pv9cdx4j9Wpmqqi1J3NZfi3L8QX0vKVmI2z7uzIs9nOpJ8cc1 KjoA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gJQ+yQEX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g4si12669079pgs.579.2019.03.25.01.37.26; Mon, 25 Mar 2019 01:37:26 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gJQ+yQEX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730325AbfCYIhY (ORCPT + 31 others); Mon, 25 Mar 2019 04:37:24 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:33998 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730289AbfCYIhW (ORCPT ); Mon, 25 Mar 2019 04:37:22 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8ajCH030863; Mon, 25 Mar 2019 03:36:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553503005; bh=Z5FsYHz2+eCaWuP/Fr5+/R+9oCvd7mzmcItqNVxbMQU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gJQ+yQEXu9b9udaGcXG/OL3a15kiZaOfNPDu/VsuhsuN6DIQKF95A4ZvkeBHbwcj4 CMMO1rzAXxQv3TpHNKOyoNXCjEWuAyJRgfqKl8B4YuHmXjwt9PixjFrFCgT1pWnXZl 0QUHwk+cx+rnM/yv9NWELUBCtGYJ7jt6dY1W/6mU= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8ajHU088947 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:36:45 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:36:45 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:36:45 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFr006534; Mon, 25 Mar 2019 03:36:41 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 11/26] PCI: dwc: Fix ATU identification for designware version >= 4.80 Date: Mon, 25 Mar 2019 14:04:46 +0530 Message-ID: <20190325083501.8088-12-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Synopsys designware version >= 4.80 uses a separate register space for programming ATU. The current code identifies if there exists a separate register space by accessing the register address of ATUs in designware version < 4.80. Accessing this address results in abort in the case of K2G. Fix it here by adding "version" member to struct dw_pcie. This should be set by platform specific drivers and designware core will use it to identify if the platform has a separate ATU space. For platforms which hasn't populated the version member, the old method of identification will still be used. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware.c | 14 ++++++++------ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 9 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index a14ca00f72aa..4e2f7946da89 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -358,13 +358,15 @@ void dw_pcie_setup(struct dw_pcie *pci) struct device *dev = pci->dev; struct device_node *np = dev->of_node; - /* Get iATU unroll support */ - pci->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pci); - dev_dbg(pci->dev, "iATU unroll: %s\n", - pci->iatu_unroll_enabled ? "enabled" : "disabled"); + if (pci->version >= 0x480A || (!pci->version && + dw_pcie_iatu_unroll_enabled(pci))) { + pci->iatu_unroll_enabled = true; + if (!pci->atu_base) + pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; + } + dev_dbg(pci->dev, "iATU unroll: %s\n", pci->iatu_unroll_enabled ? + "enabled" : "disabled"); - if (pci->iatu_unroll_enabled && !pci->atu_base) - pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; ret = of_property_read_u32(np, "num-lanes", &lanes); if (ret) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index ca3a3190a6f5..90a5b1215344 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -234,6 +234,7 @@ struct dw_pcie { struct pcie_port pp; struct dw_pcie_ep ep; const struct dw_pcie_ops *ops; + unsigned int version; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) From patchwork Mon Mar 25 08:34:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161035 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696525jan; Mon, 25 Mar 2019 01:37:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqwh524JISXTgvtweUdc91aw9++pUxlgpIwriTMpgKaMFZEPAJN2nFRXhhH2NYsprlJX1oO/ X-Received: by 2002:a63:6fc1:: with SMTP id k184mr9712824pgc.239.1553503031464; Mon, 25 Mar 2019 01:37:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503031; cv=none; d=google.com; s=arc-20160816; b=koxdrWHQZM/n1f/DxJYPlEy3/SbsJ37QoEs6aXSSC5Uk6xWWFQnmU/DN6ehl/WRfH1 FUrKaoGj8B7Q5twZrEBfbGRCs5qPSZpUfgXdqdLi/ixt57U2XbqtPXYENwmJaqSXEN0I Lrder7lV7t3AVcHlXbe+pwzrK+Y5NFiR2ympYYX9Gkp8gWaGDdMw06ktypcMVintFX7D rdr67KFm4RUt/bf+jB5MP40+95lGx8kVlEf+5AiFIWNhKrT1GljApwXVjpFylfxOUZV9 GucxlX133V2ivIKr2FiAHrYI4xj1ywiHDAJlxfGFm4KzyuLUxEOkJNa7dSSPhE354Nu+ 0X1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=QQnbdjchjriqY7MOSz5Hvpx/cYkzjC8wC0YfZRMaepc=; b=iNE/SlC6XPK5zBGmHCvUHq3GhPr22ZBYkbnicU466mPDHp36aOt+cGjQSLSva4c1p6 9S+nD6j1A+TcUMSJFDhPAodYiXBjWu9/bnx0xsNPcWN3GzFURNqnsZajvnroBOFfoP72 9UiE6JnU3vQEU4a522ICd6WbKoY3q/DcohARHofqHlvVrjtmgi4Xk/ya6yH8J2n3lKqi NsIR8pfPhF7FlYYstLDx5lb7Xclt8+alFULW+gvv2isH6VnX3yx4ImE+Ye3/KqrMxADD F3IL6fmLzxs97zy5FfAPaWNdZ1cG+F4EQKQy8xgG69HKdkpbxON5tF2eE09OJL5/4ouv ljgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wsjy9X5h; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u5si13080602pgi.162.2019.03.25.01.37.11; Mon, 25 Mar 2019 01:37:11 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=wsjy9X5h; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730258AbfCYIhJ (ORCPT + 31 others); Mon, 25 Mar 2019 04:37:09 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:36634 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726207AbfCYIhH (ORCPT ); Mon, 25 Mar 2019 04:37:07 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8aouR039638; Mon, 25 Mar 2019 03:36:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553503010; bh=QQnbdjchjriqY7MOSz5Hvpx/cYkzjC8wC0YfZRMaepc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=wsjy9X5hpudLUlezpxjcI0n4ctExu9X3P0yG3a/mwGns8iM0J17YmMadMLRrcY8zF v3Q5dG3QzpdYkhHVKNjVZ+OFP+9/O14zPo3WdsLiBsUpivP4o5jX2HCRf8ngkM/seO sxrOFIZoGb4VHzIwJQgkLMbBBd8YpHWt1Fss7w0c= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8aoRM088988 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:36:50 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:36:49 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:36:49 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFs006534; Mon, 25 Mar 2019 03:36:45 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 12/26] PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 Date: Mon, 25 Mar 2019 14:04:47 +0530 Message-ID: <20190325083501.8088-13-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org hook_fault_code is an ARM32 specific API for hooking into data abort. Since pci-keystone.c will be used for AM65X platforms which is an ARM64 platform, allow hook_fault_code to be compiled only for ARM32. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index dfe54553d832..93296d434f40 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -710,6 +710,7 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) return ret; } +#ifdef CONFIG_ARM /* * When a PCI device does not exist during config cycles, keystone host gets a * bus error instead of returning 0xffffffff. This handler always returns 0 @@ -729,6 +730,7 @@ static int ks_pcie_fault(unsigned long addr, unsigned int fsr, return 0; } +#endif static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) { @@ -778,12 +780,14 @@ static int __init ks_pcie_host_init(struct pcie_port *pp) if (ret < 0) return ret; +#ifdef CONFIG_ARM /* * PCIe access errors that result into OCP errors are caught by ARM as * "External aborts" */ hook_fault_code(17, ks_pcie_fault, SIGBUS, 0, "Asynchronous external abort"); +#endif ks_pcie_start_link(pci); dw_pcie_wait_for_link(pci); From patchwork Mon Mar 25 08:34:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161037 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696581jan; Mon, 25 Mar 2019 01:37:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqw04o15OQtiRFGHyOfKQxqKK99Jn9fn24VFbMGyf7rRRKoIOI7U/D+W447OsiD80dHtqepz X-Received: by 2002:a62:4754:: with SMTP id u81mr23183401pfa.66.1553503036246; Mon, 25 Mar 2019 01:37:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503036; cv=none; d=google.com; s=arc-20160816; b=NiqiOLQhm9F0hwqMOZHmiMaAsSjnrMQ9l+a0dJXOzrOHScGPFuQ5cG0/TdQNsl2hCB 9HXvKhQ0PvCgvo3luGkQzUbFDpPytFxTSZBlSL4cWQcyoPsZcaYqc+C/ydjZsF9mQeV0 bEv35zg9BPXtklh65FMDOE7AeOQwLR8PjWkXzifw8M4mfhOTDUdMnrFs5MCRFhF1XQn2 lHY4kXM9lRiWznbJiQqlhhsoeqsfKpnxTVl+bMvq1H5WElRgIfevE7aljjsCrCjCcE5A UotE93s08Px6BeYFhIIsOF18y0OON6m+ZkdkXY9H+v7yFaBEY8gj4G3j9Fj7vnHWX7XG LQlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=dX0AnoHumpKjN/Hxuc1DnDN/uBYu6jOtQe3dNmu6KNI=; b=Fj8kzNevDPpiB0v51wAdyMDIMH+VxpAmU8zYvM8aDhFMmSlBxAEprdymr0z9AVeZFU Jzh1Wzfc0lNhBbAMkIU0voG6XvR5JgW2A0r682YQRsgRd+Z100WwiA4cz/eJoRwfAaSK QMT3G6cdZb4bSJYWbWPHfzXJ4E6F8W6TyoW2xMv4/ngDiqWfuxTp+IDDbZ0lQW7X9GqL vstNIqruSQNg9EIlv+eUQ9RVuw+p7rCYP8TsjvBXTVKwFtHaVOPTPYTgp1Aswl13K6S7 73TCUPTPufHlo8qcE1DukbFhEW6M0rHTDNSpAwzRh2vQXsmFxYgmn21XBDfXQuzEqp+4 mkFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=RBUxVVPN; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/pci-keystone.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt index 8ee07197a063..5c60e911b8b1 100644 --- a/Documentation/devicetree/bindings/pci/pci-keystone.txt +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt @@ -11,7 +11,8 @@ described here as well as properties that are not applicable. Required Properties:- -compatibility: "ti,keystone-pcie" +compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC + Should be "ti,am654-pcie-rc" for RC on AM654x SoC reg: Three register ranges as listed in the reg-names property reg-names: "dbics" for the DesignWare PCIe registers, "app" for the TI specific application registers, "config" for the @@ -20,6 +21,9 @@ reg-names: "dbics" for the DesignWare PCIe registers, "app" for the pcie_msi_intc : Interrupt controller device node for MSI IRQ chip interrupt-cells: should be set to 1 interrupts: GIC interrupt lines connected to PCI MSI interrupt lines + (required if the compatible is "ti,keystone-pcie") +msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt + (required if the compatible is "ti,am654-pcie-rc". ti,syscon-pcie-id : phandle to the device control module required to set device id and vendor id. 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Mon, 25 Mar 2019 03:36:58 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFu006534; Mon, 25 Mar 2019 03:36:54 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 14/26] PCI: keystone: Add support for PCIe RC in AM654x Platforms Date: Mon, 25 Mar 2019 14:04:49 +0530 Message-ID: <20190325083501.8088-15-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add PCIe RC support for AM654x Platforms in pci-keystone.c Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/Kconfig | 2 +- drivers/pci/controller/dwc/pci-keystone.c | 161 ++++++++++++++++++++-- 2 files changed, 148 insertions(+), 15 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 6ea74b1c0d94..d1d00833e0b3 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -104,7 +104,7 @@ config PCIE_SPEAR13XX config PCI_KEYSTONE bool "TI Keystone PCIe controller" - depends on ARCH_KEYSTONE || (ARM && COMPILE_TEST) + depends on ARCH_KEYSTONE || ARCH_K3 || ((ARM || ARM64) && COMPILE_TEST) depends on PCI_MSI_IRQ_DOMAIN select PCIE_DW_HOST help diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 93296d434f40..a6a482bd648f 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -18,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -65,6 +67,7 @@ #define ERR_IRQ_STATUS 0x1c4 #define ERR_IRQ_ENABLE_SET 0x1c8 #define ERR_AER BIT(5) /* ECRC error */ +#define AM6_ERR_AER BIT(4) /* AM6 ECRC error */ #define ERR_AXI BIT(4) /* AXI tag lookup fatal error */ #define ERR_CORR BIT(3) /* Correctable error */ #define ERR_NONFATAL BIT(2) /* Non-fatal error */ @@ -88,8 +91,15 @@ #define KS_PCIE_SYSCLOCKOUTEN BIT(0) +#define AM654_PCIE_DEV_TYPE_MASK 0x3 + #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) +struct ks_pcie_of_data { + const struct dw_pcie_host_ops *host_ops; + unsigned int version; +}; + struct keystone_pcie { struct dw_pcie *pci; /* PCI Device ID */ @@ -109,6 +119,7 @@ struct keystone_pcie { /* Application register space */ void __iomem *va_app_base; /* DT 1st resource */ struct resource app; + bool is_am6; }; static u32 ks_pcie_app_readl(struct keystone_pcie *ks_pcie, u32 offset) @@ -250,6 +261,16 @@ static void ks_pcie_handle_legacy_irq(struct keystone_pcie *ks_pcie, ks_pcie_app_writel(ks_pcie, IRQ_EOI, offset); } +static int ks_pcie_am654_msi_host_init(struct pcie_port *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct device *dev = pci->dev; + + dev_vdbg(dev, "dummy function so that DW core doesn't configure MSI\n"); + + return 0; +} + static void ks_pcie_enable_error_irq(struct keystone_pcie *ks_pcie) { ks_pcie_app_writel(ks_pcie, ERR_IRQ_ENABLE_SET, ERR_IRQ_ALL); @@ -276,10 +297,10 @@ static irqreturn_t ks_pcie_handle_error_irq(struct keystone_pcie *ks_pcie) if (reg & ERR_CORR) dev_dbg(dev, "Correctable Error\n"); - if (reg & ERR_AXI) + if (!ks_pcie->is_am6 && (reg & ERR_AXI)) dev_err(dev, "AXI tag lookup fatal Error\n"); - if (reg & ERR_AER) + if (reg & ERR_AER || (ks_pcie->is_am6 && (reg & AM6_ERR_AER))) dev_err(dev, "ECRC Error\n"); ks_pcie_app_writel(ks_pcie, ERR_IRQ_STATUS, reg); @@ -377,6 +398,9 @@ static void ks_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); ks_pcie_clear_dbi_mode(ks_pcie); + if (ks_pcie->is_am6) + return; + val = ilog2(OB_WIN_SIZE); ks_pcie_app_writel(ks_pcie, OB_SIZE, val); @@ -619,6 +643,8 @@ static int ks_pcie_config_msi_irq(struct keystone_pcie *ks_pcie) intc_np = of_get_child_by_name(np, "msi-interrupt-controller"); if (!intc_np) { + if (ks_pcie->is_am6) + return 0; dev_warn(dev, "msi-interrupt-controller node is absent\n"); return -EINVAL; } @@ -668,6 +694,12 @@ static int ks_pcie_config_legacy_irq(struct keystone_pcie *ks_pcie) intc_np = of_get_child_by_name(np, "legacy-interrupt-controller"); if (!intc_np) { + /* + * Since legacy interrupts are modeled as edge-interrupts in + * AM6, keep it disabled for now. + */ + if (ks_pcie->is_am6) + return 0; dev_warn(dev, "legacy-interrupt-controller node is absent\n"); return -EINVAL; } @@ -749,8 +781,10 @@ static int __init ks_pcie_init_id(struct keystone_pcie *ks_pcie) if (ret) return ret; + dw_pcie_dbi_ro_wr_en(pci); dw_pcie_writew_dbi(pci, PCI_VENDOR_ID, id & PCIE_VENDORID_MASK); dw_pcie_writew_dbi(pci, PCI_DEVICE_ID, id >> PCIE_DEVICEID_SHIFT); + dw_pcie_dbi_ro_wr_dis(pci); return 0; } @@ -803,6 +837,11 @@ static const struct dw_pcie_host_ops ks_pcie_host_ops = { .scan_bus = ks_pcie_v3_65_scan_bus, }; +static const struct dw_pcie_host_ops ks_pcie_am654_host_ops = { + .host_init = ks_pcie_host_init, + .msi_host_init = ks_pcie_am654_msi_host_init, +}; + static irqreturn_t ks_pcie_err_irq_handler(int irq, void *priv) { struct keystone_pcie *ks_pcie = priv; @@ -826,7 +865,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, pp->va_cfg1_base = pp->va_cfg0_base; - pp->ops = &ks_pcie_host_ops; ret = dw_pcie_host_init(pp); if (ret) { dev_err(dev, "failed to initialize host\n"); @@ -836,14 +874,6 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, return 0; } -static const struct of_device_id ks_pcie_of_match[] = { - { - .type = "pci", - .compatible = "ti,keystone-pcie", - }, - { }, -}; - static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { .start_link = ks_pcie_start_link, .stop_link = ks_pcie_stop_link, @@ -913,14 +943,67 @@ static int ks_pcie_set_mode(struct device *dev) return 0; } +static int ks_pcie_am654_set_mode(struct device *dev) +{ + struct device_node *np = dev->of_node; + struct regmap *syscon; + u32 val; + u32 mask; + int ret = 0; + + syscon = syscon_regmap_lookup_by_phandle(np, "ti,syscon-pcie-mode"); + if (IS_ERR(syscon)) + return 0; + + mask = AM654_PCIE_DEV_TYPE_MASK; + val = RC; + + ret = regmap_update_bits(syscon, 0, mask, val); + if (ret) { + dev_err(dev, "failed to set pcie mode\n"); + return ret; + } + + return 0; +} + +static const struct ks_pcie_of_data ks_pcie_rc_of_data = { + .host_ops = &ks_pcie_host_ops, + .version = 0x365A, +}; + +static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { + .host_ops = &ks_pcie_am654_host_ops, + .version = 0x490A, +}; + +static const struct of_device_id ks_pcie_of_match[] = { + { + .type = "pci", + .data = &ks_pcie_rc_of_data, + .compatible = "ti,keystone-pcie", + }, + { + .data = &ks_pcie_am654_rc_of_data, + .compatible = "ti,am654-pcie-rc", + }, + { }, +}; + static int __init ks_pcie_probe(struct platform_device *pdev) { + const struct dw_pcie_host_ops *host_ops; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; + const struct ks_pcie_of_data *data; + const struct of_device_id *match; struct dw_pcie *pci; struct keystone_pcie *ks_pcie; struct device_link **link; + struct gpio_desc *gpiod; + void __iomem *atu_base; struct resource *res; + unsigned int version; void __iomem *base; u32 num_viewport; struct phy **phy; @@ -930,6 +1013,14 @@ static int __init ks_pcie_probe(struct platform_device *pdev) int irq; int i; + match = of_match_device(of_match_ptr(ks_pcie_of_match), dev); + data = (struct ks_pcie_of_data *)match->data; + if (!data) + return -EINVAL; + + version = data->version; + host_ops = data->host_ops; + ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); if (!ks_pcie) return -ENOMEM; @@ -950,9 +1041,13 @@ static int __init ks_pcie_probe(struct platform_device *pdev) if (IS_ERR(base)) return PTR_ERR(base); + if (of_device_is_compatible(np, "ti,am654-pcie-rc")) + ks_pcie->is_am6 = true; + pci->dbi_base = base; pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops; + pci->version = version; ret = of_property_read_u32(np, "num-viewport", &num_viewport); if (ret < 0) { @@ -1011,6 +1106,15 @@ static int __init ks_pcie_probe(struct platform_device *pdev) ks_pcie->num_viewport = num_viewport; ks_pcie->phy = phy; + gpiod = devm_gpiod_get_optional(dev, "reset", + GPIOD_OUT_LOW); + if (IS_ERR(gpiod)) { + ret = PTR_ERR(gpiod); + if (ret != -EPROBE_DEFER) + dev_err(dev, "Failed to get reset GPIO\n"); + goto err_link; + } + ret = ks_pcie_enable_phy(ks_pcie); if (ret) { dev_err(dev, "failed to enable phy\n"); @@ -1025,10 +1129,39 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } - ret = ks_pcie_set_mode(dev); - if (ret < 0) - goto err_get_sync; + if (pci->version >= 0x480A) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); + atu_base = devm_ioremap_resource(dev, res); + if (IS_ERR(atu_base)) { + ret = PTR_ERR(atu_base); + goto err_get_sync; + } + + pci->atu_base = atu_base; + + ret = ks_pcie_am654_set_mode(dev); + if (ret < 0) + goto err_get_sync; + } else { + ret = ks_pcie_set_mode(dev); + if (ret < 0) + goto err_get_sync; + } + + /* + * "Power Sequencing and Reset Signal Timings" table in + * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 + * indicates PERST# should be deasserted after minimum of 100us + * once REFCLK is stable. The REFCLK to the connector in RC + * mode is selected while enabling the PHY. So deassert PERST# + * after 100 us. + */ + if (gpiod) { + usleep_range(100, 200); + gpiod_set_value_cansleep(gpiod, 1); + } + pci->pp.ops = host_ops; ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) goto err_get_sync; From patchwork Mon Mar 25 08:34:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161038 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696630jan; Mon, 25 Mar 2019 01:37:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqwutZrCpIpWml5gl9uRBkH4wPBOVgYamoRfIjM/nxVvAPH+P03ba+VLvYBeuFbwVtEphIPP X-Received: by 2002:a63:d706:: with SMTP id d6mr21218195pgg.367.1553503040034; Mon, 25 Mar 2019 01:37:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503040; cv=none; d=google.com; s=arc-20160816; b=hsifqDDiH0GDxSkubVLbcbGWc8V9Gv8TTHL7VJBjZ7n8jCsh0ERljC6dsEhnEUt8zw f7pZ44I6lCgP2jg2z/NMqQ243hXUJRh5z98JlACzoCb1ipulYc+q7VjBsYbKDVYZGKGI Dc+/lJbw2oiqi7uVZf3pvScmFWPW2fIGaYIVJgfciHpkA49IK02zZC74JPCms+eXg1kS tMIHpRl9epQF6MdDpy5RrAn72128jic8OUK2bP6HfVoiSkgPySJMSeMSxhjELz0pgzAT lniG0wAM3Nu/9eZW7EMpBUdPkBWKVH7aFQHjEIsHI6ULHv3ktCL6pYTbVtrS70n+teuu hmrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=9+2eOM3oSY0oLj93leiipPk6vycQ1SmzvQwVGhiyl5g=; b=SR+1afbDrAP0lKHarRK41bDZDNpXX6dsggpo2OCNRR1G0pUMJ72JTfZ8sBGOoAst/Z bxPqLaEW0bN5/jlmsLquF968DmcCM9yEWq9rbf+pt2GJSxH7m6+kfioHYND+SU+RJgmm bCQ3wNcRfkwA1JUxp+2AO+7SQQVP4TG6K8cgWzAeAk7AR0ilqPu2Y03YyVjSFdJazpF2 ZCoofnAaJVnvVBqlsKnQtdZOQy7eqepHjdVpv9dUt/TSFztMee2OpXOnmTytoudpF31E MRRTljm+FPVDLgn4VrUiHINAZqF7uVEey0aBCat0ScTm+uWKYpEdSel0H0p5m3tvQ/+O wqpA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=IoaIWNfL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u5si13080602pgi.162.2019.03.25.01.37.19; Mon, 25 Mar 2019 01:37:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=IoaIWNfL; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730306AbfCYIhS (ORCPT + 31 others); Mon, 25 Mar 2019 04:37:18 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:33980 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730289AbfCYIhP (ORCPT ); Mon, 25 Mar 2019 04:37:15 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8b3qD030975; Mon, 25 Mar 2019 03:37:03 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553503023; bh=9+2eOM3oSY0oLj93leiipPk6vycQ1SmzvQwVGhiyl5g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IoaIWNfLZqrC1CFmioiRHCzpk/z8u0zdxswV61Nh96AOAACivPQIpx8xiA7X6nTDF qRQct3PEzSXvTQEeG0iYrSfFZ8Nn0YEBY7rAVh1Z04udUbS5Hrtt/L1OSOPy5IsTBR 20pVXY5dnOVnkdkNNAWHj8bxAvRUdQttJU3cic+E= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8b2I7053481 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:37:03 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:37:02 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:37:02 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFv006534; Mon, 25 Mar 2019 03:36:58 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 15/26] PCI: keystone: Invoke phy_reset API before enabling PHY Date: Mon, 25 Mar 2019 14:04:50 +0530 Message-ID: <20190325083501.8088-16-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SERDES connected to the PCIe controller in AM654 requires power on reset enable (POR_EN) to be set in the SERDES. The SERDES driver sets POR_EN in the reset ops and it has to be invoked before init or enable ops. In order for SERDES driver to set POR_EN, invoke phy_reset API in pci-keystone driver. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 4 ++++ 1 file changed, 4 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index a6a482bd648f..e4a816f53b8e 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -897,6 +897,10 @@ static int ks_pcie_enable_phy(struct keystone_pcie *ks_pcie) int num_lanes = ks_pcie->num_lanes; for (i = 0; i < num_lanes; i++) { + ret = phy_reset(ks_pcie->phy[i]); + if (ret < 0) + goto err_phy; + ret = phy_init(ks_pcie->phy[i]); if (ret < 0) goto err_phy; From patchwork Mon Mar 25 08:34:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161044 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696981jan; Mon, 25 Mar 2019 01:37:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqw6YBrQloWeHnizBJqWq7LhXIwd6NIRaXmkx83e7HjLJiVUdlEVlxeI763kbH5ChDpUz+Fn X-Received: by 2002:a63:5ec2:: with SMTP id s185mr21909906pgb.27.1553503066633; Mon, 25 Mar 2019 01:37:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503066; cv=none; d=google.com; s=arc-20160816; b=QddqN8iFDLo/1MdUVduLuvIKS5QchFZ9WruqmdhYpl8AESmh8D7lObbKX7Ul6Kf9Ug NOATo+mffHCPDb/3BhDakktpbyN24pI7ypWetvgy02+F0HJMbIV1C1L1LukuDnMl6ia1 lBsSIYGBypLvZAI1vlQcAvCyrHJlmpPaZ5tUU97JMExzX6fn7l6OmCyHbZPQtNp49HRL 8gzEpciMBbE7ix6c4Udb2WX+H43cS558ITDCe6C0Np38k3IvVzOmVnnMffg+D6BPTKoi NruVcIdMPNGcmS8dKvar1A03SqqxcmkDhEknOxo9CNIvZ47/6a0uEVoQ+UWm7xQCC8TF 1x1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=dFVQ4pidiC5cYCJgE2pe5Ra71CSY84AMLd39Zm5xel0=; b=hIFLF9jHg8DXwSv+36hShdlPhOLHtK2BPrUdKkSQkou0DpX2VOuyx+pRpvxauFxMbm P+Yy03FGxmGfk4OOf1lpxCBXNlK+NtMQzbAkMzmD/Ai2GklshUCrY5XtKgwHcH6ur7L5 JLn2DJ+l35oNZcVmJWAbxzn4kiUFp3mBB4WZpyEggiZoj5CKSag/tGmoRcsn+5dHyu1r SCAG5dQIdAKRn+Ao2hysYnEaObE02hGdtv9hfgTep1Raq2SxnjAKcVvCq5kJ/8/BFBDn 6jYCa5bJ371xcJ10GBwXviOh+WQILbkJG43hOcnkOr2v/N6UO4W29Q+Fx3Tmcfh5firy dSJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=bvvOX3aP; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y6si13174734plk.126.2019.03.25.01.37.46; Mon, 25 Mar 2019 01:37:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=bvvOX3aP; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730405AbfCYIhp (ORCPT + 31 others); Mon, 25 Mar 2019 04:37:45 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:34064 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730384AbfCYIhm (ORCPT ); Mon, 25 Mar 2019 04:37:42 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8b7pY031019; Mon, 25 Mar 2019 03:37:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553503027; bh=dFVQ4pidiC5cYCJgE2pe5Ra71CSY84AMLd39Zm5xel0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=bvvOX3aPuVG2CgTj2NbwKfTkRdjvgSBQ6CFdQo8emOS3EcdAGZ/ZIFDU/gbvGXzTY CwClzWFSqxrwEGPG6D07Z78bRYnpcG6+zPpJZIk2MvYUpc2bFqBoKk6/9TvKc04fgJ BGEROm5xFWM04gDwSGxhs2z9VfJ6N9fGLahK/bVM= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8b7lm092499 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:37:07 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:37:06 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:37:06 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFw006534; Mon, 25 Mar 2019 03:37:02 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , , Sekhar Nori Subject: [PATCH v2 16/26] PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers Date: Mon, 25 Mar 2019 14:04:51 +0530 Message-ID: <20190325083501.8088-17-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org of_pci_get_max_link_speed() is built only if CONFIG_PCI is enabled. Make of_pci_get_max_link_speed() to be also used by PCI Endpoint controllers with just CONFIG_PCI_ENDPOINT enabled. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- drivers/pci/Makefile | 2 +- drivers/pci/of.c | 44 +++++++++++++++++++++++--------------------- 2 files changed, 24 insertions(+), 22 deletions(-) -- 2.17.1 diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 657d642fcc67..28cdd8c0213a 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -10,10 +10,10 @@ obj-$(CONFIG_PCI) += access.o bus.o probe.o host-bridge.o \ ifdef CONFIG_PCI obj-$(CONFIG_PROC_FS) += proc.o obj-$(CONFIG_SYSFS) += slot.o -obj-$(CONFIG_OF) += of.o obj-$(CONFIG_ACPI) += pci-acpi.o endif +obj-$(CONFIG_OF) += of.o obj-$(CONFIG_PCI_QUIRKS) += quirks.o obj-$(CONFIG_PCIEPORTBUS) += pcie/ obj-$(CONFIG_HOTPLUG_PCI) += hotplug/ diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 3d32da15c215..8095933f8452 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -15,6 +15,7 @@ #include #include "pci.h" +#ifdef CONFIG_PCI void pci_set_of_node(struct pci_dev *dev) { if (!dev->bus->dev.of_node) @@ -196,27 +197,6 @@ int of_get_pci_domain_nr(struct device_node *node) } EXPORT_SYMBOL_GPL(of_get_pci_domain_nr); -/** - * This function will try to find the limitation of link speed by finding - * a property called "max-link-speed" of the given device node. - * - * @node: device tree node with the max link speed information - * - * Returns the associated max link speed from DT, or a negative value if the - * required property is not found or is invalid. - */ -int of_pci_get_max_link_speed(struct device_node *node) -{ - u32 max_link_speed; - - if (of_property_read_u32(node, "max-link-speed", &max_link_speed) || - max_link_speed > 4) - return -EINVAL; - - return max_link_speed; -} -EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed); - /** * of_pci_check_probe_only - Setup probe only mode if linux,pci-probe-only * is present and valid @@ -537,3 +517,25 @@ int pci_parse_request_of_pci_ranges(struct device *dev, return err; } +#endif /* CONFIG_PCI */ + +/** + * This function will try to find the limitation of link speed by finding + * a property called "max-link-speed" of the given device node. + * + * @node: device tree node with the max link speed information + * + * Returns the associated max link speed from DT, or a negative value if the + * required property is not found or is invalid. + */ +int of_pci_get_max_link_speed(struct device_node *node) +{ + u32 max_link_speed; + + if (of_property_read_u32(node, "max-link-speed", &max_link_speed) || + max_link_speed > 4) + return -EINVAL; + + return max_link_speed; +} +EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed); From patchwork Mon Mar 25 08:34:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161040 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696755jan; Mon, 25 Mar 2019 01:37:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqwXzWGACtA2CZTpNwMP7YK43RK8hatNJE46bKiQ9e6Nk05iW3nyq48J7Igk95GYVReExIc3 X-Received: by 2002:a17:902:4101:: with SMTP id e1mr24537229pld.25.1553503050311; Mon, 25 Mar 2019 01:37:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503050; cv=none; d=google.com; s=arc-20160816; b=gCr5lf/cWBuqjHAg3UQKyeyiita+A8ejuoiTDfQAVwyRvfZGnRSJTJ2yQWWqbGxa7P El+tZl3nuCqZKI0/TaQex1jyaznQkvLYlvGN7tpB6VlGtOTfe+GsRTztwjMmzMz3F/Pd t9YGvr+ohn/0Ba9z068xHhf6lE3MUXCj9BFxudSwIuTVZae/+uPHho2lSOJqowEpEsU0 /CXosOU0o8Tch3ygUAa19R2SxRY9Zfc2ZZN3GVlu0hW//TUSOfbh/v6OJLfOi50dibIr Pi1Fc2P60estJpR2hjYKlKvKT8n7JvJnBVDJB1+IEPrsWodD5ctK5JdZHn71/NJmwejh a/fg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=chMDM1S73N5348Ke4wiey3wF6sgdC3UveRlW6BwAUuY=; b=T0NjYptwVNAOoEZUdpqve5rrLk29JJ3VHiDg12rpd/ICztqaX/Rx5YdoHX22j+MCmE 0RcOOK4kq9Zm+eFdWbreTjG3X176djpjto9DDqQC9mfb0APQTixnyv398SDurVJ6kzbQ 7Br1Fki+QLV+3qY0kHKtAO+SXzdfwwe18zMqXJa7OAtUFrbwZew46hEHpN7K56/9dAe5 s5y62A/HMqHkoeTe/paIIn8Fn/9LG/CfxQJqLSIpIraiopLkKSVyAigeIXsaRkdTWQan ij0ag7xwH2n+85cA6hrfLgF8XBOaQx9e3U4LvYtu8ek9UE2x7ie3xU1Y9TffMyTMILr2 eDKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Ke9kO7Mr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g4si12669079pgs.579.2019.03.25.01.37.30; Mon, 25 Mar 2019 01:37:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Ke9kO7Mr; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729985AbfCYIh2 (ORCPT + 31 others); Mon, 25 Mar 2019 04:37:28 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:36682 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730323AbfCYIhY (ORCPT ); Mon, 25 Mar 2019 04:37:24 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8bBjV039834; Mon, 25 Mar 2019 03:37:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553503031; bh=chMDM1S73N5348Ke4wiey3wF6sgdC3UveRlW6BwAUuY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Ke9kO7MrjIUhvbMmukZbWdEHyvEo7M3LIS+G7eg0BaR0QBDlF0PonhhK8+xZClZzx 24oWqUPuyTU4GwFQllys/7ZWLRmmfjwTmoynfxyliQkvqKiUWGP93cIh5m2SPgx5ZK vdw9ae3vGe/D3k7lFm+f7135VhOXn+bG4eWplxCQ= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8bBNN089549 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:37:11 -0500 Received: from DLEE111.ent.ti.com (157.170.170.22) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:37:11 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:37:11 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsFx006534; Mon, 25 Mar 2019 03:37:07 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 17/26] PCI: keystone: Add support to set the max link speed from DT Date: Mon, 25 Mar 2019 14:04:52 +0530 Message-ID: <20190325083501.8088-18-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org PCIe in TI's AM654 devices is by default configured to work in GEN3 mode. However PCIe doesn't work reliably in GEN3 mode because of SERDES configuration. Add support to set the link speed to GEN1, GEN2 or GEN3 based on "max-link-speed" dt property with GEN2 as the default speed if "max-link-speed" is absent. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pci-keystone.c | 35 +++++++++++++++++++++++ 1 file changed, 35 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index e4a816f53b8e..312fd0c49bbb 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -28,6 +28,7 @@ #include #include +#include "../../pci.h" #include "pcie-designware.h" #define PCIE_VENDORID_MASK 0xffff @@ -89,6 +90,8 @@ #define LEG_EP 0x1 #define RC 0x2 +#define EXP_CAP_ID_OFFSET 0x70 + #define KS_PCIE_SYSCLOCKOUTEN BIT(0) #define AM654_PCIE_DEV_TYPE_MASK 0x3 @@ -971,6 +974,31 @@ static int ks_pcie_am654_set_mode(struct device *dev) return 0; } +static void ks_pcie_set_link_speed(struct dw_pcie *pci, int link_speed) +{ + u32 val; + + dw_pcie_dbi_ro_wr_en(pci); + + val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP); + if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) { + val &= ~((u32)PCI_EXP_LNKCAP_SLS); + val |= link_speed; + dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCAP, + val); + } + + val = dw_pcie_readl_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2); + if ((val & PCI_EXP_LNKCAP_SLS) != link_speed) { + val &= ~((u32)PCI_EXP_LNKCAP_SLS); + val |= link_speed; + dw_pcie_writel_dbi(pci, EXP_CAP_ID_OFFSET + PCI_EXP_LNKCTL2, + val); + } + + dw_pcie_dbi_ro_wr_dis(pci); +} + static const struct ks_pcie_of_data ks_pcie_rc_of_data = { .host_ops = &ks_pcie_host_ops, .version = 0x365A, @@ -1011,6 +1039,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) void __iomem *base; u32 num_viewport; struct phy **phy; + int link_speed; u32 num_lanes; char name[10]; int ret; @@ -1165,6 +1194,12 @@ static int __init ks_pcie_probe(struct platform_device *pdev) gpiod_set_value_cansleep(gpiod, 1); } + link_speed = of_pci_get_max_link_speed(np); + if (link_speed < 0) + link_speed = 2; + + ks_pcie_set_link_speed(pci, link_speed); + pci->pp.ops = host_ops; ret = ks_pcie_add_pcie_port(ks_pcie, pdev); if (ret < 0) From patchwork Mon Mar 25 08:34:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161041 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3696802jan; Mon, 25 Mar 2019 01:37:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqyEVdowmDStYLpZaZPuRg+xnq8QijlNt8VCVAIyoYRwc2eac219kNscvP59wiMFhfJaP4ET X-Received: by 2002:a62:574d:: with SMTP id l74mr23515153pfb.9.1553503053552; Mon, 25 Mar 2019 01:37:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503053; cv=none; d=google.com; s=arc-20160816; b=TE0X9P7eQyz6VS0Dbn6OdsoTH2iSqswgOkOoQAvlZgMYUTdGK26YYfly30uiHy9xpq OFXBBL7Ww2niAcWRAI54invIqquUYdbPhNxL+S0EupsYz8qIbdJP/LOAwncW+bYbXLEO T7GI7ms+5kRmHLqFNnlTn9jhmWSuGp3juqDNjW/x/CtzxNsDO/siFRrFLGrMPAcq7Kps CIvKOXx5Vhlx6A3Ozh6ASK3FcyeVNYYtTDcEqQizyhPva/dsCcvBN1bwga8TD9wXDyTb 1nSaPVePW8e4KzFtXd+cjUAxAWo165oDS43KxpcIZYlVFlb5c3YQf/tsCUQ+W+z6Jp36 yzTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=FQifuCUrENL8NGdaDyObLGabN5HL+zMUVCN85TUbVgM=; b=0LVvNLA9Yb4V3f6nkILg4/+oBqwmI0tGj+8x8EFFCzUbeJu7NKvTVLFYoj8PKBvnnh hkDdsAWRP3JdlV1eBjmKoJ0th+M1OeXn3kuH7Wbu04mhieOFHnFhdb7h5MFXZsw9QDI6 SB+oOcQqGOfo9oRgXpIbQHDWb/rgSMpLM23k7W2w8tSEhIL6q151uCKfvxIxjXNF+bzg /dyZEf+6f8q/a7iP/1tWCKLFr3bjOHCng4TPh1D9O0ogLvodkYhCN7b62yWiIz3ctd+R aVn/mvWoCVtQ/pF6pJ7daHmYBO9eDJJND4Tr06XpwWCpfeOUpb/0EerS1fyi8WpHAwsa 7azg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="dRMx/GDi"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id u18si3014560pgk.469.2019.03.25.01.37.33; Mon, 25 Mar 2019 01:37:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="dRMx/GDi"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730354AbfCYIhb (ORCPT + 31 others); Mon, 25 Mar 2019 04:37:31 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:34024 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730339AbfCYIh2 (ORCPT ); Mon, 25 Mar 2019 04:37:28 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8bF24031066; Mon, 25 Mar 2019 03:37:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553503035; bh=FQifuCUrENL8NGdaDyObLGabN5HL+zMUVCN85TUbVgM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=dRMx/GDiA9rKvNYZYFZjWHS5a9DhHERda7h0wJYPZn0r47pNqLVOy1e0XsQ33P0rJ HCCc6tG61ay4nem8l7yCgqz9wVky3/keBkouXk9Iz+uyA36s8H8a/3igsLJE6TyKd2 Q/d5E6SH8Zsz+sXgHGeF3oSMsG6XvJRi50tGB0Q0= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8bFcx017630 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:37:15 -0500 Received: from DLEE105.ent.ti.com (157.170.170.35) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:37:15 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:37:14 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsG0006534; Mon, 25 Mar 2019 03:37:11 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 18/26] PCI: endpoint: Add support to allocate aligned buffers to be mapped in BARs Date: Mon, 25 Mar 2019 14:04:53 +0530 Message-ID: <20190325083501.8088-19-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Modify pci_epf_alloc_space API to take alignment size as argument in order to argument in order to allocate aligned buffers to be mapped to BARs. Add 'align' parameter to epc_features which can be used by platform drivers to specifiy the BAR allocation alignment requirements and use this while invoking pci_epf_alloc_space. This is mainly required for Synopsys Designware PCIe core which masks the lower bits based on the BAR size (See "I/O and MEM Match Modes" section in DesignWare Cores PCI Express Controller Databook version 4.90a). Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/functions/pci-epf-test.c | 5 +++-- drivers/pci/endpoint/pci-epf-core.c | 10 ++++++++-- include/linux/pci-epc.h | 2 ++ include/linux/pci-epf.h | 3 ++- 4 files changed, 15 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index d0b91da49bf4..c0786ca74312 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -438,7 +438,7 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf) epc_features = epf_test->epc_features; base = pci_epf_alloc_space(epf, sizeof(struct pci_epf_test_reg), - test_reg_bar); + test_reg_bar, epc_features->align); if (!base) { dev_err(dev, "Failed to allocated register space\n"); return -ENOMEM; @@ -453,7 +453,8 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf) if (!!(epc_features->reserved_bar & (1 << bar))) continue; - base = pci_epf_alloc_space(epf, bar_size[bar], bar); + base = pci_epf_alloc_space(epf, bar_size[bar], bar, + epc_features->align); if (!base) dev_err(dev, "Failed to allocate space for BAR%d\n", bar); diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index 8bfdcd291196..fb1306de8f40 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -109,10 +109,12 @@ EXPORT_SYMBOL_GPL(pci_epf_free_space); * pci_epf_alloc_space() - allocate memory for the PCI EPF register space * @size: the size of the memory that has to be allocated * @bar: the BAR number corresponding to the allocated register space + * @align: alignment size for the allocation region * * Invoke to allocate memory for the PCI EPF register space. */ -void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar) +void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, + size_t align) { void *space; struct device *dev = epf->epc->dev.parent; @@ -120,7 +122,11 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar) if (size < 128) size = 128; - size = roundup_pow_of_two(size); + + if (align) + size = ALIGN(size, align); + else + size = roundup_pow_of_two(size); space = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL); if (!space) { diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index c3ffa3917f88..f641badc2c61 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -109,6 +109,7 @@ struct pci_epc { * @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver * @bar_fixed_64bit: bitmap to indicate fixed 64bit BARs * @bar_fixed_size: Array specifying the size supported by each BAR + * @align: alignment size required for BAR buffer allocation */ struct pci_epc_features { unsigned int linkup_notifier : 1; @@ -117,6 +118,7 @@ struct pci_epc_features { u8 reserved_bar; u8 bar_fixed_64bit; u64 bar_fixed_size[BAR_5 + 1]; + size_t align; }; #define to_pci_epc(device) container_of((device), struct pci_epc, dev) diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index ec02f58758c8..2d6f07556682 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -149,7 +149,8 @@ void pci_epf_destroy(struct pci_epf *epf); int __pci_epf_register_driver(struct pci_epf_driver *driver, struct module *owner); void pci_epf_unregister_driver(struct pci_epf_driver *driver); -void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar); +void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, + size_t align); void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar); int pci_epf_bind(struct pci_epf *epf); void pci_epf_unbind(struct pci_epf *epf); From patchwork Mon Mar 25 08:34:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161045 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3697063jan; Mon, 25 Mar 2019 01:37:54 -0700 (PDT) X-Google-Smtp-Source: APXvYqwi1pcTmw9R2lk9EPVIPr4WmZuMSgOxG4wx+lNcZIXmzTmUYUorLuQ5zh8vmNpIVNDrTKMR X-Received: by 2002:a17:902:7044:: with SMTP id h4mr17073949plt.274.1553503074154; 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[209.132.180.67]) by mx.google.com with ESMTP id u9si12864071pgp.269.2019.03.25.01.37.53; Mon, 25 Mar 2019 01:37:54 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=DiU7+pdX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730076AbfCYIhw (ORCPT + 31 others); Mon, 25 Mar 2019 04:37:52 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:52388 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730012AbfCYIht (ORCPT ); Mon, 25 Mar 2019 04:37:49 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8bSiI106731; Mon, 25 Mar 2019 03:37:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553503048; bh=mRZ/N3tIORcVcdf8U0MRLHXGRFmU8jONue5muhGax30=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DiU7+pdX8DwYX/IK1tcEm694NGt19dsDWnA7hYwR/wFML+l2gmI6hw6hiZnBxBqwr 4RYeLHxzdOQST4Sdw4a6GXHXRclqT79ZdStJPYFZfwOuLvt/OcZA8InP/r6giJrRSw PcOZLVSC3p6n576wOEmMnaE7wRHjWvGD/Us/DzBE= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8bSMV017860 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:37:28 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:37:28 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:37:28 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsG3006534; Mon, 25 Mar 2019 03:37:24 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 21/26] PCI: dwc: Add callbacks for accessing dbi2 address space Date: Mon, 25 Mar 2019 14:04:56 +0530 Message-ID: <20190325083501.8088-22-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Certain platforms like TI's AM654 doesn't have separate address space for dbi2 instead they are accessed using the same address space as dbi with some configuration bit set. In order to support such platforms, add callbacks for accessing dbi2 address space. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware.c | 31 ++++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 12 ++++++-- 2 files changed, 41 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 4e2f7946da89..d7cc1a0c1de6 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -89,6 +89,37 @@ void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, dev_err(pci->dev, "Write DBI address failed\n"); } +u32 __dw_pcie_read_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size) +{ + int ret; + u32 val; + + if (pci->ops->read_dbi2) + return pci->ops->read_dbi2(pci, base, reg, size); + + ret = dw_pcie_read(base + reg, size, &val); + if (ret) + dev_err(pci->dev, "read DBI address failed\n"); + + return val; +} + +void __dw_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size, u32 val) +{ + int ret; + + if (pci->ops->write_dbi2) { + pci->ops->write_dbi2(pci, base, reg, size, val); + return; + } + + ret = dw_pcie_write(base + reg, size, val); + if (ret) + dev_err(pci->dev, "write DBI address failed\n"); +} + static u32 dw_pcie_readl_ob_unroll(struct dw_pcie *pci, u32 index, u32 reg) { u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index e36941ff7cf6..7abca9eb00bf 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -218,6 +218,10 @@ struct dw_pcie_ops { size_t size); void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg, size_t size, u32 val); + u32 (*read_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, + size_t size); + void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, + size_t size, u32 val); int (*link_up)(struct dw_pcie *pcie); int (*start_link)(struct dw_pcie *pcie); void (*stop_link)(struct dw_pcie *pcie); @@ -249,6 +253,10 @@ u32 __dw_pcie_read_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size); void __dw_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, u32 reg, size_t size, u32 val); +u32 __dw_pcie_read_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size); +void __dw_pcie_write_dbi2(struct dw_pcie *pci, void __iomem *base, u32 reg, + size_t size, u32 val); int dw_pcie_link_up(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); void dw_pcie_prog_outbound_atu(struct dw_pcie *pci, int index, @@ -292,12 +300,12 @@ static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg) static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val) { - __dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, val); + __dw_pcie_write_dbi2(pci, pci->dbi_base2, reg, 0x4, val); } static inline u32 dw_pcie_readl_dbi2(struct dw_pcie *pci, u32 reg) { - return __dw_pcie_read_dbi(pci, pci->dbi_base2, reg, 0x4); + return __dw_pcie_read_dbi2(pci, pci->dbi_base2, reg, 0x4); } static inline void dw_pcie_writel_atu(struct dw_pcie *pci, u32 reg, u32 val) From patchwork Mon Mar 25 08:34:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161046 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3697206jan; Mon, 25 Mar 2019 01:38:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqxpNOivj1lFRLKuItquldqRYpDWBA4g2LOtgEiBCpc5xxTU79uyw40TuyCmd/3troHutqhs X-Received: by 2002:a63:1d03:: with SMTP id d3mr22162301pgd.42.1553503087448; Mon, 25 Mar 2019 01:38:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503087; cv=none; d=google.com; s=arc-20160816; b=ac0q2t73d51/f2SJo2dnysKkIhtG8hSF9DOLjvDUC/1/LTI3OU2sV95YyJg9ucAl0/ uN4DbEKyDAYY9A/jFVeBoL+AlI10SYErhqncIysDRYGF9EGKrSk6qVIzhBAJMjWlK6zg jkxjwN+VepD7aGggRyU/jxEBvGVhAgHbtsS5DvN5RlWhxFvPdRkIDVP7ydEJZLjMFLeG 0mCpqbs1a6KvwoK1KXjIIBLM46f7hXt+8fRb7eHV4AZrhl9MEv3Jvap1mPigqyjHxqW9 d8s+1Nba2nV0iSFE4dsiGJg2ODbjq5BMD3KRah6QPjiCbyeuu/Ltkm8LA7aW5NNf30dr qm6w== ARC-Message-Signature: i=1; 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The PCI controller on Keystone is based on DesignWare hardware and therefore the driver re-uses the DesignWare core functions to implement the driver. +if PCI_KEYSTONE + +config PCI_KEYSTONE_HOST + bool "PCI Keystone Host Mode" + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + default y + help + Enables support for the PCIe controller in the Keystone SoC to work in + host mode. + +config PCI_KEYSTONE_EP + bool "PCI Keystone Endpoint Mode" + depends on PCI_ENDPOINT + select PCIE_DW_EP + help + Enables support for the PCIe controller in the Keystone SoC to work in + endpoint mode. + +endif + config PCI_LAYERSCAPE bool "Freescale Layerscape PCIe controller" depends on OF && (ARM || ARCH_LAYERSCAPE || COMPILE_TEST) diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c index 312fd0c49bbb..459485b0f65d 100644 --- a/drivers/pci/controller/dwc/pci-keystone.c +++ b/drivers/pci/controller/dwc/pci-keystone.c @@ -52,6 +52,12 @@ #define OB_ENABLEN BIT(0) #define OB_WIN_SIZE 8 /* 8MB */ +#define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1))) +#define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1))) +#define PCIE_EP_IRQ_SET 0x64 +#define PCIE_EP_IRQ_CLR 0x68 +#define INT_ENABLE BIT(0) + /* IRQ register defines */ #define IRQ_EOI 0x050 @@ -95,11 +101,16 @@ #define KS_PCIE_SYSCLOCKOUTEN BIT(0) #define AM654_PCIE_DEV_TYPE_MASK 0x3 +#define AM654_WIN_SIZE SZ_64K + +#define APP_ADDR_SPACE_0 (16 * SZ_1K) #define to_keystone_pcie(x) dev_get_drvdata((x)->dev) struct ks_pcie_of_data { + enum dw_pcie_device_mode mode; const struct dw_pcie_host_ops *host_ops; + const struct dw_pcie_ep_ops *ep_ops; unsigned int version; }; @@ -877,12 +888,139 @@ static int __init ks_pcie_add_pcie_port(struct keystone_pcie *ks_pcie, return 0; } +static u32 ks_pcie_am654_read_dbi2(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size) +{ + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + u32 val; + + ks_pcie_set_dbi_mode(ks_pcie); + dw_pcie_read(base + reg, size, &val); + ks_pcie_clear_dbi_mode(ks_pcie); + return val; +} + +static void ks_pcie_am654_write_dbi2(struct dw_pcie *pci, void __iomem *base, + u32 reg, size_t size, u32 val) +{ + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + + ks_pcie_set_dbi_mode(ks_pcie); + dw_pcie_write(base + reg, size, val); + ks_pcie_clear_dbi_mode(ks_pcie); +} + static const struct dw_pcie_ops ks_pcie_dw_pcie_ops = { .start_link = ks_pcie_start_link, .stop_link = ks_pcie_stop_link, .link_up = ks_pcie_link_up, + .read_dbi2 = ks_pcie_am654_read_dbi2, + .write_dbi2 = ks_pcie_am654_write_dbi2, }; +static void ks_pcie_am654_ep_init(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + int flags; + + ep->page_size = AM654_WIN_SIZE; + flags = PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_32; + dw_pcie_writel_dbi2(pci, PCI_BASE_ADDRESS_0, APP_ADDR_SPACE_0 - 1); + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, flags); +} + +static void ks_pcie_am654_raise_legacy_irq(struct keystone_pcie *ks_pcie) +{ + struct dw_pcie *pci = ks_pcie->pci; + u8 int_pin; + + int_pin = dw_pcie_readb_dbi(pci, PCI_INTERRUPT_PIN); + if (int_pin == 0 || int_pin > 4) + return; + + ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_SET(int_pin), + INT_ENABLE); + ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_SET, INT_ENABLE); + mdelay(1); + ks_pcie_app_writel(ks_pcie, PCIE_EP_IRQ_CLR, INT_ENABLE); + ks_pcie_app_writel(ks_pcie, PCIE_LEGACY_IRQ_ENABLE_CLR(int_pin), + INT_ENABLE); +} + +static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + enum pci_epc_irq_type type, + u16 interrupt_num) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); + + switch (type) { + case PCI_EPC_IRQ_LEGACY: + ks_pcie_am654_raise_legacy_irq(ks_pcie); + break; + case PCI_EPC_IRQ_MSI: + dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + break; + default: + dev_err(pci->dev, "UNKNOWN IRQ type\n"); + return -EINVAL; + } + + return 0; +} + +static const struct pci_epc_features ks_pcie_am654_epc_features = { + .linkup_notifier = false, + .msi_capable = true, + .msix_capable = false, + .reserved_bar = 1 << BAR_0 | 1 << BAR_1, + .bar_fixed_64bit = 1 << BAR_0, + .bar_fixed_size[2] = SZ_1M, + .bar_fixed_size[3] = SZ_64K, + .bar_fixed_size[4] = 256, + .bar_fixed_size[5] = SZ_1M, + .align = SZ_1M, +}; + +static const struct pci_epc_features* +ks_pcie_am654_get_features(struct dw_pcie_ep *ep) +{ + return &ks_pcie_am654_epc_features; +} + +static const struct dw_pcie_ep_ops ks_pcie_am654_ep_ops = { + .ep_init = ks_pcie_am654_ep_init, + .raise_irq = ks_pcie_am654_raise_irq, + .get_features = &ks_pcie_am654_get_features, +}; + +static int __init ks_pcie_add_pcie_ep(struct keystone_pcie *ks_pcie, + struct platform_device *pdev) +{ + int ret; + struct dw_pcie_ep *ep; + struct resource *res; + struct device *dev = &pdev->dev; + struct dw_pcie *pci = ks_pcie->pci; + + ep = &pci->ep; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); + if (!res) + return -EINVAL; + + ep->phys_base = res->start; + ep->addr_size = resource_size(res); + + ret = dw_pcie_ep_init(ep); + if (ret) { + dev_err(dev, "failed to initialize endpoint\n"); + return ret; + } + + return 0; +} + static void ks_pcie_disable_phy(struct keystone_pcie *ks_pcie) { int num_lanes = ks_pcie->num_lanes; @@ -950,7 +1088,8 @@ static int ks_pcie_set_mode(struct device *dev) return 0; } -static int ks_pcie_am654_set_mode(struct device *dev) +static int ks_pcie_am654_set_mode(struct device *dev, + enum dw_pcie_device_mode mode) { struct device_node *np = dev->of_node; struct regmap *syscon; @@ -963,7 +1102,18 @@ static int ks_pcie_am654_set_mode(struct device *dev) return 0; mask = AM654_PCIE_DEV_TYPE_MASK; - val = RC; + + switch (mode) { + case DW_PCIE_RC_TYPE: + val = RC; + break; + case DW_PCIE_EP_TYPE: + val = EP; + break; + default: + dev_err(dev, "INVALID device type %d\n", mode); + return -EINVAL; + } ret = regmap_update_bits(syscon, 0, mask, val); if (ret) { @@ -1006,6 +1156,13 @@ static const struct ks_pcie_of_data ks_pcie_rc_of_data = { static const struct ks_pcie_of_data ks_pcie_am654_rc_of_data = { .host_ops = &ks_pcie_am654_host_ops, + .mode = DW_PCIE_RC_TYPE, + .version = 0x490A, +}; + +static const struct ks_pcie_of_data ks_pcie_am654_ep_of_data = { + .ep_ops = &ks_pcie_am654_ep_ops, + .mode = DW_PCIE_EP_TYPE, .version = 0x490A, }; @@ -1019,16 +1176,22 @@ static const struct of_device_id ks_pcie_of_match[] = { .data = &ks_pcie_am654_rc_of_data, .compatible = "ti,am654-pcie-rc", }, + { + .data = &ks_pcie_am654_ep_of_data, + .compatible = "ti,am654-pcie-ep", + }, { }, }; static int __init ks_pcie_probe(struct platform_device *pdev) { const struct dw_pcie_host_ops *host_ops; + const struct dw_pcie_ep_ops *ep_ops; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; const struct ks_pcie_of_data *data; const struct of_device_id *match; + enum dw_pcie_device_mode mode; struct dw_pcie *pci; struct keystone_pcie *ks_pcie; struct device_link **link; @@ -1053,6 +1216,8 @@ static int __init ks_pcie_probe(struct platform_device *pdev) version = data->version; host_ops = data->host_ops; + ep_ops = data->ep_ops; + mode = data->mode; ks_pcie = devm_kzalloc(dev, sizeof(*ks_pcie), GFP_KERNEL); if (!ks_pcie) @@ -1078,16 +1243,11 @@ static int __init ks_pcie_probe(struct platform_device *pdev) ks_pcie->is_am6 = true; pci->dbi_base = base; + pci->dbi_base2 = base; pci->dev = dev; pci->ops = &ks_pcie_dw_pcie_ops; pci->version = version; - ret = of_property_read_u32(np, "num-viewport", &num_viewport); - if (ret < 0) { - dev_err(dev, "unable to read *num-viewport* property\n"); - return ret; - } - irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(dev, "missing IRQ resource: %d\n", irq); @@ -1136,7 +1296,6 @@ static int __init ks_pcie_probe(struct platform_device *pdev) ks_pcie->pci = pci; ks_pcie->link = link; ks_pcie->num_lanes = num_lanes; - ks_pcie->num_viewport = num_viewport; ks_pcie->phy = phy; gpiod = devm_gpiod_get_optional(dev, "reset", @@ -1172,7 +1331,7 @@ static int __init ks_pcie_probe(struct platform_device *pdev) pci->atu_base = atu_base; - ret = ks_pcie_am654_set_mode(dev); + ret = ks_pcie_am654_set_mode(dev, mode); if (ret < 0) goto err_get_sync; } else { @@ -1181,29 +1340,58 @@ static int __init ks_pcie_probe(struct platform_device *pdev) goto err_get_sync; } - /* - * "Power Sequencing and Reset Signal Timings" table in - * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 - * indicates PERST# should be deasserted after minimum of 100us - * once REFCLK is stable. The REFCLK to the connector in RC - * mode is selected while enabling the PHY. So deassert PERST# - * after 100 us. - */ - if (gpiod) { - usleep_range(100, 200); - gpiod_set_value_cansleep(gpiod, 1); - } - link_speed = of_pci_get_max_link_speed(np); if (link_speed < 0) link_speed = 2; ks_pcie_set_link_speed(pci, link_speed); - pci->pp.ops = host_ops; - ret = ks_pcie_add_pcie_port(ks_pcie, pdev); - if (ret < 0) - goto err_get_sync; + switch (mode) { + case DW_PCIE_RC_TYPE: + if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_HOST)) { + ret = -ENODEV; + goto err_get_sync; + } + + ret = of_property_read_u32(np, "num-viewport", &num_viewport); + if (ret < 0) { + dev_err(dev, "unable to read *num-viewport* property\n"); + return ret; + } + + /* + * "Power Sequencing and Reset Signal Timings" table in + * PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 2.0 + * indicates PERST# should be deasserted after minimum of 100us + * once REFCLK is stable. The REFCLK to the connector in RC + * mode is selected while enabling the PHY. So deassert PERST# + * after 100 us. + */ + if (gpiod) { + usleep_range(100, 200); + gpiod_set_value_cansleep(gpiod, 1); + } + + ks_pcie->num_viewport = num_viewport; + pci->pp.ops = host_ops; + ret = ks_pcie_add_pcie_port(ks_pcie, pdev); + if (ret < 0) + goto err_get_sync; + break; + case DW_PCIE_EP_TYPE: + if (!IS_ENABLED(CONFIG_PCI_KEYSTONE_EP)) { + ret = -ENODEV; + goto err_get_sync; + } + + pci->ep.ops = ep_ops; + ret = ks_pcie_add_pcie_ep(ks_pcie, pdev); + if (ret < 0) + goto err_get_sync; + break; + default: + dev_err(dev, "INVALID device type %d\n", mode); + } ks_pcie_enable_error_irq(ks_pcie); From patchwork Mon Mar 25 08:34:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161048 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3697318jan; Mon, 25 Mar 2019 01:38:15 -0700 (PDT) X-Google-Smtp-Source: APXvYqzj7YmLCNOUUZyWt1kW4JlTznNeE1ct98C92SV1XbySRwHXRmGx6uusk7AWOOBPudvGrFx4 X-Received: by 2002:a63:e845:: with SMTP id a5mr22013419pgk.246.1553503095876; Mon, 25 Mar 2019 01:38:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503095; cv=none; d=google.com; s=arc-20160816; b=jF4WmCsx5wIYrv7MDOqQoo9Kgzz7B/QZKEi9GTZvTnCO2gEvN/8envIibienadmdO+ fhB0/jhzz8Nf78OyQ07fH5vCK5KYBR9P0e/PKvEGozMUEpmkExbYR7sA1pXqlC4e3b94 L4M8TLf8LMpBq8WRzIkj3qXBj3L9ICngwiBzIf5IZLl9iQbnMN36pd0vm3unswCC+OYp uXUhcJ8BWJz40hLcMaafV5WUalpDz0L5CtYp/LxRU2dG5y/Hi1tApzOxkBI6VK0MkvV8 8czwotm00uh0WGZDsQIM/YOMzdhs0Ia6tZ5HCFZbEqCe/Hq4fNvuDkV8/AtaE/NZnAPf okOQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=q3j+eLddVjEWh3KTfPJhB6vOyzvGXKalq1Td4n5w/YE=; b=IDx9ev3wpRiEpA4+b+v9iCxamHxoVAv3dv84iYAb7MwA9t4e5lB+MkI4jex6Wkx5oB 75UnyzE7fPYDCmyL4+TRVFTm0rNARmL7Bw6FiYsv4rKcmfC/X+WSFu6Z3lFN1y++7NNo jkzJIALViae28Qhj6TFuDl30qi2p2ljfta0est9PbCiSNcJZPSSIFB4TFsA+FMErLS+E Q2zSZiVyPOMaMWPxLIWgadDVNXygujqOb0akrPt71FgWftxRtJHjnbwNmIJ3YyJ4pbGu fkWHttcDO+D/2krEIGY2Gms2IMhfgdu4YGiHQp5LqhDHvol1tJtEg1SReefLd+bqw51I vGqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="CL/HInyt"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b7si12788510pgw.149.2019.03.25.01.38.15; Mon, 25 Mar 2019 01:38:15 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="CL/HInyt"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730451AbfCYIiO (ORCPT + 31 others); Mon, 25 Mar 2019 04:38:14 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:36852 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730012AbfCYIiL (ORCPT ); Mon, 25 Mar 2019 04:38:11 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8bbgt040030; Mon, 25 Mar 2019 03:37:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553503057; bh=q3j+eLddVjEWh3KTfPJhB6vOyzvGXKalq1Td4n5w/YE=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=CL/HInytVykafhYka/XXTXKvqidSBo80CmlUPc1DhcekQ3aSFn6ws/7rSMB55fDmS ic7eK3xzSrs9gZzt+agu33/2NOHHqjDjwKDQpgYOTVtZ0KyKJe5J4UB26Q7M+yJb0/ syEQ/neq/6F6lr1BK3EXPKYjE97BbWuxtxOtb0Aw= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8bbY2093041 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:37:37 -0500 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:37:36 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:37:36 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsG5006534; Mon, 25 Mar 2019 03:37:32 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 23/26] PCI: designware-ep: Configure RESBAR to advertise the smallest size Date: Mon, 25 Mar 2019 14:04:58 +0530 Message-ID: <20190325083501.8088-24-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Configure RESBAR capability to advertise the smallest size (1MB) for couple of reasons. A) Host side resource allocation of BAR fails for larger sizes. B) Endpoint function driver does not allocate memory for all supported sizes in RESBAR capability. If and when there is a usecase required to add more flexibility using RESBAR, this can be revisited. Signed-off-by: Kishon Vijay Abraham I --- .../pci/controller/dwc/pcie-designware-ep.c | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 74477ad7467f..0c208b9bda43 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -504,10 +504,32 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep) pci_epc_mem_exit(epc); } +static unsigned int dw_pcie_ep_find_ext_capability(struct dw_pcie *pci, int cap) +{ + u32 header; + int pos = PCI_CFG_SPACE_SIZE; + + while (pos) { + header = dw_pcie_readl_dbi(pci, pos); + if (PCI_EXT_CAP_ID(header) == cap) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + if (!pos) + break; + } + + return 0; +} + int dw_pcie_ep_init(struct dw_pcie_ep *ep) { + int i; int ret; + u32 reg; void *addr; + unsigned int nbars; + unsigned int offset; struct pci_epc *epc; struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct device *dev = pci->dev; @@ -591,6 +613,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX); + offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR); + if (offset) { + reg = dw_pcie_readl_dbi(pci, offset + PCI_REBAR_CTRL); + nbars = (reg & PCI_REBAR_CTRL_NBAR_MASK) >> + PCI_REBAR_CTRL_NBAR_SHIFT; + + dw_pcie_dbi_ro_wr_en(pci); + for (i = 0; i < nbars; i++, offset += PCI_REBAR_CTRL) + dw_pcie_writel_dbi(pci, offset + PCI_REBAR_CAP, 0x0); + dw_pcie_dbi_ro_wr_dis(pci); + } + dw_pcie_setup(pci); return 0; From patchwork Mon Mar 25 08:34:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161051 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3697679jan; Mon, 25 Mar 2019 01:38:43 -0700 (PDT) X-Google-Smtp-Source: APXvYqwDDlS24oAXWscItn5dzO4rK3ZmxHSRDcu1eXX7QZk+NI8lt7dpZ5HO8SDmrnfl5mBkmt7q X-Received: by 2002:a17:902:2848:: with SMTP id e66mr24465352plb.181.1553503123626; Mon, 25 Mar 2019 01:38:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503123; cv=none; d=google.com; s=arc-20160816; b=aB8saKTWSUzGVqLqH0SDRWJssRzzVjAL42i/JPuy3NskSA9tgMrn2GD4hnoBK/Hg3H jfk0IfqWNu4vLWSvCjRDYoPdqwqGY5pdSkGP3Zv+L7xHaI/7+5uWSUvP4DpIlhaeEUR6 aPoFpOlbq2ysHRuxfMCbdiGlPVJMI49FthkFlY05yVdwOj54Uus8zV44jJVzn8hGO1GK 10ZMOCp9wcipJkYE4n3+sFlBUTjpUhtiPZXJ5BjWkD7OYOIM7Lbmg6IMcIEvN07EKXbi evzYDqbxEZFlF7G+siLiS2JS8vgJCISsVOrMnmEJmoX0LQpxzIgFIvcFYaem89Qlne92 +x5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=c3UBlJ2/J/eUILjH1LmTrngxtCdjzgHiiyV0ibrE7Fc=; b=gQvooKfERQpGRlaVsJlEyZL5PZZebmDGE9EyjOcWpjcxOYoC0dCorN5JhyO64VWjQ+ eJNWpz/n8MtaCH4pejiHXOXrSc7IKerAOeRkHrh70zpdMG7bRtXEnNBZ5NcUQi8B5ACh Fl9vGr6azNdGzQ6jnUaV1yJFpYEaHqnl7w1x5VvKNAJFK6l9Yh/OWorlgVKv2rWxxlmI wsv4fG6hrtywi+yNp2Xk7mahrA0uGfAIdeZQbsJFopTwm4Pv3kLNeOODCAhz/lvVgn5l Y7h8qehWdmGnb789IDXrIyORwqXObMkq8QTb8c1cZ79TYrPlv0LnYkbvf4Q1e8anwqja 75tg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=NqE3o8qc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 141si10413250pgb.178.2019.03.25.01.38.43; Mon, 25 Mar 2019 01:38:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=NqE3o8qc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730456AbfCYIiZ (ORCPT + 31 others); Mon, 25 Mar 2019 04:38:25 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:52500 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730012AbfCYIiW (ORCPT ); Mon, 25 Mar 2019 04:38:22 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8bf8m106815; Mon, 25 Mar 2019 03:37:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553503061; bh=c3UBlJ2/J/eUILjH1LmTrngxtCdjzgHiiyV0ibrE7Fc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NqE3o8qcgqm2HW6kTsHid2Tm+7EFwnjMpb2Pi4nvllaEE3OJBSWE3PVhOOa7voKDn zNE7hB3gb2Z/nZwPcN5gKzUF4mYZF+sMbpu1RBGVPoLOpGcya7au2d7OgQPU+zJogq wX8cSrUoQOuCFx/rHI5jxU3JWFa5hc8zcVhJDHEQ= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8bfPq054520 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:37:41 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:37:40 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:37:40 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsG6006534; Mon, 25 Mar 2019 03:37:37 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 24/26] PCI: designware-ep: Use aligned ATU window for raising MSI interrupts Date: Mon, 25 Mar 2019 14:04:59 +0530 Message-ID: <20190325083501.8088-25-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Certain platforms like K2G reguires the outbound ATU window to be aligned. The alignment size is already present in mem->page_size. Use the alignment size present in mem->page_size to configre a aligned ATU window. In order to raise an interrupt, CPU has to write to address offset from the start of the window unlike before where writes were always to the beginning of the ATU window. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/dwc/pcie-designware-ep.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 0c208b9bda43..2bf5a35c0570 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -397,6 +397,7 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct pci_epc *epc = ep->epc; + unsigned int aligned_offset; u16 msg_ctrl, msg_data; u32 msg_addr_lower, msg_addr_upper, reg; u64 msg_addr; @@ -422,13 +423,15 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, reg = ep->msi_cap + PCI_MSI_DATA_32; msg_data = dw_pcie_readw_dbi(pci, reg); } - msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower; + aligned_offset = msg_addr_lower & (epc->mem->page_size - 1); + msg_addr = ((u64)msg_addr_upper) << 32 | + (msg_addr_lower & ~aligned_offset); ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr, epc->mem->page_size); if (ret) return ret; - writel(msg_data | (interrupt_num - 1), ep->msi_mem); + writel(msg_data | (interrupt_num - 1), ep->msi_mem + aligned_offset); dw_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys); From patchwork Mon Mar 25 08:35:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161050 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3697607jan; Mon, 25 Mar 2019 01:38:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqyDmNasDm7fGqjDhLj2c2YyXxkqjsmS0btyKQ7z0OxzRFA8grlAsn+CgGXPdji2hW5lvTG5 X-Received: by 2002:a63:3190:: with SMTP id x138mr15423368pgx.273.1553503117937; Mon, 25 Mar 2019 01:38:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503117; cv=none; d=google.com; s=arc-20160816; b=rSIg60it9xnqvm78AoAaDJl7oCs0Z3YVB34kp5r9n2t6ixSWWJ13zB4KTzNMnpMk1L ksk0ow7Hpwbe8zxovf4TSAbAf1UKw7isJYfi6nwDqVAO2LuxiWTOuOILSN8nYyHFnw2h KD1o3GrYsgx6b2lUxBc14f1BpVoJ/POqQJTIkM870MSVDYiN7MHaizmzhTwnyQoC9+JK +roLCF97DBGptpr1NFv8Uc2J2UJDlu/3KASVJdMIlM60yHSSLzlG5kNB516pv2OyE/MM bvWpd3y6SesWXQuSOyb2E/CExRycYOcE0/Ohz9SrlbSRo1YaBVnP1dxgL/3tAAR59PhB qwbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ecY/+Ui4SK2VPooZ8MRoP5X7hto+xBrP5+SVRZo/EkI=; b=zbQnPskWHCHh6in5cPxb3SDaaQiQODH0jXoq9V4Ed9Emanwk6K42F/KIixwML8+ZwY 06Q3Wbodq15yBmzWmwJ14U1XNSmU3yiD9mkbjmLU6WkR+4bwHy1lApWjjI8OB0KPaVpL yxx3TER9jfy+edMjoQCSkk4UANA/eSdh3uIEncm5vw2nWS/W1SNUeAhdtWieW3SKqHpw 5Pl9XxqhrlYfc39Q7RjOzsNVWSJTyNHFFDkdmNgBhmJBKrPKSTneamVo40MJrA2tFGAU SGKGRYQGNuPUZSxpgge7l0atJP4PEt4/okGuxwJwepIPSsyTnhLY7T2h+MWUtJv9qxMa 8xpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=nABhlNPl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v8si12583165pgs.55.2019.03.25.01.38.37; Mon, 25 Mar 2019 01:38:37 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=nABhlNPl; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730499AbfCYIig (ORCPT + 31 others); Mon, 25 Mar 2019 04:38:36 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:52578 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730482AbfCYIie (ORCPT ); Mon, 25 Mar 2019 04:38:34 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2P8bjR9106850; Mon, 25 Mar 2019 03:37:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553503065; bh=ecY/+Ui4SK2VPooZ8MRoP5X7hto+xBrP5+SVRZo/EkI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=nABhlNPlJTLJIek0kqbIX0W+S3oBUO3cAcPsNZUZVPfQ57qIktE++39teT61zXVN8 KWKNtK5DZDVCtwasK5BGkDJpRttCU96MFyTKnlO1upOzTrkVNV3n2gw9hx5Kzw47XY hiLzDsLZvuKif3++DBuVYdGbXRmxA0DqQ3qL9zb0= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2P8bjsM018060 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 25 Mar 2019 03:37:45 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Mon, 25 Mar 2019 03:37:45 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Mon, 25 Mar 2019 03:37:45 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2P8ZsG7006534; Mon, 25 Mar 2019 03:37:41 -0500 From: Kishon Vijay Abraham I To: Gustavo Pimentel , Bjorn Helgaas , Rob Herring , Lorenzo Pieralisi , Arnd Bergmann , Murali Karicheri CC: Kishon Vijay Abraham I , Jingoo Han , Greg Kroah-Hartman , , , , , , Subject: [PATCH v2 25/26] misc: pci_endpoint_test: Add support to test PCI EP in AM654x Date: Mon, 25 Mar 2019 14:05:00 +0530 Message-ID: <20190325083501.8088-26-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190325083501.8088-1-kishon@ti.com> References: <20190325083501.8088-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org TI's AM654x PCIe EP has a restriction that BAR_0 is mapped to application registers. "PCIe Inbound Address Translation" section in AM65x Sitara Processors TRM (SPRUID7 – April 2018) describes BAR0 is reserved. Configure pci_endpoint_test to use BAR_2 instead. Also set alignment to 64K since "PCIe Subsystem Address Translation" section in TRM indicates minimum ATU window size is 64K. Signed-off-by: Kishon Vijay Abraham I --- drivers/misc/pci_endpoint_test.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) -- 2.17.1 diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 29582fe57151..e015e8fa9bd3 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -75,6 +75,11 @@ #define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24 #define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28 +#define PCI_DEVICE_ID_TI_AM654 0xb00c + +#define is_am654_pci_dev(pdev) \ + ((pdev)->device == PCI_DEVICE_ID_TI_AM654) + static DEFINE_IDA(pci_endpoint_test_ida); #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \ @@ -588,6 +593,7 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd, int ret = -EINVAL; enum pci_barno bar; struct pci_endpoint_test *test = to_endpoint_test(file->private_data); + struct pci_dev *pdev = test->pdev; mutex_lock(&test->mutex); switch (cmd) { @@ -595,6 +601,8 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd, bar = arg; if (bar < 0 || bar > 5) goto ret; + if (is_am654_pci_dev(pdev) && bar == BAR_0) + goto ret; ret = pci_endpoint_test_bar(test, bar); break; case PCITEST_LEGACY_IRQ: @@ -785,11 +793,20 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev) pci_disable_device(pdev); } +static const struct pci_endpoint_test_data am654_data = { + .test_reg_bar = BAR_2, + .alignment = SZ_64K, + .irq_type = IRQ_TYPE_MSI, +}; + static const struct pci_device_id pci_endpoint_test_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) }, { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) }, { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0) }, { PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 0xedda) }, + { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654), + .driver_data = (kernel_ulong_t)&am654_data + }, { } }; MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl); From patchwork Mon Mar 25 08:35:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 161047 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp3697249jan; Mon, 25 Mar 2019 01:38:11 -0700 (PDT) X-Google-Smtp-Source: APXvYqwhBBSuJG8DLO/RTE+c1mqQBI2G9OAIgpfJXtyCQOS4HnS9Hm2NO2p3OJvcupHpG6HLXch/ X-Received: by 2002:a17:902:ba88:: with SMTP id k8mr21606247pls.268.1553503090946; Mon, 25 Mar 2019 01:38:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553503090; cv=none; d=google.com; s=arc-20160816; b=NRyyK01CMni1xMrW8+SyglUx00PPW9P/LnWCWRSZ4kJUCBVgokv0TpbkJTwtOxMviO KF1MNjPuCNZiaDlvMRk2HQmaSXmSWnj6KN8MMpn8zuEToka/FCHE/+NTPO3RDJWLD8CX gh4KY3va3QGCJO6fJZf4j59BYCnPFED9iiybbe2H2k15kZwQdm5VVq8M8+YpMx99qB/d wqlOFlxcTVXKL5XZKRUgrh5lk4LeEuRU21GMnSdfTASFGarZUDoi/8n4a0toXSZmRNHm 6iWzSfi/Oy5vVesf38tf8CvZW8TN21PF26CSx9LtG/SFqG06jYVBRwsRen4NH0EpG7uw ebtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=2++9Tg54a9f6hIecMipMBo4Cbzj6epb7v0EYAzsW2ns=; b=nNuKWghJmL1BfEuu3MbvAfT1p/R9wtiqPvDjjEvlbv4dhGauBxyOwwk6JoswKDwQKI KXzVE6J3s2iFpXqxr0hERJ7xoehdT2fygaoweziFQd+AtNWdE2wPPA5/YDcudgte9bAJ UHcM71QUtC0aqQd2JTMnXB7eTATk18ax9LO82NbMbuboBzNw6eyB93O5ZLLTQ8FtJFDq yiSjYfo6JngAvaIcQbqwucOiKhQs6XWmaWW1lkeFPnNnY8kAdrJxazGxDN25f3Y3AdjU GICO+5IQ4a/n4X1pbs0vzXMVh3o0jGzjTqowSFigHY/LD0ZbtgLPExWfj7usHKS6xnzN Xfkw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=IgnQdBJi; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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This results in test_reg_bar having invalid value when used outside probe. Fix it here. Fixes: 834b9051992580ac8fd3966d023b ("misc: pci_endpoint_test: Add support for PCI_ENDPOINT_TEST regs to be mapped to any BAR") Signed-off-by: Kishon Vijay Abraham I --- drivers/misc/pci_endpoint_test.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index e015e8fa9bd3..7b015f2a1c6f 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -670,6 +670,7 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev, data = (struct pci_endpoint_test_data *)ent->driver_data; if (data) { test_reg_bar = data->test_reg_bar; + test->test_reg_bar = test_reg_bar; test->alignment = data->alignment; irq_type = data->irq_type; }