From patchwork Fri Dec 2 08:16:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 630965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D495CC4167B for ; Fri, 2 Dec 2022 08:19:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232896AbiLBITU (ORCPT ); Fri, 2 Dec 2022 03:19:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232772AbiLBISe (ORCPT ); Fri, 2 Dec 2022 03:18:34 -0500 Received: from sender4-op-o18.zoho.com (sender4-op-o18.zoho.com [136.143.188.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8F1EF585; Fri, 2 Dec 2022 00:17:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669969043; cv=none; d=zohomail.com; s=zohoarc; b=YnUPjnsuIe+0K04IK7XQmhRRfK2SNlpJMtnX0fxANCuZlPNalSovgjBoy4al2bdHmlUjFonc6ceHBbxhewlR0ipyEkT9DfwBLUIGpozo9AFJiSRKHyfRMhR56gfvpQ6cXnItQQ3rGYeOUsTSSym6g0hSSRvFnvsmGuF2VJTq4Gg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1669969043; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=Rratc0OttPrJfv5oyD9jUDBZ1BW+JJIqS7W6aA3RiwM=; b=RnQgn1KvbYcZ0Gpb4QyLihaYgoGaYwGjmVmu3kqRtIZjEyEiotY0IiS6MCu5KgMKGh1uWSYZNuAvT977IL8Pwy9ADnSvswxo9xeKHHteT5zjyQIOANxzmdLMlDmaTsYwLnLvgQkYcytvh/rsSbsznU6WGr45+ymAaHVK3IKus/A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1669969043; s=zmail; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Reply-To; bh=Rratc0OttPrJfv5oyD9jUDBZ1BW+JJIqS7W6aA3RiwM=; b=Pt8k1vXB48VEjsvLG8jmk/IqR7ZjDfDdPMvjsHtUbuy1aoYkr9/WYq793TQfWSBA ClQtrKX8RfPP1azvStjDOW7gXktvhV0aLNUSGg6Y7jYImsdBmoLUbgFfOuXF6+u5oFG sxVGiw08G0XBhDU9CHz5ms0F6/4PR6Gy8psXK3m0= Received: from edelgard.fodlan.icenowy.me (120.85.99.229 [120.85.99.229]) by mx.zohomail.com with SMTPS id 1669969040692988.3765698302417; Fri, 2 Dec 2022 00:17:20 -0800 (PST) From: Icenowy Zheng To: Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Greg Kroah-Hartman , Matthias Kaehlcke , Andre Przywara Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Icenowy Zheng , Krzysztof Kozlowski Subject: [PATCH v2 1/6] dt-bindings: vendor-prefixes: add Genesys Logic Date: Fri, 2 Dec 2022 16:16:42 +0800 Message-Id: <20221202081647.3183870-2-uwu@icenowy.me> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221202081647.3183870-1-uwu@icenowy.me> References: <20221202081647.3183870-1-uwu@icenowy.me> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Genesys Logic, Inc. is a manufacturer for interface chips, especially USB hubs. https://www.genesyslogic.com.tw/ Signed-off-by: Icenowy Zheng Acked-by: Krzysztof Kozlowski --- Changes in v2: - Add Krzysztof's ACK. Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 6e323a380294..43359c0ccaf5 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -488,6 +488,8 @@ patternProperties: description: GE Fanuc Intelligent Platforms Embedded Systems, Inc. "^gemei,.*": description: Gemei Digital Technology Co., Ltd. + "^genesys,.*": + description: Genesys Logic, Inc. "^geniatech,.*": description: Geniatech, Inc. "^giantec,.*": From patchwork Fri Dec 2 08:16:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 630964 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FE0FC4167B for ; Fri, 2 Dec 2022 08:19:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232778AbiLBITh (ORCPT ); Fri, 2 Dec 2022 03:19:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32918 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232781AbiLBISf (ORCPT ); Fri, 2 Dec 2022 03:18:35 -0500 Received: from sender4-op-o18.zoho.com (sender4-op-o18.zoho.com [136.143.188.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6ACF313F1F; Fri, 2 Dec 2022 00:17:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669969049; cv=none; d=zohomail.com; s=zohoarc; b=KKwgdwJkmSqoAQSGxIHOyceZkreh9/SJb/7xMLTIwbJe3OvfbbBqEdN1/9kOn0TMjI4I+17HZ433/OJRgZS0x8q37VXBKi496q/lFI4RLJcYDuDnda7/gJAkgqmWKwCTO5b9GEAezfY0AdYCEV3K97XU/Bno35xPrdXU1LTSC/s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1669969049; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=ORW3PCrQfzAkTQ7duk9/RgOnxHxJYMd6++GTmA/EuUQ=; b=W3DiYxW4gcKVHFV/GQFzCHL4SL14Cf4c/eT28EvSUtdcBQD3+efeaiXhdqqEjDIuV4YE5pD5FLp9sa6AyoKaUHkzUaAb5oKhF0rfLkQa9Z/E77rNFcM1v5bNm9XbLv5p9nz01jjx6m2o016mjb0fd6uwx8Y+fcVfmo/mbfZpNTE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1669969049; s=zmail; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Reply-To; bh=ORW3PCrQfzAkTQ7duk9/RgOnxHxJYMd6++GTmA/EuUQ=; b=Eprz7xti57zaJ0er7EgoNKw2kE2b0CBhd4/sBrR2B+zleffWXxB6LPOO8k9dJ5RQ 1CGao6jKAMyNjO7lq1dh32rE07qk1HMkQvP5MXcdl6xRBtDXjkF1ohge4eXocQhj17b uOXaYfQIG0OrF4y7lwC+5XEDV4AXbh03GYlO4z/E= Received: from edelgard.fodlan.icenowy.me (120.85.99.229 [120.85.99.229]) by mx.zohomail.com with SMTPS id 1669969047936410.260924341292; Fri, 2 Dec 2022 00:17:27 -0800 (PST) From: Icenowy Zheng To: Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Greg Kroah-Hartman , Matthias Kaehlcke , Andre Przywara Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Icenowy Zheng Subject: [PATCH v2 2/6] dt-bindings: usb: Add binding for Genesys Logic GL850G hub controller Date: Fri, 2 Dec 2022 16:16:43 +0800 Message-Id: <20221202081647.3183870-3-uwu@icenowy.me> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221202081647.3183870-1-uwu@icenowy.me> References: <20221202081647.3183870-1-uwu@icenowy.me> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Genesys Logic GL850G is a USB 2.0 Single TT hub controller that features 4 downstream ports, an internal 5V-to-3.3V LDO regulator (can be bypassed) and an external reset pin. Add a device tree binding for its USB protocol part. The internal LDO is not covered by this and can just be modelled as a fixed regulator. Signed-off-by: Icenowy Zheng --- Changes in v2: - Misc fixes suggested by Krzysztof, including property descriptions, single-item "items" and fixing the example's gpio property. - Fixed $id. .../bindings/usb/genesys,gl850g.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/genesys,gl850g.yaml diff --git a/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml b/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml new file mode 100644 index 000000000000..966462ca6acb --- /dev/null +++ b/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/genesys,gl850g.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Genesys Logic GL850G USB 2.0 hub controller + +maintainers: + - Icenowy Zheng + +allOf: + - $ref: usb-device.yaml# + +properties: + compatible: + enum: + - usb5e3,608 + + reg: true + + reset-gpios: + description: GPIO controlling the RESET# pin. + + vdd-supply: + description: + the regulator that provides 3.3V core power to the hub. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + usb { + dr_mode = "host"; + #address-cells = <1>; + #size-cells = <0>; + + hub: hub@1 { + compatible = "usb5e3,608"; + reg = <1>; + reset-gpios = <&pio 7 2>; + }; + }; From patchwork Fri Dec 2 08:16:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 630432 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F3B4EC47088 for ; Fri, 2 Dec 2022 08:19:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232795AbiLBIT6 (ORCPT ); Fri, 2 Dec 2022 03:19:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232619AbiLBISk (ORCPT ); Fri, 2 Dec 2022 03:18:40 -0500 Received: from sender4-op-o18.zoho.com (sender4-op-o18.zoho.com [136.143.188.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A400540900; Fri, 2 Dec 2022 00:18:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669969067; cv=none; d=zohomail.com; s=zohoarc; b=L07URF0wZwvYLggDZBZA2tPzDguru9spJ9HLUaaqTScJMHkVuHssoB9ao8PjKzH7h/4D+ZMzQpH8JSNNGspnc7ekTVIFZ8FmC7nutyVPTde77XZkgEBGFxJ/z6/c7ikC4uKyJR4fBKl7IU23cnZTV61Ci/On/iO1AUPb7f1p9tU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1669969067; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=OLlTVhT3idm/OLIzzgRQz3I7RcmreMDAJB3HnjwLFY4=; b=KKamnyA3wSZPymAl9DS7KO6THAibSn+MZYwCiK/gENsyXlIKbLd0TXIqPcjiIjMVzW8iEBc0J/bVYYkpFQhzHu5tTVALp7naNIby+SUKhLJb7kYZEfHIseuJkb4JxKJONWG4C4tWG2akt2ERSWfPZ2n8V1bYCjyu4YX77G6whiw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1669969067; s=zmail; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Reply-To; bh=OLlTVhT3idm/OLIzzgRQz3I7RcmreMDAJB3HnjwLFY4=; b=Rpcfg4DCnEPWtpEZBN6E7Z6qizn7lKTxr2I+JkilHnsS4lR9XRfqX/ubPC7VvTYH G2pui6pVqoFPgghqgpo0KTRffLktyAcGSw8OQ2qOzGLG5B7UvZTXdXQKKKCrek0/H6Y Y1McqnZa/FEqYxaXcAf4sLMNn/MKCfS0chYfXblk= Received: from edelgard.fodlan.icenowy.me (120.85.99.229 [120.85.99.229]) by mx.zohomail.com with SMTPS id 1669969066601638.7158094915221; Fri, 2 Dec 2022 00:17:46 -0800 (PST) From: Icenowy Zheng To: Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Greg Kroah-Hartman , Matthias Kaehlcke , Andre Przywara Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Icenowy Zheng Subject: [PATCH v2 3/6] usb: misc: onboard_usb_hub: add Genesys Logic GL850G hub support Date: Fri, 2 Dec 2022 16:16:44 +0800 Message-Id: <20221202081647.3183870-4-uwu@icenowy.me> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221202081647.3183870-1-uwu@icenowy.me> References: <20221202081647.3183870-1-uwu@icenowy.me> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Genesys Logic GL850G is a 4-port USB 2.0 STT hub that has a reset pin to toggle and a 3.3V core supply exported (although an integrated LDO is available for powering it with 5V). Add the support for this hub, for controlling the reset pin and the core power supply. Signed-off-by: Icenowy Zheng Acked-by: Matthias Kaehlcke --- Changes in v2: - Sort things, by names or vendor IDs. drivers/usb/misc/onboard_usb_hub.c | 2 ++ drivers/usb/misc/onboard_usb_hub.h | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/drivers/usb/misc/onboard_usb_hub.c b/drivers/usb/misc/onboard_usb_hub.c index d63c63942af1..94e7966e199d 100644 --- a/drivers/usb/misc/onboard_usb_hub.c +++ b/drivers/usb/misc/onboard_usb_hub.c @@ -331,6 +331,7 @@ static struct platform_driver onboard_hub_driver = { /************************** USB driver **************************/ +#define VENDOR_ID_GENESYS 0x05e3 #define VENDOR_ID_MICROCHIP 0x0424 #define VENDOR_ID_REALTEK 0x0bda #define VENDOR_ID_TI 0x0451 @@ -407,6 +408,7 @@ static void onboard_hub_usbdev_disconnect(struct usb_device *udev) } static const struct usb_device_id onboard_hub_id_table[] = { + { USB_DEVICE(VENDOR_ID_GENESYS, 0x0608) }, /* Genesys Logic GL850G USB 2.0 */ { USB_DEVICE(VENDOR_ID_MICROCHIP, 0x2514) }, /* USB2514B USB 2.0 */ { USB_DEVICE(VENDOR_ID_REALTEK, 0x0411) }, /* RTS5411 USB 3.1 */ { USB_DEVICE(VENDOR_ID_REALTEK, 0x5411) }, /* RTS5411 USB 2.1 */ diff --git a/drivers/usb/misc/onboard_usb_hub.h b/drivers/usb/misc/onboard_usb_hub.h index 34beab8bce3d..62129a6a1ba5 100644 --- a/drivers/usb/misc/onboard_usb_hub.h +++ b/drivers/usb/misc/onboard_usb_hub.h @@ -22,10 +22,15 @@ static const struct onboard_hub_pdata ti_tusb8041_data = { .reset_us = 3000, }; +static const struct onboard_hub_pdata genesys_gl850g_data = { + .reset_us = 3, +}; + static const struct of_device_id onboard_hub_match[] = { { .compatible = "usb424,2514", .data = µchip_usb424_data, }, { .compatible = "usb451,8140", .data = &ti_tusb8041_data, }, { .compatible = "usb451,8142", .data = &ti_tusb8041_data, }, + { .compatible = "usb5e3,608", .data = &genesys_gl850g_data, }, { .compatible = "usbbda,411", .data = &realtek_rts5411_data, }, { .compatible = "usbbda,5411", .data = &realtek_rts5411_data, }, { .compatible = "usbbda,414", .data = &realtek_rts5411_data, }, From patchwork Fri Dec 2 08:16:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 630963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7AC7BC47088 for ; Fri, 2 Dec 2022 08:20:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232860AbiLBIUX (ORCPT ); Fri, 2 Dec 2022 03:20:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232413AbiLBISo (ORCPT ); Fri, 2 Dec 2022 03:18:44 -0500 Received: from sender4-op-o18.zoho.com (sender4-op-o18.zoho.com [136.143.188.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8CB860B73; Fri, 2 Dec 2022 00:18:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669969079; cv=none; d=zohomail.com; s=zohoarc; b=BpIk+3PS27+rqhe8xeqTHXMatArygXvfrPQTgopGYzpHh+dYQZsHfa9Kp4MRxcn7ZzR6EdMBxmQETUjJ+y2JLaBuQ4MquPX78nRlD6foQFOcf9YwUsBJVr5OGff4z9ebnqHrsAa9Nrf1KKV9sjuZBt7sbFpmTxraZeuWBCT309M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1669969079; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=qIOjPPxRBJHg1FZr7N6ohN9vGSHFYL2Yc+prewJ9KUc=; b=UHHHvvok6hp8Bd3U7t9giB/DIU9Wtl6FYOHmS5yf4RKE81wCHNHDt5yT3DD17JlmizfD7XTQGQwtH5lrBloQSArSnAYYedgYg2RWIWVips0plqGJVJRLiC4Puq46pcLJeKqwK7SkbHDjHIUtqnbGhVNuCQG/JJdF9nfOPTa/ki8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1669969079; s=zmail; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Reply-To; bh=qIOjPPxRBJHg1FZr7N6ohN9vGSHFYL2Yc+prewJ9KUc=; b=SpCP7ass54C0rAG0PB/Tj7sXwUPXjXQdh8t++Y5g+H4UeeCBe0NYbXhSOh0lEKSV ScoFPYQDtOxUZpkYVKWx3GOYgE3V8oDM2gy5YqigYxbmbb8ubDy4unUpG8ZSRGGGMWr yzWCQYUfkLX/ruOus0CcJx8ajt1aAPfwwpuDPrns= Received: from edelgard.fodlan.icenowy.me (120.85.99.229 [120.85.99.229]) by mx.zohomail.com with SMTPS id 1669969077180575.6488779211163; Fri, 2 Dec 2022 00:17:57 -0800 (PST) From: Icenowy Zheng To: Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Greg Kroah-Hartman , Matthias Kaehlcke , Andre Przywara Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Icenowy Zheng , Krzysztof Kozlowski Subject: [PATCH v2 4/6] vendor-prefixes: Add Shenzhen Rongpin Electronics Co., Ltd Date: Fri, 2 Dec 2022 16:16:45 +0800 Message-Id: <20221202081647.3183870-5-uwu@icenowy.me> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221202081647.3183870-1-uwu@icenowy.me> References: <20221202081647.3183870-1-uwu@icenowy.me> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the vendor prefix for Shenzhen Rongpin Electronics Co., Ltd, which specializes in ARM SoMs and EVBs. Website: http://www.rpdzkj.com/ Signed-off-by: Icenowy Zheng Acked-by: Krzysztof Kozlowski --- Changes in v2: - Add Krzysztof's ACK. Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 43359c0ccaf5..952ddeed4b4a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1091,6 +1091,8 @@ patternProperties: description: ROHM Semiconductor Co., Ltd "^ronbo,.*": description: Ronbo Electronics + "^rongpin,.*": + description: Shenzhen Rongpin Electronics Co., Ltd "^roofull,.*": description: Shenzhen Roofull Technology Co, Ltd "^roseapplepi,.*": From patchwork Fri Dec 2 08:16:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 630431 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6490EC4332F for ; Fri, 2 Dec 2022 08:20:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232827AbiLBIUg (ORCPT ); Fri, 2 Dec 2022 03:20:36 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232754AbiLBITD (ORCPT ); Fri, 2 Dec 2022 03:19:03 -0500 Received: from sender4-op-o18.zoho.com (sender4-op-o18.zoho.com [136.143.188.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CE3EAD309; Fri, 2 Dec 2022 00:18:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669969089; cv=none; d=zohomail.com; s=zohoarc; b=T+W1DalycLhYAsP18ryuYYn1E279/0FGYrDbYa3YRlub3YY8OhAqVj4l1HxdbI3g40UzacYWltrai15yIlu8d7Rm/Xep6/Y9q1/PW9KxWGRJLDbLa3IwuZhPWTKa7/b+vjQgT0uRn9IEJei/i9tMzOyWY1o5PAX8jEf3B7obn0A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1669969089; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=YjVqQPVDrMTTPaH9XdK31p0qv5gXWSbzArYnoQvmmro=; b=Ndoxzwt8sLT8CMt+jVtcdBL5F7aW2pkoY6vC2ZLCzBXESgSlTiY3kdmHa0N7yXYM8A6M1YHAlcMUPPYmgMxYh0hkOUFKFYeEeXDJTy3FWoS1Wgc/wC84H6vFIZGVJCirzjX5VdcxUvOhtBpHxhLbTdC8BHnbjhrIXTlEFYsxxPw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1669969089; s=zmail; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Reply-To; bh=YjVqQPVDrMTTPaH9XdK31p0qv5gXWSbzArYnoQvmmro=; b=VlmV1t/XKncTo1U6jeIZIR/HKuLZ4msDuzF3DmGPgIebxazVNGjjTyN+06yjcyrb U0TXaKHg2fopS1/Zqb0LingVkcpOWW04lolWdlhl/ZZYDAflz0BDlui5KD7dB168G2P MOyIcG19y1bolehREdKbPlCas58T9OD8lkXEJTOc= Received: from edelgard.fodlan.icenowy.me (120.85.99.229 [120.85.99.229]) by mx.zohomail.com with SMTPS id 1669969087734695.9599994502184; Fri, 2 Dec 2022 00:18:07 -0800 (PST) From: Icenowy Zheng To: Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Greg Kroah-Hartman , Matthias Kaehlcke , Andre Przywara Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Icenowy Zheng , Krzysztof Kozlowski Subject: [PATCH v2 5/6] dt-bindings: arm: sunxi: add Rongpin RP-H6B board Date: Fri, 2 Dec 2022 16:16:46 +0800 Message-Id: <20221202081647.3183870-6-uwu@icenowy.me> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221202081647.3183870-1-uwu@icenowy.me> References: <20221202081647.3183870-1-uwu@icenowy.me> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rongpin RP-H6B is a development board with RP-H6C SoM, which uses an Allwinner H6 SoC. Add compatible strings for it, including the board-specific compatible and the SoM compatible. Signed-off-by: Icenowy Zheng Acked-by: Krzysztof Kozlowski Reviewed-by: Samuel Holland --- Changes in v2: - Add Krzysztof's ACK. Documentation/devicetree/bindings/arm/sunxi.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 3ad1cd50e3fe..482631815f2f 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -792,6 +792,12 @@ properties: - const: rervision,h3-dvk - const: allwinner,sun8i-h3 + - description: Rongpin RP-H6B development board + items: + - const: rongpin,rp-h6b + - const: rongpin,rp-h6c + - const: allwinner,sun50i-h6 + - description: Sinlinx SinA31s Core Board items: - const: sinlinx,sina31s From patchwork Fri Dec 2 08:16:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Icenowy Zheng X-Patchwork-Id: 630962 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38FBEC4708D for ; Fri, 2 Dec 2022 08:20:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232936AbiLBIUh (ORCPT ); Fri, 2 Dec 2022 03:20:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232760AbiLBITK (ORCPT ); Fri, 2 Dec 2022 03:19:10 -0500 Received: from sender4-op-o18.zoho.com (sender4-op-o18.zoho.com [136.143.188.18]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 13AD3CE1A; Fri, 2 Dec 2022 00:18:41 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1669969105; cv=none; d=zohomail.com; s=zohoarc; b=FpQaqfHYP5GHGr5ts8bcTnxrbeeev/iddGX/Q72Ehs+T1pfW+WDYQ1rrBklV/hGw2zziPdIffiPjHA+AVxj8FyWOZeffrv8IB9UQOfnCcWatYFSYyTrMrlkLSTVmx6Wi2Dvp7PsIfyUWviTPwgiFVdw4v74Aj19ICeZTYPPYrJY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1669969105; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=8ECuMZawpjSVHvQjUBetfP6Pc3GP52JI3GjpdBPc0V4=; b=fNbTMSSWh2qSdwgYnXccsZb+q1h90pgpDE5dGVo/EEhCXLe3hwtZ6Q6IRheI/FTp04Il1yWqIb/4dH8AA6moFS0cde2mOPpmZEJ+/ESj9FJMYpfgVlozJsBD8nVMYeWVwCuWE7WV7U2y9LOU7jE2XqoBWRo373vv/W+g+ThBjmw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=icenowy.me; spf=pass smtp.mailfrom=uwu@icenowy.me; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1669969105; s=zmail; d=icenowy.me; i=uwu@icenowy.me; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-Id:Message-Id:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Reply-To; bh=8ECuMZawpjSVHvQjUBetfP6Pc3GP52JI3GjpdBPc0V4=; b=Wss7KYQO6OjtvcTvd+BhmqDFiS08z2Yspp2Gf0eegLlx9Z9AVtRg6qXMhpoVAA48 QvvLrvLi+DHOGlU3omcKAMiENjyToeggHAbpSvc88ID3lJA5YOYGC3d1DSCLOdMc9hN 0ZoyAd7hFQuOiZTASAlEVUp06OI2sJFOxiZXGlmk= Received: from edelgard.fodlan.icenowy.me (120.85.99.229 [120.85.99.229]) by mx.zohomail.com with SMTPS id 1669969103150602.338938716538; Fri, 2 Dec 2022 00:18:23 -0800 (PST) From: Icenowy Zheng To: Rob Herring , Krzysztof Kozlowski , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Greg Kroah-Hartman , Matthias Kaehlcke , Andre Przywara Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, Icenowy Zheng Subject: [PATCH v2 6/6] arm64: dts: allwinner: h6: add Rongpin RP-H6C SoM and RP-H6B board Date: Fri, 2 Dec 2022 16:16:47 +0800 Message-Id: <20221202081647.3183870-7-uwu@icenowy.me> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221202081647.3183870-1-uwu@icenowy.me> References: <20221202081647.3183870-1-uwu@icenowy.me> MIME-Version: 1.0 X-ZohoMailClient: External Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rongpin RP-H6C is an Allwinner H6 SoM by Rongpin, with Allwinner H6 SoC, AXP805 PMIC, LPDDR3 memory and eMMC storage on it. RP-H6B is their official evaluation board of RP-H6C, with an onboard GL850G USB hub, Ampak AP6212 Wi-Fi module and some circuits about LVDS display. It also exports the OTG USB port, the USB 3.0 port, PCIe bus (as mPCIe slot), internal Ethernet PHY, analog audio/video and HDMI port. Add a DTSI file for the SoM and a DTS for the full board. Signed-off-by: Icenowy Zheng --- Changes in v2: - Name all regulator nodes regulator-xxx. - Fixed underscores in node names. arch/arm64/boot/dts/allwinner/Makefile | 1 + .../boot/dts/allwinner/sun50i-h6-rp-h6b.dts | 239 ++++++++++++++++++ .../boot/dts/allwinner/sun50i-h6-rp-h6c.dtsi | 180 +++++++++++++ 3 files changed, 420 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-rp-h6b.dts create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-rp-h6c.dtsi diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index 6a96494a2e0a..e289fedcac29 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -36,6 +36,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-rp-h6b.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-rp-h6b.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-rp-h6b.dts new file mode 100644 index 000000000000..d9994e9beb81 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-rp-h6b.dts @@ -0,0 +1,239 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2022 Icenowy Zheng + */ +/dts-v1/; + +#include "sun50i-h6-rp-h6c.dtsi" + +#include + +/ { + model = "Rongpin RP-H6B baseboard"; + compatible = "rongpin,rp-h6b", "rongpin,rp-h6c", + "allwinner,sun50i-h6"; + + aliases { + ethernet0 = &emac; + serial0 = &uart0; + /* + * Prioritize the external RTC because it's powered + * by a cell battery. + */ + rtc0 = &hym8563; + rtc1 = &rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi_connector: connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + led { + label = "rongpin:red:link"; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */ + /* + * On the schematics this LED is marked as "lit when + * powering on and blinking when running". + */ + linux,default-trigger = "heartbeat"; + }; + }; + + /* + * The VDD_5V power rail is connected to the internal regulator + * of GL850G, to power up the 3.3V core of it. + */ + reg_v33_hub: regulator-v33-hub { + compatible = "regulator-fixed"; + regulator-name = "v33-hub"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vdd_5v>; + }; + + /* + * This board inputs 5V to AP6212 via a SS34 diode. Use this + * regulator as the model of the internal regulator of AP6212. + */ + reg_vcc3v3_ap6212: regulator-vcc3v3-ap6212 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3-ap6212"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_ps>; + }; + + reg_vdd_5v: regulator-vdd-5v { + compatible = "regulator-fixed"; + regulator-name = "vdd-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <100000>; + gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_ps>; + }; + + /* For mPCIe slot WWAN modules / PCIe cards */ + reg_vdd_3g: regulator-vdd-3g { + compatible = "regulator-fixed"; + regulator-name = "vdd-3g"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_ps>; + /* + * As a hack for lacking of control of a hub downstream + * port's Vbus. + */ + regulator-always-on; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */ + post-power-on-delay-ms = <200>; + }; +}; + +&de { + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci3 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + /* Genesys Logic GL850G usb hub */ + compatible = "usb5e3,608"; + reg = <1>; + vdd-supply = <®_v33_hub>; + reset-gpios = <&pio 7 2 GPIO_ACTIVE_LOW>; + }; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&i2c0 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + vmmc-supply = <®_cldo1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <®_vcc3v3_ap6212>; + vqmmc-supply = <®_bldo3>; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + bus-width = <4>; + status = "okay"; + + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&r_pio>; + interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */ + interrupt-names = "host-wake"; + }; +}; + +&ohci0 { + status = "okay"; +}; + +/* Converted from 12v with a fixed DC-DC on the baseboard */ +®_ps { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; + +/* Bluetooth */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + max-speed = <1500000>; + clocks = <&rtc CLK_OSC32K_FANOUT>; + clock-names = "lpo"; + vbat-supply = <®_ps>; + vddio-supply = <®_bldo3>; + device-wakeup-gpios = <&r_pio 1 2 GPIO_ACTIVE_HIGH>; /* PM2 */ + shutdown-gpios = <&r_pio 1 4 GPIO_ACTIVE_HIGH>; /* PM4 */ + interrupt-parent = <&r_pio>; + interrupts = <1 1 IRQ_TYPE_EDGE_FALLING>; /* PM1 */ + interrupt-names = "host-wakeup"; + }; +}; + +&uart1_pins { + bias-pull-up; +}; + +&uart1_rts_cts_pins { + bias-pull-up; +}; + +&usb2otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb2phy { + usb0_vbus-supply = <®_vdd_5v>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-rp-h6c.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-rp-h6c.dtsi new file mode 100644 index 000000000000..637c194016c4 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-rp-h6c.dtsi @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2019-2022 Icenowy Zheng + */ + +#include "sun50i-h6.dtsi" +#include "sun50i-h6-cpu-opp.dtsi" +#include "sun50i-h6-gpu-opp.dtsi" + +/ { + ext_osc32k: ext-osc32k-clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "ext_osc32k"; + }; + + /* Marked 3.4v~5.5v on SoM schematics */ + reg_ps: regulator-ps { + compatible = "regulator-fixed"; + regulator-name = "ps"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdca>; +}; + +&gpu { + mali-supply = <®_dcdcc>; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <®_cldo1>; + vqmmc-supply = <®_bldo2>; + non-removable; + cap-mmc-hw-reset; + bus-width = <8>; + status = "okay"; +}; + +&pio { + vcc-pc-supply = <®_bldo2>; + vcc-pd-supply = <®_aldo2>; + vcc-pg-supply = <®_bldo3>; +}; + +&r_pio { + /* + * FIXME: We can't add that supply for now since it would + * create a circular dependency between pinctrl, the regulator + * and the RSB Bus. + * + * vcc-pl-supply = <®_aldo1>; + */ + vcc-pm-supply = <®_bldo3>; +}; + +&r_rsb { + status = "okay"; + clock-frequency = <400000>; + + axp805: pmic@745 { + compatible = "x-powers,axp805", "x-powers,axp806"; + reg = <0x745>; + interrupt-parent = <&r_intc>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + x-powers,self-working-mode; + vina-supply = <®_ps>; + vinb-supply = <®_ps>; + vinc-supply = <®_ps>; + vind-supply = <®_ps>; + vine-supply = <®_ps>; + aldoin-supply = <®_ps>; + bldoin-supply = <®_ps>; + cldoin-supply = <®_ps>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ac200"; + regulator-enable-ramp-delay = <100000>; + }; + + aldo3 { + /* unused */ + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-bias-pll"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-efuse-pcie-hdmi-io"; + }; + + reg_bldo3: bldo3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dcxoio"; + }; + + bldo4 { + /* unused */ + }; + + reg_cldo1: cldo1 { + /* This regulator is connected with ALDO3 */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3-2"; + }; + + cldo2 { + /* unused */ + }; + + cldo3 { + /* unused */ + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1160000>; + regulator-ramp-delay = <2500>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-gpu"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <960000>; + regulator-max-microvolt = <960000>; + regulator-name = "vdd-sys"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&rtc { + clocks = <&ext_osc32k>; +};