From patchwork Fri Dec 2 16:23:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 630945 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A4AEC63703 for ; Fri, 2 Dec 2022 16:25:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233548AbiLBQZl (ORCPT ); Fri, 2 Dec 2022 11:25:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231470AbiLBQZX (ORCPT ); Fri, 2 Dec 2022 11:25:23 -0500 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B883101D; Fri, 2 Dec 2022 08:24:13 -0800 (PST) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 5F20484F66; Fri, 2 Dec 2022 17:24:11 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1669998252; bh=CJLV50zn4/UdYMLrvwnU+6Q7Znd55DAnHXwpVXmTeWs=; h=From:To:Cc:Subject:Date:From; b=eWp8X8DtAWZhQUDrxevA4wVUkOKn/FJgL5sLPk29zi+iwBvId3tRL30KrUvdOjONG vvBh/t72U9EKgT7DfXTXgn4TV2Em3prtyPzXAusx/rkXhE9fTnIj+HgAm5NAb7XBG8 ZO+F9KBip7T4LsYiwYY1aTYinNGON8oLzNNob8Nhwavzc7TptIBVw1NVzaEfP2A7C0 xbGE4i38eqtxYp7O9glpxbF5Z4gYsVs0/8mcm5n03GePRe6CkhV50sa6HdBifxWL/h 1Qo3HbiyNyZuhYZi8mSbmB13M7mYpZkNo8s+J31Kn6GViUqbmFyKmOYHiNxE5vvLpL fNxpnYAjv0Gdw== From: Marek Vasut To: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Krzysztof Kozlowski , Adam Ford , Alice Guo , Amit Kucheria , Daniel Lezcano , Fabio Estevam , Krzysztof Kozlowski , Li Jun , Lucas Stach , Markus Niebel , NXP Linux Team , Peng Fan , Pengutronix Kernel Team , "Rafael J . Wysocki" , Richard Cochran , Rob Herring , Sascha Hauer , Shawn Guo , Zhang Rui , devicetree@vger.kernel.org Subject: [PATCH v3 1/5] dt-bindings: thermal: imx8mm-thermal: Document optional nvmem-cells Date: Fri, 2 Dec 2022 17:23:49 +0100 Message-Id: <20221202162353.274009-1-marex@denx.de> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with calibration values from OCOTP. Document optional phandle to OCOTP nvmem provider. Acked-by: Krzysztof Kozlowski Signed-off-by: Marek Vasut --- Cc: Adam Ford Cc: Alice Guo Cc: Amit Kucheria Cc: Daniel Lezcano Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Li Jun Cc: Lucas Stach Cc: Markus Niebel Cc: NXP Linux Team Cc: Peng Fan Cc: Pengutronix Kernel Team Cc: Rafael J. Wysocki Cc: Richard Cochran Cc: Rob Herring Cc: Sascha Hauer Cc: Shawn Guo Cc: Zhang Rui Cc: devicetree@vger.kernel.org To: linux-pm@vger.kernel.org To: linux-arm-kernel@lists.infradead.org --- V2: Add AB from Krzysztof V3: No change --- .../devicetree/bindings/thermal/imx8mm-thermal.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml index 89c54e08ee61b..b90726229ac9c 100644 --- a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.yaml @@ -32,6 +32,13 @@ properties: clocks: maxItems: 1 + nvmem-cells: + maxItems: 1 + description: Phandle to the calibration data provided by ocotp + + nvmem-cell-names: + const: calib + "#thermal-sensor-cells": description: | Number of cells required to uniquely identify the thermal From patchwork Fri Dec 2 16:23:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 630412 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72A91C47090 for ; Fri, 2 Dec 2022 16:25:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233921AbiLBQZl (ORCPT ); Fri, 2 Dec 2022 11:25:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233995AbiLBQZX (ORCPT ); Fri, 2 Dec 2022 11:25:23 -0500 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11A622AF3; Fri, 2 Dec 2022 08:24:14 -0800 (PST) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 1C74884F24; Fri, 2 Dec 2022 17:24:12 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1669998252; bh=cpkr+6W4IkLsd2qpDf9AOZesJ6DmLNkDIFbno1OM1Gk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=C0UOsiIFaS7SA+oekVgYFcpc5H8qC8TIoYdrCh/wC9NdkYGzAop2J18M6MwK5fzmK i63Sb4eGz6AIcD419JCAsSmdHjHZiG4p4WCnQ6xwpQ0fYQ8gsQN/IsxQ2UlfNtGeQJ FfRFDYzMLv04KGVcHaSMCxywewr+3BqFDcTmYVPNEZeNxDTRjtbyZMReYkhfGz8rx1 g7jzU/pv8nAE5rCUxiuQ83tKI4aAkUdXc3neyIg65uIAE0nyPrRzIGHf7bj7C4tOTI RnN318n9Bt0Yg+uKyjiGNAbWD5uhOxHV2LqaZcYe9s4z7ba7z7PpchQ/2ICwbqCCb1 Zm+jhdwwORDmA== From: Marek Vasut To: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Peng Fan , Adam Ford , Alice Guo , Amit Kucheria , Daniel Lezcano , Fabio Estevam , Krzysztof Kozlowski , Li Jun , Lucas Stach , Markus Niebel , NXP Linux Team , Pengutronix Kernel Team , "Rafael J . Wysocki" , Richard Cochran , Rob Herring , Sascha Hauer , Shawn Guo , Zhang Rui , devicetree@vger.kernel.org Subject: [PATCH v3 2/5] arm64: dts: imx8m: Align SoC unique ID node unit address Date: Fri, 2 Dec 2022 17:23:50 +0100 Message-Id: <20221202162353.274009-2-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221202162353.274009-1-marex@denx.de> References: <20221202162353.274009-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Align the SoC unique ID DT node unit address with its reg property. Reviewed-by: Peng Fan Fixes: cbff23797fa1 ("arm64: dts: imx8m: add NVMEM provider and consumer to read soc unique ID") Signed-off-by: Marek Vasut --- Cc: Adam Ford Cc: Alice Guo Cc: Amit Kucheria Cc: Daniel Lezcano Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Li Jun Cc: Lucas Stach Cc: Markus Niebel Cc: NXP Linux Team Cc: Peng Fan Cc: Pengutronix Kernel Team Cc: Rafael J. Wysocki Cc: Richard Cochran Cc: Rob Herring Cc: Sascha Hauer Cc: Shawn Guo Cc: Zhang Rui Cc: devicetree@vger.kernel.org To: linux-pm@vger.kernel.org To: linux-arm-kernel@lists.infradead.org --- V2: Add RB from Peng V3: No change --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 0c97aca8db6b6..423cb36cbcd53 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -563,7 +563,7 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; - imx8mm_uid: unique-id@410 { + imx8mm_uid: unique-id@4 { reg = <0x4 0x8>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 9b3a9e1384ae9..312e3abc35ea8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -564,7 +564,7 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; - imx8mn_uid: unique-id@410 { + imx8mn_uid: unique-id@4 { reg = <0x4 0x8>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index f18cf611f778e..c9459ed21b243 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -426,7 +426,7 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; - imx8mp_uid: unique-id@420 { + imx8mp_uid: unique-id@8 { reg = <0x8 0x8>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 5246b44a37d4a..2b6d3f4ff5d93 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -593,7 +593,7 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; - imx8mq_uid: soc-uid@410 { + imx8mq_uid: soc-uid@4 { reg = <0x4 0x8>; }; From patchwork Fri Dec 2 16:23:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 630411 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1EC99C63704 for ; Fri, 2 Dec 2022 16:25:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233721AbiLBQZm (ORCPT ); Fri, 2 Dec 2022 11:25:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37600 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233994AbiLBQZX (ORCPT ); Fri, 2 Dec 2022 11:25:23 -0500 Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E12B38BD; Fri, 2 Dec 2022 08:24:15 -0800 (PST) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id D916D85023; Fri, 2 Dec 2022 17:24:12 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1669998253; bh=bC+za2ZVM8M2aK2qyKqPCjL7Y/MV2IrnYhSRg8YnxvE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TY7Dm6p1ZmzQ4WYb8sPsLfvSgGE/+WNHnXx10T5i3o8C/bunCYVKXYX9jt3HnNvUd E3azup13Z2vJAG4JFHcs7Xp4wRZ9avxetH5A00ph3nK+xbRc999broV4MbRWQ7YhXD dZBqWUNkJnNfsIT6OHgIDk9AStHDoc/HmXLDBv/eer0ygYXftMaoW69iPcjnThY24U wTa1M3noMGLKpdcEOHqMWXrDxFuIa8ITEsl85dggCgzthHhA4wJ1xu589XgRWg17nf /fVzaGvchLtKl22JkEF1aqOYhN1aLYJJw/IBFrr3gpA1vOZQBJOjVLXTR4KbQdDgFz n5oeifLX6jR5g== From: Marek Vasut To: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Peng Fan , Adam Ford , Alice Guo , Amit Kucheria , Daniel Lezcano , Fabio Estevam , Krzysztof Kozlowski , Li Jun , Lucas Stach , Markus Niebel , NXP Linux Team , Pengutronix Kernel Team , "Rafael J . Wysocki" , Richard Cochran , Rob Herring , Sascha Hauer , Shawn Guo , Zhang Rui , devicetree@vger.kernel.org Subject: [PATCH v3 3/5] arm64: dts: imx8m: Document the fuse address calculation Date: Fri, 2 Dec 2022 17:23:51 +0100 Message-Id: <20221202162353.274009-3-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221202162353.274009-1-marex@denx.de> References: <20221202162353.274009-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The mapping from OCOTP reg DT property to Fusemap Descriptions Table in the datasheet is often unclear. Add a comment to make it easier to find out how it works. No functional change. Reviewed-by: Peng Fan Signed-off-by: Marek Vasut --- Cc: Adam Ford Cc: Alice Guo Cc: Amit Kucheria Cc: Daniel Lezcano Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Li Jun Cc: Lucas Stach Cc: Markus Niebel Cc: NXP Linux Team Cc: Peng Fan Cc: Pengutronix Kernel Team Cc: Rafael J. Wysocki Cc: Richard Cochran Cc: Rob Herring Cc: Sascha Hauer Cc: Shawn Guo Cc: Zhang Rui Cc: devicetree@vger.kernel.org To: linux-pm@vger.kernel.org To: linux-arm-kernel@lists.infradead.org --- V2: Add RB from Peng V3: No change --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 19 ++++++++++++++++--- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 19 ++++++++++++++++--- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 21 +++++++++++++++++---- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 19 ++++++++++++++++--- 4 files changed, 65 insertions(+), 13 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 423cb36cbcd53..513c2de0caa15 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -563,15 +563,28 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; - imx8mm_uid: unique-id@4 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = ; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mm_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - fec_mac_address: mac-address@90 { + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 312e3abc35ea8..068f599cdf757 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -564,15 +564,28 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; - imx8mn_uid: unique-id@4 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = ; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mn_uid: unique-id@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - fec_mac_address: mac-address@90 { + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index c9459ed21b243..ddcd5e23ba47d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -426,19 +426,32 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; - imx8mp_uid: unique-id@8 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = ; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x8 0x8> describes fuses 0x420 and + * 0x430). + */ + imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ reg = <0x8 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - eth_mac1: mac-address@90 { + eth_mac1: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; - eth_mac2: mac-address@96 { + eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 2b6d3f4ff5d93..8a2ec90b493d9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -593,15 +593,28 @@ ocotp: efuse@30350000 { #address-cells = <1>; #size-cells = <1>; - imx8mq_uid: soc-uid@4 { + /* + * The register address below maps to the MX8M + * Fusemap Description Table entries this way. + * Assuming + * reg = ; + * then + * Fuse Address = (ADDR * 4) + 0x400 + * Note that if SIZE is greater than 4, then + * each subsequent fuse is located at offset + * +0x10 in Fusemap Description Table (e.g. + * reg = <0x4 0x8> describes fuses 0x410 and + * 0x420). + */ + imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */ reg = <0x4 0x8>; }; - cpu_speed_grade: speed-grade@10 { + cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; - fec_mac_address: mac-address@90 { + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; }; From patchwork Fri Dec 2 16:23:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 630944 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C60CC63706 for ; Fri, 2 Dec 2022 16:25:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233977AbiLBQZo (ORCPT ); Fri, 2 Dec 2022 11:25:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233997AbiLBQZX (ORCPT ); Fri, 2 Dec 2022 11:25:23 -0500 Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8304955A2; Fri, 2 Dec 2022 08:24:15 -0800 (PST) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 8C69D85059; Fri, 2 Dec 2022 17:24:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1669998254; bh=oC2RfYDBCDmy6yoSbXjoZS9LjpfPx/ya6P5cWNUhJh4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=O1O/Eim2YydtxObd01vacxLfnwsnBEcEfWKUwBuqn5qIiCYs/eRXGNQ5l/hps++Hy K/q8XZrzKKWkUqmEYKqJ2oc096vkfFiZGrB/02g60PlStoAI8ETX/IAOXO7Jlos2Of v6ZMMhVpkmzaOkpPJu9kGWfoyqsjKS531KF6C4T1triwZjnIrGbOnGHg/E/aq7Lf88 Uuzg0w7eYW19srtk5WWYQHaikYU1/D20J0H+ny3mbGsH82c/4g8LwJAf0GuEtfUAnr tzvrb9S7J8P7KwV6XCu8aRYMpgFdv9kK0I64axltQnxC8qopj74SdobX7jUfNXLz52 Nu3nZqDoiNpMA== From: Marek Vasut To: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Peng Fan , Adam Ford , Alice Guo , Amit Kucheria , Daniel Lezcano , Fabio Estevam , Krzysztof Kozlowski , Li Jun , Lucas Stach , Markus Niebel , NXP Linux Team , Pengutronix Kernel Team , "Rafael J . Wysocki" , Richard Cochran , Rob Herring , Sascha Hauer , Shawn Guo , Zhang Rui , devicetree@vger.kernel.org Subject: [PATCH v3 4/5] arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP Date: Fri, 2 Dec 2022 17:23:52 +0100 Message-Id: <20221202162353.274009-4-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221202162353.274009-1-marex@denx.de> References: <20221202162353.274009-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with calibration values in OCOTP. Add the OCOTP calibration values phandle so the TMU driver can perform this programming. The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4. Reviewed-by: Peng Fan Signed-off-by: Marek Vasut --- Cc: Adam Ford Cc: Alice Guo Cc: Amit Kucheria Cc: Daniel Lezcano Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Li Jun Cc: Lucas Stach Cc: Markus Niebel Cc: NXP Linux Team Cc: Peng Fan Cc: Pengutronix Kernel Team Cc: Rafael J. Wysocki Cc: Richard Cochran Cc: Rob Herring Cc: Sascha Hauer Cc: Shawn Guo Cc: Zhang Rui Cc: devicetree@vger.kernel.org To: linux-pm@vger.kernel.org To: linux-arm-kernel@lists.infradead.org --- V2: Add RB from Peng V3: No change --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 513c2de0caa15..0cd7fff47c44d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -496,6 +496,8 @@ tmu: tmu@30260000 { compatible = "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; }; @@ -584,6 +586,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; + tmu_calib: calib@3c { /* 0x4f0 */ + reg = <0x3c 4>; + }; + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 068f599cdf757..5eef9b274edde 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -498,6 +498,8 @@ tmu: tmu@30260000 { compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MN_CLK_TMU_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <0>; }; @@ -585,6 +587,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */ reg = <0x10 4>; }; + tmu_calib: calib@3c { /* 0x4f0 */ + reg = <0x3c 4>; + }; + fec_mac_address: mac-address@90 { /* 0x640 */ reg = <0x90 6>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index ddcd5e23ba47d..0173e394ad4d8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -380,6 +380,8 @@ tmu: tmu@30260000 { compatible = "fsl,imx8mp-tmu"; reg = <0x30260000 0x10000>; clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; + nvmem-cells = <&tmu_calib>; + nvmem-cell-names = "calib"; #thermal-sensor-cells = <1>; }; @@ -454,6 +456,10 @@ eth_mac1: mac-address@90 { /* 0x640 */ eth_mac2: mac-address@96 { /* 0x658 */ reg = <0x96 6>; }; + + tmu_calib: calib@264 { /* 0xd90-0xdc0 */ + reg = <0x264 0x10>; + }; }; anatop: clock-controller@30360000 { From patchwork Fri Dec 2 16:23:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Vasut X-Patchwork-Id: 630410 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDC43C47090 for ; Fri, 2 Dec 2022 16:25:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233987AbiLBQZo (ORCPT ); Fri, 2 Dec 2022 11:25:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37284 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234011AbiLBQZY (ORCPT ); Fri, 2 Dec 2022 11:25:24 -0500 Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 196045F86; Fri, 2 Dec 2022 08:24:16 -0800 (PST) Received: from tr.lan (ip-86-49-120-218.bb.vodafone.cz [86.49.120.218]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 3158D850CB; Fri, 2 Dec 2022 17:24:14 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1669998254; bh=iHde2NMqBoGtBkyoPfcB8QQKtw2qTzVLTm3MY/RLBqs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fjEmuSdo3Rz4q07zvodZEwgB1fjchE3+bAEEXBp/X3mmJ8x8dMmsLlH1mpE8ujYvn yXmvC0BtxlFVpT/Inr8+06l+HVFW5YMbvbrJhmR6Bi9Mfx6bsoiFSOEeXpm1v10Frj oWrybLvz+68lWlN0urEOxHtsMCpH1YoX72a0xLY8I9X7xlWS7z6wXRBBOtVH622vft 2f99QIb9ZZO4Uf9cmxTi3Rl62aQyr3wdjc8liMEc3skwLmceNKXwQ8XIOlJJ3j3QeM g1SjaHquqqq54gP2cEA4oPMKHpJZSBA1q70lJktLJTgMMoz9kJGqxI37uwloaQnL7d Cb760JKrPFHtw== From: Marek Vasut To: linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Peng Fan , Adam Ford , Alice Guo , Amit Kucheria , Daniel Lezcano , Fabio Estevam , Krzysztof Kozlowski , Li Jun , Lucas Stach , Markus Niebel , NXP Linux Team , Pengutronix Kernel Team , "Rafael J . Wysocki" , Richard Cochran , Rob Herring , Sascha Hauer , Shawn Guo , Zhang Rui , devicetree@vger.kernel.org Subject: [PATCH v3 5/5] thermal/drivers/imx: Add support for loading calibration data from OCOTP Date: Fri, 2 Dec 2022 17:23:53 +0100 Message-Id: <20221202162353.274009-5-marex@denx.de> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221202162353.274009-1-marex@denx.de> References: <20221202162353.274009-1-marex@denx.de> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with calibration values in OCOTP. Add support for reading the OCOTP calibration data and programming those into the TMU hardware. The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4, the programming differs in each case. Based on U-Boot commits: 70487ff386c ("imx8mm: Load fuse for TMU TCALIV and TASR") ebb9aab318b ("imx: load calibration parameters from fuse for i.MX8MP") Reviewed-by: Peng Fan Signed-off-by: Marek Vasut --- Cc: Adam Ford Cc: Alice Guo Cc: Amit Kucheria Cc: Daniel Lezcano Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Li Jun Cc: Lucas Stach Cc: Markus Niebel Cc: NXP Linux Team Cc: Peng Fan Cc: Pengutronix Kernel Team Cc: Rafael J. Wysocki Cc: Richard Cochran Cc: Rob Herring Cc: Sascha Hauer Cc: Shawn Guo Cc: Zhang Rui Cc: devicetree@vger.kernel.org To: linux-pm@vger.kernel.org To: linux-arm-kernel@lists.infradead.org --- V2: - Add RB from Peng - Include slab.h to get kfree() definition V3: - Replace %ld with %zu --- drivers/thermal/imx8mm_thermal.c | 164 +++++++++++++++++++++++++++++++ 1 file changed, 164 insertions(+) diff --git a/drivers/thermal/imx8mm_thermal.c b/drivers/thermal/imx8mm_thermal.c index e2c2673025a7a..a8b04dc0023de 100644 --- a/drivers/thermal/imx8mm_thermal.c +++ b/drivers/thermal/imx8mm_thermal.c @@ -10,9 +10,11 @@ #include #include #include +#include #include #include #include +#include #include #include "thermal_core.h" @@ -20,6 +22,22 @@ #define TER 0x0 /* TMU enable */ #define TPS 0x4 #define TRITSR 0x20 /* TMU immediate temp */ +/* TMU calibration data registers */ +#define TASR 0x28 +#define TASR_BUF_SLOPE_MASK GENMASK(19, 16) +#define TASR_BUF_VREF_MASK GENMASK(4, 0) /* TMU_V1 */ +#define TASR_BUF_VERF_SEL_MASK GENMASK(1, 0) /* TMU_V2 */ +#define TCALIV(n) (0x30 + ((n) * 4)) +#define TCALIV_EN BIT(31) +#define TCALIV_HR_MASK GENMASK(23, 16) /* TMU_V1 */ +#define TCALIV_RT_MASK GENMASK(7, 0) /* TMU_V1 */ +#define TCALIV_SNSR105C_MASK GENMASK(27, 16) /* TMU_V2 */ +#define TCALIV_SNSR25C_MASK GENMASK(11, 0) /* TMU_V2 */ +#define TRIM 0x3c +#define TRIM_BJT_CUR_MASK GENMASK(23, 20) +#define TRIM_BGR_MASK GENMASK(31, 28) +#define TRIM_VLSB_MASK GENMASK(15, 12) +#define TRIM_EN_CH BIT(7) #define TER_ADC_PD BIT(30) #define TER_EN BIT(31) @@ -32,6 +50,25 @@ #define SIGN_BIT BIT(7) #define TEMP_VAL_MASK GENMASK(6, 0) +/* TMU OCOTP calibration data bitfields */ +#define ANA0_EN BIT(25) +#define ANA0_BUF_VREF_MASK GENMASK(24, 20) +#define ANA0_BUF_SLOPE_MASK GENMASK(19, 16) +#define ANA0_HR_MASK GENMASK(15, 8) +#define ANA0_RT_MASK GENMASK(7, 0) +#define TRIM2_VLSB_MASK GENMASK(23, 20) +#define TRIM2_BGR_MASK GENMASK(19, 16) +#define TRIM2_BJT_CUR_MASK GENMASK(15, 12) +#define TRIM2_BUF_SLOP_SEL_MASK GENMASK(11, 8) +#define TRIM2_BUF_VERF_SEL_MASK GENMASK(7, 6) +#define TRIM3_TCA25_0_LSB_MASK GENMASK(31, 28) +#define TRIM3_TCA40_0_MASK GENMASK(27, 16) +#define TRIM4_TCA40_1_MASK GENMASK(31, 20) +#define TRIM4_TCA105_0_MASK GENMASK(19, 8) +#define TRIM4_TCA25_0_MSB_MASK GENMASK(7, 0) +#define TRIM5_TCA105_1_MASK GENMASK(23, 12) +#define TRIM5_TCA25_1_MASK GENMASK(11, 0) + #define VER1_TEMP_LOW_LIMIT 10000 #define VER2_TEMP_LOW_LIMIT -40000 #define VER2_TEMP_HIGH_LIMIT 125000 @@ -128,6 +165,129 @@ static void imx8mm_tmu_probe_sel_all(struct imx8mm_tmu *tmu) writel_relaxed(val, tmu->base + TPS); } +static int imx8mm_tmu_probe_set_calib_v1(struct platform_device *pdev, + struct imx8mm_tmu *tmu) +{ + struct device *dev = &pdev->dev; + u32 ana0; + int ret; + + ret = nvmem_cell_read_u32(&pdev->dev, "calib", &ana0); + if (ret) { + dev_warn(dev, "Failed to read OCOTP nvmem cell (%d).\n", ret); + return ret; + } + + writel(FIELD_PREP(TASR_BUF_VREF_MASK, + FIELD_GET(ANA0_BUF_VREF_MASK, ana0)) | + FIELD_PREP(TASR_BUF_SLOPE_MASK, + FIELD_GET(ANA0_BUF_SLOPE_MASK, ana0)), + tmu->base + TASR); + + writel(FIELD_PREP(TCALIV_RT_MASK, FIELD_GET(ANA0_RT_MASK, ana0)) | + FIELD_PREP(TCALIV_HR_MASK, FIELD_GET(ANA0_HR_MASK, ana0)) | + ((ana0 & ANA0_EN) ? TCALIV_EN : 0), + tmu->base + TCALIV(0)); + + return 0; +} + +static int imx8mm_tmu_probe_set_calib_v2(struct platform_device *pdev, + struct imx8mm_tmu *tmu) +{ + struct device *dev = &pdev->dev; + struct nvmem_cell *cell; + u32 trim[4] = { 0 }; + size_t len; + void *buf; + + cell = nvmem_cell_get(dev, "calib"); + if (IS_ERR(cell)) + return PTR_ERR(cell); + + buf = nvmem_cell_read(cell, &len); + nvmem_cell_put(cell); + + if (IS_ERR(buf)) + return PTR_ERR(buf); + + memcpy(trim, buf, min(len, sizeof(trim))); + kfree(buf); + + if (len != 16) { + dev_err(dev, + "OCOTP nvmem cell length is %zu, must be 16.\n", len); + return -EINVAL; + } + + /* Blank sample hardware */ + if (!trim[0] && !trim[1] && !trim[2] && !trim[3]) { + /* Use a default 25C binary codes */ + writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c), + tmu->base + TCALIV(0)); + writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c), + tmu->base + TCALIV(1)); + return 0; + } + + writel(FIELD_PREP(TASR_BUF_VERF_SEL_MASK, + FIELD_GET(TRIM2_BUF_VERF_SEL_MASK, trim[0])) | + FIELD_PREP(TASR_BUF_SLOPE_MASK, + FIELD_GET(TRIM2_BUF_SLOP_SEL_MASK, trim[0])), + tmu->base + TASR); + + writel(FIELD_PREP(TRIM_BJT_CUR_MASK, + FIELD_GET(TRIM2_BJT_CUR_MASK, trim[0])) | + FIELD_PREP(TRIM_BGR_MASK, FIELD_GET(TRIM2_BGR_MASK, trim[0])) | + FIELD_PREP(TRIM_VLSB_MASK, FIELD_GET(TRIM2_VLSB_MASK, trim[0])) | + TRIM_EN_CH, + tmu->base + TRIM); + + writel(FIELD_PREP(TCALIV_SNSR25C_MASK, + FIELD_GET(TRIM3_TCA25_0_LSB_MASK, trim[1]) | + (FIELD_GET(TRIM4_TCA25_0_MSB_MASK, trim[2]) << 4)) | + FIELD_PREP(TCALIV_SNSR105C_MASK, + FIELD_GET(TRIM4_TCA105_0_MASK, trim[2])), + tmu->base + TCALIV(0)); + + writel(FIELD_PREP(TCALIV_SNSR25C_MASK, + FIELD_GET(TRIM5_TCA25_1_MASK, trim[3])) | + FIELD_PREP(TCALIV_SNSR105C_MASK, + FIELD_GET(TRIM5_TCA105_1_MASK, trim[3])), + tmu->base + TCALIV(1)); + + writel(FIELD_PREP(TCALIV_SNSR25C_MASK, + FIELD_GET(TRIM3_TCA40_0_MASK, trim[1])) | + FIELD_PREP(TCALIV_SNSR105C_MASK, + FIELD_GET(TRIM4_TCA40_1_MASK, trim[2])), + tmu->base + TCALIV(2)); + + return 0; +} + +static int imx8mm_tmu_probe_set_calib(struct platform_device *pdev, + struct imx8mm_tmu *tmu) +{ + struct device *dev = &pdev->dev; + + /* + * Lack of calibration data OCOTP reference is not considered + * fatal to retain compatibility with old DTs. It is however + * strongly recommended to update such old DTs to get correct + * temperature compensation values for each SoC. + */ + if (!of_find_property(pdev->dev.of_node, "nvmem-cells", NULL)) { + dev_warn(dev, + "No OCOTP nvmem reference found, SoC-specific calibration not loaded. Please update your DT.\n"); + return 0; + } + + if (tmu->socdata->version == TMU_VER1) + return imx8mm_tmu_probe_set_calib_v1(pdev, tmu); + + return imx8mm_tmu_probe_set_calib_v2(pdev, tmu); +} + static int imx8mm_tmu_probe(struct platform_device *pdev) { const struct thermal_soc_data *data; @@ -180,6 +340,10 @@ static int imx8mm_tmu_probe(struct platform_device *pdev) platform_set_drvdata(pdev, tmu); + ret = imx8mm_tmu_probe_set_calib(pdev, tmu); + if (ret) + goto disable_clk; + /* enable all the probes for V2 TMU */ if (tmu->socdata->version == TMU_VER2) imx8mm_tmu_probe_sel_all(tmu);