From patchwork Fri Mar 22 08:58:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 160880 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp557417jan; Fri, 22 Mar 2019 01:58:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqyt0S1NtI8u3Q2RpVB8+HH92ldOjhNIfHSUi2Q48o6Qe9WFAr5U/95LOzJeT3P257YxgSYJ X-Received: by 2002:a17:902:421:: with SMTP id 30mr8245580ple.142.1553245098628; Fri, 22 Mar 2019 01:58:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553245098; cv=none; d=google.com; s=arc-20160816; b=OlSBXCfvXTkoqBbnovK+QOJ4Q04UyXyp1lRGbIOq/b6YQfQGDAdjVPfbZqKpFNezuF rgT1xCSbfGzTX7lw7yrEx9ZfluxwjzFl0fRgLnbINSVgeToymvkP0+fvV7Bt9wgu5OGR 7/4p5gEfAvHgN+F/MDQxnggSHMk02mL+gmDba83CBAEpSKRw0S6Xll2lxAy6v96Wge9M I1Z/0rcSE1KxbArT18ZFca/vsJ/spGTDcDixQVug6JMmJ909IdcwpTDMFGh/p5xvxfMt fx2vPaBByV4fTsL1Td8GIjOh//JYlYstnGL+Vi+m3WstfQMSXQSM3ugmfkQPO/mQRdeR U8vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=JZva8GreHTBsEQhYw2VOI3/fonXSa/Q4j46jwDuckpc=; b=C39+ut1V3V2Vzkk9pHxrU1Hgq4yhygAW9E6ZPimTm8jSzCF2A8uf73zVBoPMLGZ/fo GNNn5fpfmbb79HAe4cq4ZmJspfamN9p3d6vvnMvPY30O1uDFiqmfaNo/ads25GVHGPDt 26eb+OcUwA58hfGaS1Zy5UaBCctTl/ZngP/48UEItJeG8eafnz9lci5o33c81Qs36OFB mPTqE2+q+lVc03hlBxleiE1jR3Uj52kbXo/uMJU2kcHUQOsaLXcTDWqiMzLcgDaAwgRI z9V1iNsdjNpS1XZ22X2pUlSTRasaxwTANpw/r03GELr+recR9dmIrXm/ouQ3cluenexH LJWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jWB69jl+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e17si6008425pgo.44.2019.03.22.01.58.18; Fri, 22 Mar 2019 01:58:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jWB69jl+; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727852AbfCVI6R (ORCPT + 31 others); Fri, 22 Mar 2019 04:58:17 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:60476 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726029AbfCVI6Q (ORCPT ); Fri, 22 Mar 2019 04:58:16 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2M8wFAX027051 for ; Fri, 22 Mar 2019 03:58:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553245095; bh=JZva8GreHTBsEQhYw2VOI3/fonXSa/Q4j46jwDuckpc=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=jWB69jl+FUiImZckWL9UiUDuL/dBklttukW5SpxbvTkpzxtXrzWht4KPGRa8+kA4y I+4C8uJaS7PKUHyZ0dkXftqdx3DzPGYB8rsygpqBDDVD1QrFZFUMq00sGULhMMl0zZ fytUFM2dCUUKCbfGjsavVZf0+nEa2Rz/GCUpiI8E= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2M8wFPo076747 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Fri, 22 Mar 2019 03:58:15 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 22 Mar 2019 03:58:13 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Fri, 22 Mar 2019 03:58:13 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2M8w9b7016866; Fri, 22 Mar 2019 03:58:11 -0500 From: Roger Quadros To: CC: , , , Roger Quadros Subject: [PATCH 1/4] phy: ti-pipe3: Introduce mode property in driver data Date: Fri, 22 Mar 2019 10:58:04 +0200 Message-ID: <20190322085807.30216-2-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190322085807.30216-1-rogerq@ti.com> References: <20190322085807.30216-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce a mode property in the driver data so that we don't have to keep using "of_device_is_compatible()" throughtout the driver. No functional change. Signed-off-by: Roger Quadros --- drivers/phy/ti/phy-ti-pipe3.c | 93 +++++++++++++++++++++-------------- 1 file changed, 57 insertions(+), 36 deletions(-) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c index 68ce4a082b9b..0913dd55d82a 100644 --- a/drivers/phy/ti/phy-ti-pipe3.c +++ b/drivers/phy/ti/phy-ti-pipe3.c @@ -110,6 +110,10 @@ #define PLL_IDLE_TIME 100 /* in milliseconds */ #define PLL_LOCK_TIME 100 /* in milliseconds */ +enum pipe3_mode { PIPE3_MODE_PCIE = 1, + PIPE3_MODE_SATA, + PIPE3_MODE_USBSS }; + struct pipe3_dpll_params { u16 m; u8 n; @@ -141,6 +145,7 @@ struct ti_pipe3 { unsigned int power_reg; /* power reg. index within syscon */ unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */ bool sata_refclk_enabled; + enum pipe3_mode mode; }; static struct pipe3_dpll_map dpll_map_usb[] = { @@ -163,6 +168,25 @@ static struct pipe3_dpll_map dpll_map_sata[] = { { }, /* Terminator */ }; +struct pipe3_data { + enum pipe3_mode mode; + struct pipe3_dpll_map *dpll_map; +}; + +static struct pipe3_data data_usb = { + .mode = PIPE3_MODE_USBSS, + .dpll_map = dpll_map_usb, +}; + +static struct pipe3_data data_sata = { + .mode = PIPE3_MODE_SATA, + .dpll_map = dpll_map_sata, +}; + +static struct pipe3_data data_pcie = { + .mode = PIPE3_MODE_PCIE, +}; + static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset) { return __raw_readl(addr + offset); @@ -340,7 +364,7 @@ static int ti_pipe3_init(struct phy *x) * as recommended in AM572x TRM SPRUHZ6, section 18.5.2.2, table * 18-1804. */ - if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) { + if (phy->mode == PIPE3_MODE_PCIE) { if (!phy->pcs_syscon) { omap_control_pcie_pcs(phy->control_dev, 0x96); return 0; @@ -367,8 +391,7 @@ static int ti_pipe3_init(struct phy *x) /* SATA has issues if re-programmed when locked */ val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if ((val & PLL_LOCK) && of_device_is_compatible(phy->dev->of_node, - "ti,phy-pipe3-sata")) + if ((val & PLL_LOCK) && phy->mode == PIPE3_MODE_SATA) return ret; /* Program the DPLL */ @@ -390,12 +413,11 @@ static int ti_pipe3_exit(struct phy *x) /* If dpll_reset_syscon is not present we wont power down SATA DPLL * due to Errata i783 */ - if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata") && - !phy->dpll_reset_syscon) + if (phy->mode == PIPE3_MODE_SATA && !phy->dpll_reset_syscon) return 0; /* PCIe doesn't have internal DPLL */ - if (!of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-pcie")) { + if (phy->mode != PIPE3_MODE_PCIE) { /* Put DPLL in IDLE mode */ val = ti_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); val |= PLL_IDLE; @@ -418,7 +440,7 @@ static int ti_pipe3_exit(struct phy *x) } /* i783: SATA needs control bit toggle after PLL unlock */ - if (of_device_is_compatible(phy->dev->of_node, "ti,phy-pipe3-sata")) { + if (phy->mode == PIPE3_MODE_SATA) { regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg, SATA_PLL_SOFT_RESET, SATA_PLL_SOFT_RESET); regmap_update_bits(phy->dpll_reset_syscon, phy->dpll_reset_reg, @@ -443,7 +465,6 @@ static int ti_pipe3_get_clk(struct ti_pipe3 *phy) { struct clk *clk; struct device *dev = phy->dev; - struct device_node *node = dev->of_node; phy->refclk = devm_clk_get(dev, "refclk"); if (IS_ERR(phy->refclk)) { @@ -451,11 +472,11 @@ static int ti_pipe3_get_clk(struct ti_pipe3 *phy) /* older DTBs have missing refclk in SATA PHY * so don't bail out in case of SATA PHY. */ - if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) + if (phy->mode != PIPE3_MODE_SATA) return PTR_ERR(phy->refclk); } - if (!of_device_is_compatible(node, "ti,phy-pipe3-sata")) { + if (phy->mode != PIPE3_MODE_SATA) { phy->wkupclk = devm_clk_get(dev, "wkupclk"); if (IS_ERR(phy->wkupclk)) { dev_err(dev, "unable to get wkupclk\n"); @@ -465,8 +486,7 @@ static int ti_pipe3_get_clk(struct ti_pipe3 *phy) phy->wkupclk = ERR_PTR(-ENODEV); } - if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie") || - phy->phy_power_syscon) { + if (phy->mode != PIPE3_MODE_PCIE || phy->phy_power_syscon) { phy->sys_clk = devm_clk_get(dev, "sysclk"); if (IS_ERR(phy->sys_clk)) { dev_err(dev, "unable to get sysclk\n"); @@ -474,7 +494,7 @@ static int ti_pipe3_get_clk(struct ti_pipe3 *phy) } } - if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) { + if (phy->mode == PIPE3_MODE_PCIE) { clk = devm_clk_get(dev, "dpll_ref"); if (IS_ERR(clk)) { dev_err(dev, "unable to get dpll ref clk\n"); @@ -546,7 +566,7 @@ static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy) phy->control_dev = &control_pdev->dev; } - if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) { + if (phy->mode == PIPE3_MODE_PCIE) { phy->pcs_syscon = syscon_regmap_lookup_by_phandle(node, "syscon-pcs"); if (IS_ERR(phy->pcs_syscon)) { @@ -564,7 +584,7 @@ static int ti_pipe3_get_sysctrl(struct ti_pipe3 *phy) } } - if (of_device_is_compatible(node, "ti,phy-pipe3-sata")) { + if (phy->mode == PIPE3_MODE_SATA) { phy->dpll_reset_syscon = syscon_regmap_lookup_by_phandle(node, "syscon-pllreset"); if (IS_ERR(phy->dpll_reset_syscon)) { @@ -589,10 +609,9 @@ static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy) { struct resource *res; struct device *dev = phy->dev; - struct device_node *node = dev->of_node; struct platform_device *pdev = to_platform_device(dev); - if (!of_device_is_compatible(node, "ti,phy-pipe3-pcie")) + if (phy->mode != PIPE3_MODE_PCIE) return 0; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, @@ -611,24 +630,12 @@ static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy) static int ti_pipe3_get_pll_base(struct ti_pipe3 *phy) { struct resource *res; - const struct of_device_id *match; struct device *dev = phy->dev; - struct device_node *node = dev->of_node; struct platform_device *pdev = to_platform_device(dev); - if (of_device_is_compatible(node, "ti,phy-pipe3-pcie")) + if (phy->mode == PIPE3_MODE_PCIE) return 0; - match = of_match_device(ti_pipe3_id_table, dev); - if (!match) - return -EINVAL; - - phy->dpll_map = (struct pipe3_dpll_map *)match->data; - if (!phy->dpll_map) { - dev_err(dev, "no DPLL data\n"); - return -EINVAL; - } - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll_ctrl"); phy->pll_ctrl_base = devm_ioremap_resource(dev, res); @@ -640,15 +647,28 @@ static int ti_pipe3_probe(struct platform_device *pdev) struct ti_pipe3 *phy; struct phy *generic_phy; struct phy_provider *phy_provider; - struct device_node *node = pdev->dev.of_node; struct device *dev = &pdev->dev; int ret; + const struct of_device_id *match; + struct pipe3_data *data; phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); if (!phy) return -ENOMEM; - phy->dev = dev; + match = of_match_device(ti_pipe3_id_table, dev); + if (!match) + return -EINVAL; + + data = (struct pipe3_data *)match->data; + if (!data) { + dev_err(dev, "no driver data\n"); + return -EINVAL; + } + + phy->dev = dev; + phy->mode = data->mode; + phy->dpll_map = data->dpll_map; ret = ti_pipe3_get_pll_base(phy); if (ret) @@ -672,7 +692,7 @@ static int ti_pipe3_probe(struct platform_device *pdev) /* * Prevent auto-disable of refclk for SATA PHY due to Errata i783 */ - if (of_device_is_compatible(node, "ti,phy-pipe3-sata")) { + if (phy->mode == PIPE3_MODE_SATA) { if (!IS_ERR(phy->refclk)) { clk_prepare_enable(phy->refclk); phy->sata_refclk_enabled = true; @@ -762,18 +782,19 @@ static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy) static const struct of_device_id ti_pipe3_id_table[] = { { .compatible = "ti,phy-usb3", - .data = dpll_map_usb, + .data = &data_usb, }, { .compatible = "ti,omap-usb3", - .data = dpll_map_usb, + .data = &data_usb, }, { .compatible = "ti,phy-pipe3-sata", - .data = dpll_map_sata, + .data = &data_sata, }, { .compatible = "ti,phy-pipe3-pcie", + .data = &data_pcie, }, {} }; From patchwork Fri Mar 22 08:58:05 2019 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id v198si3827557pgb.204.2019.03.22.01.58.24; Fri, 22 Mar 2019 01:58:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=kTOnW31I; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727904AbfCVI6V (ORCPT + 31 others); Fri, 22 Mar 2019 04:58:21 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:60478 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727744AbfCVI6S (ORCPT ); Fri, 22 Mar 2019 04:58:18 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2M8wGkD027062 for ; Fri, 22 Mar 2019 03:58:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553245096; bh=fTjnIsuQ8hpmovpcLwfvsAPy/Ud+Kro/q2XdWGbTPcI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kTOnW31IOSknDw7wMiL+0sXeLrSzOnLqfgOSAbqhXevTt4aEGuUZgUACq9vsrP5At LS7E+kfc0YUmxYGTIFfdOcObRJgplzDsPSsTEbISODN6UdeG++iTesiy73ysTUJKxD gTlFPDE30agGFbQltMXZov0503860kN87f4wZd/k= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2M8wGWZ104339 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL) for ; Fri, 22 Mar 2019 03:58:16 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Fri, 22 Mar 2019 03:58:14 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1713.5 via Frontend Transport; Fri, 22 Mar 2019 03:58:14 -0500 Received: from lta0400828d.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x2M8w9b8016866; Fri, 22 Mar 2019 03:58:13 -0500 From: Roger Quadros To: CC: , , , Roger Quadros Subject: [PATCH 2/4] phy: ti-pipe3: improve DPLL stability for SATA & USB Date: Fri, 22 Mar 2019 10:58:05 +0200 Message-ID: <20190322085807.30216-3-rogerq@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190322085807.30216-1-rogerq@ti.com> References: <20190322085807.30216-1-rogerq@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For increased DPLL stability use the settings recommended in the TRM [1] for PHY_RX registers for SATA and USB. For SATA we need to use spread spectrum settings even though we don't have spread spectrum enabled. The suggested non-spread spectrum settings don't work. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros --- drivers/phy/ti/phy-ti-pipe3.c | 215 +++++++++++++++++++++++++++------- 1 file changed, 173 insertions(+), 42 deletions(-) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c index 0913dd55d82a..cdc994f153b2 100644 --- a/drivers/phy/ti/phy-ti-pipe3.c +++ b/drivers/phy/ti/phy-ti-pipe3.c @@ -68,39 +68,61 @@ #define PCIE_PCS_MASK 0xFF0000 #define PCIE_PCS_DELAY_COUNT_SHIFT 0x10 -#define PCIEPHYRX_ANA_PROGRAMMABILITY 0x0000000C +#define PIPE3_PHY_RX_ANA_PROGRAMMABILITY 0x0000000C #define INTERFACE_MASK GENMASK(31, 27) #define INTERFACE_SHIFT 27 +#define INTERFACE_MODE_USBSS BIT(4) +#define INTERFACE_MODE_SATA_1P5 BIT(3) +#define INTERFACE_MODE_SATA_3P0 BIT(2) +#define INTERFACE_MODE_PCIE BIT(0) + #define LOSD_MASK GENMASK(17, 14) #define LOSD_SHIFT 14 #define MEM_PLLDIV GENMASK(6, 5) -#define PCIEPHYRX_TRIM 0x0000001C -#define MEM_DLL_TRIM_SEL GENMASK(31, 30) +#define PIPE3_PHY_RX_TRIM 0x0000001C +#define MEM_DLL_TRIM_SEL_MASK GENMASK(31, 30) #define MEM_DLL_TRIM_SHIFT 30 -#define PCIEPHYRX_DLL 0x00000024 -#define MEM_DLL_PHINT_RATE GENMASK(31, 30) +#define PIPE3_PHY_RX_DLL 0x00000024 +#define MEM_DLL_PHINT_RATE_MASK GENMASK(31, 30) +#define MEM_DLL_PHINT_RATE_SHIFT 30 -#define PCIEPHYRX_DIGITAL_MODES 0x00000028 +#define PIPE3_PHY_RX_DIGITAL_MODES 0x00000028 +#define MEM_HS_RATE_MASK GENMASK(28, 27) +#define MEM_HS_RATE_SHIFT 27 +#define MEM_OVRD_HS_RATE BIT(26) +#define MEM_OVRD_HS_RATE_SHIFT 26 #define MEM_CDR_FASTLOCK BIT(23) -#define MEM_CDR_LBW GENMASK(22, 21) -#define MEM_CDR_STEPCNT GENMASK(20, 19) +#define MEM_CDR_FASTLOCK_SHIFT 23 +#define MEM_CDR_LBW_MASK GENMASK(22, 21) +#define MEM_CDR_LBW_SHIFT 21 +#define MEM_CDR_STEPCNT_MASK GENMASK(20, 19) +#define MEM_CDR_STEPCNT_SHIFT 19 #define MEM_CDR_STL_MASK GENMASK(18, 16) #define MEM_CDR_STL_SHIFT 16 #define MEM_CDR_THR_MASK GENMASK(15, 13) #define MEM_CDR_THR_SHIFT 13 #define MEM_CDR_THR_MODE BIT(12) -#define MEM_CDR_CDR_2NDO_SDM_MODE BIT(11) -#define MEM_OVRD_HS_RATE BIT(26) - -#define PCIEPHYRX_EQUALIZER 0x00000038 -#define MEM_EQLEV GENMASK(31, 16) -#define MEM_EQFTC GENMASK(15, 11) -#define MEM_EQCTL GENMASK(10, 7) +#define MEM_CDR_THR_MODE_SHIFT 12 +#define MEM_CDR_2NDO_SDM_MODE BIT(11) +#define MEM_CDR_2NDO_SDM_MODE_SHIFT 11 + +#define PIPE3_PHY_RX_EQUALIZER 0x00000038 +#define MEM_EQLEV_MASK GENMASK(31, 16) +#define MEM_EQLEV_SHIFT 16 +#define MEM_EQFTC_MASK GENMASK(15, 11) +#define MEM_EQFTC_SHIFT 11 +#define MEM_EQCTL_MASK GENMASK(10, 7) #define MEM_EQCTL_SHIFT 7 #define MEM_OVRD_EQLEV BIT(2) +#define MEM_OVRD_EQLEV_SHIFT 2 #define MEM_OVRD_EQFTC BIT(1) +#define MEM_OVRD_EQFTC_SHIFT 1 + +#define SATA_PHY_RX_IO_AND_A2D_OVERRIDES 0x44 +#define MEM_CDR_LOS_SOURCE_MASK GENMASK(10, 9) +#define MEM_CDR_LOS_SOURCE_SHIFT 9 /* * This is an Empirical value that works, need to confirm the actual @@ -127,6 +149,27 @@ struct pipe3_dpll_map { struct pipe3_dpll_params params; }; +struct pipe3_settings { + u8 ana_interface; + u8 ana_losd; + u8 dig_fastlock; + u8 dig_lbw; + u8 dig_stepcnt; + u8 dig_stl; + u8 dig_thr; + u8 dig_thr_mode; + u8 dig_2ndo_sdm_mode; + u8 dig_hs_rate; + u8 dig_ovrd_hs_rate; + u8 dll_trim_sel; + u8 dll_phint_rate; + u8 eq_lev; + u8 eq_ftc; + u8 eq_ctl; + u8 eq_ovrd_lev; + u8 eq_ovrd_ftc; +}; + struct ti_pipe3 { void __iomem *pll_ctrl_base; void __iomem *phy_rx; @@ -146,6 +189,7 @@ struct ti_pipe3 { unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */ bool sata_refclk_enabled; enum pipe3_mode mode; + struct pipe3_settings settings; }; static struct pipe3_dpll_map dpll_map_usb[] = { @@ -171,20 +215,84 @@ static struct pipe3_dpll_map dpll_map_sata[] = { struct pipe3_data { enum pipe3_mode mode; struct pipe3_dpll_map *dpll_map; + struct pipe3_settings settings; }; static struct pipe3_data data_usb = { .mode = PIPE3_MODE_USBSS, .dpll_map = dpll_map_usb, + .settings = { + /* DRA75x TRM Table 26-17. Preferred USB3_PHY_RX SCP Register Settings */ + .ana_interface = INTERFACE_MODE_USBSS, + .ana_losd = 0xa, + .dig_fastlock = 1, + .dig_lbw = 3, + .dig_stepcnt = 0, + .dig_stl = 0x3, + .dig_thr = 1, + .dig_thr_mode = 1, + .dig_2ndo_sdm_mode = 0, + .dig_hs_rate = 0, + .dig_ovrd_hs_rate = 1, + .dll_trim_sel = 0x2, + .dll_phint_rate = 0x3, + .eq_lev = 0, + .eq_ftc = 0, + .eq_ctl = 0x9, + .eq_ovrd_lev = 0, + .eq_ovrd_ftc = 0, + }, }; static struct pipe3_data data_sata = { .mode = PIPE3_MODE_SATA, .dpll_map = dpll_map_sata, + .settings = { + /* DRA75x TRM Table 26-9. Preferred SATA_PHY_RX SCP Register Settings */ + .ana_interface = INTERFACE_MODE_SATA_3P0, + .ana_losd = 0x5, + .dig_fastlock = 1, + .dig_lbw = 3, + .dig_stepcnt = 0, + .dig_stl = 0x3, + .dig_thr = 1, + .dig_thr_mode = 1, + .dig_2ndo_sdm_mode = 0, + .dig_hs_rate = 0, /* Not in TRM preferred settings */ + .dig_ovrd_hs_rate = 0, /* Not in TRM preferred settings */ + .dll_trim_sel = 0x1, + .dll_phint_rate = 0x2, /* for 1.5 GHz DPLL clock */ + .eq_lev = 0, + .eq_ftc = 0x1f, + .eq_ctl = 0, + .eq_ovrd_lev = 1, + .eq_ovrd_ftc = 1, + }, }; static struct pipe3_data data_pcie = { .mode = PIPE3_MODE_PCIE, + .settings = { + /* DRA75x TRM Table 26-62. Preferred PCIe_PHY_RX SCP Register Settings */ + .ana_interface = INTERFACE_MODE_PCIE, + .ana_losd = 0xa, + .dig_fastlock = 1, + .dig_lbw = 3, + .dig_stepcnt = 0, + .dig_stl = 0x3, + .dig_thr = 1, + .dig_thr_mode = 1, + .dig_2ndo_sdm_mode = 0, + .dig_hs_rate = 0, + .dig_ovrd_hs_rate = 0, + .dll_trim_sel = 0x2, + .dll_phint_rate = 0x3, + .eq_lev = 0, + .eq_ftc = 0x1f, + .eq_ctl = 1, + .eq_ovrd_lev = 0, + .eq_ovrd_ftc = 0, + }, }; static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset) @@ -324,32 +432,55 @@ static int ti_pipe3_dpll_program(struct ti_pipe3 *phy) static void ti_pipe3_calibrate(struct ti_pipe3 *phy) { u32 val; + struct pipe3_settings *s = &phy->settings; - val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_ANA_PROGRAMMABILITY); + val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY); val &= ~(INTERFACE_MASK | LOSD_MASK | MEM_PLLDIV); - val = (0x1 << INTERFACE_SHIFT | 0xA << LOSD_SHIFT); - ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_ANA_PROGRAMMABILITY, val); - - val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_DIGITAL_MODES); - val &= ~(MEM_CDR_STEPCNT | MEM_CDR_STL_MASK | MEM_CDR_THR_MASK | - MEM_CDR_CDR_2NDO_SDM_MODE | MEM_OVRD_HS_RATE); - val |= (MEM_CDR_FASTLOCK | MEM_CDR_LBW | 0x3 << MEM_CDR_STL_SHIFT | - 0x1 << MEM_CDR_THR_SHIFT | MEM_CDR_THR_MODE); - ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_DIGITAL_MODES, val); - - val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_TRIM); - val &= ~MEM_DLL_TRIM_SEL; - val |= 0x2 << MEM_DLL_TRIM_SHIFT; - ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_TRIM, val); - - val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_DLL); - val |= MEM_DLL_PHINT_RATE; - ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_DLL, val); - - val = ti_pipe3_readl(phy->phy_rx, PCIEPHYRX_EQUALIZER); - val &= ~(MEM_EQLEV | MEM_EQCTL | MEM_OVRD_EQLEV | MEM_OVRD_EQFTC); - val |= MEM_EQFTC | 0x1 << MEM_EQCTL_SHIFT; - ti_pipe3_writel(phy->phy_rx, PCIEPHYRX_EQUALIZER, val); + val = (s->ana_interface << INTERFACE_SHIFT | s->ana_losd << LOSD_SHIFT); + ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_ANA_PROGRAMMABILITY, val); + + val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES); + val &= ~(MEM_HS_RATE_MASK | MEM_OVRD_HS_RATE | MEM_CDR_FASTLOCK | + MEM_CDR_LBW_MASK | MEM_CDR_STEPCNT_MASK | MEM_CDR_STL_MASK | + MEM_CDR_THR_MASK | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE); + val |= s->dig_hs_rate << MEM_HS_RATE_SHIFT | + s->dig_ovrd_hs_rate << MEM_OVRD_HS_RATE_SHIFT | + s->dig_fastlock << MEM_CDR_FASTLOCK_SHIFT | + s->dig_lbw << MEM_CDR_LBW_SHIFT | + s->dig_stepcnt << MEM_CDR_STEPCNT_SHIFT | + s->dig_stl << MEM_CDR_STL_SHIFT | + s->dig_thr << MEM_CDR_THR_SHIFT | + s->dig_thr_mode << MEM_CDR_THR_MODE_SHIFT | + s->dig_2ndo_sdm_mode << MEM_CDR_2NDO_SDM_MODE_SHIFT; + ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DIGITAL_MODES, val); + + val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_TRIM); + val &= ~MEM_DLL_TRIM_SEL_MASK; + val |= s->dll_trim_sel << MEM_DLL_TRIM_SHIFT; + ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_TRIM, val); + + val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_DLL); + val &= ~MEM_DLL_PHINT_RATE_MASK; + val |= s->dll_phint_rate << MEM_DLL_PHINT_RATE_SHIFT; + ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_DLL, val); + + val = ti_pipe3_readl(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER); + val &= ~(MEM_EQLEV_MASK | MEM_EQFTC_MASK | MEM_EQCTL_MASK | + MEM_OVRD_EQLEV | MEM_OVRD_EQFTC); + val |= s->eq_lev << MEM_EQLEV_SHIFT | + s->eq_ftc << MEM_EQFTC_SHIFT | + s->eq_ctl << MEM_EQCTL_SHIFT | + s->eq_ovrd_lev << MEM_OVRD_EQLEV_SHIFT | + s->eq_ovrd_ftc << MEM_OVRD_EQFTC_SHIFT; + ti_pipe3_writel(phy->phy_rx, PIPE3_PHY_RX_EQUALIZER, val); + + if (phy->mode == PIPE3_MODE_SATA) { + val = ti_pipe3_readl(phy->phy_rx, + SATA_PHY_RX_IO_AND_A2D_OVERRIDES); + val &= ~MEM_CDR_LOS_SOURCE_MASK; + ti_pipe3_writel(phy->phy_rx, SATA_PHY_RX_IO_AND_A2D_OVERRIDES, + val); + } } static int ti_pipe3_init(struct phy *x) @@ -401,6 +532,8 @@ static int ti_pipe3_init(struct phy *x) return -EINVAL; } + ti_pipe3_calibrate(phy); + return ret; } @@ -611,9 +744,6 @@ static int ti_pipe3_get_tx_rx_base(struct ti_pipe3 *phy) struct device *dev = phy->dev; struct platform_device *pdev = to_platform_device(dev); - if (phy->mode != PIPE3_MODE_PCIE) - return 0; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy_rx"); phy->phy_rx = devm_ioremap_resource(dev, res); @@ -669,6 +799,7 @@ static int ti_pipe3_probe(struct platform_device *pdev) phy->dev = dev; phy->mode = data->mode; phy->dpll_map = data->dpll_map; + phy->settings = data->settings; ret = ti_pipe3_get_pll_base(phy); if (ret) From patchwork Fri Mar 22 08:58:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 160883 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp557586jan; Fri, 22 Mar 2019 01:58:32 -0700 (PDT) X-Google-Smtp-Source: APXvYqyt6EaD4bhxN/WAxFxZ5xZI/wNu1CWocfYneAd0igG8vnjC8jR+y7pWpWiEWJlnPv8sfO6w X-Received: by 2002:a17:902:8697:: with SMTP id g23mr8587660plo.30.1553245112907; Fri, 22 Mar 2019 01:58:32 -0700 (PDT) ARC-Seal: i=1; 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SATA PHY Subsystem Low-Level Programming Sequence" in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros --- drivers/phy/ti/phy-ti-pipe3.c | 44 ++++++++++++++++++++++++----------- 1 file changed, 30 insertions(+), 14 deletions(-) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c index cdc994f153b2..71a7634c026d 100644 --- a/drivers/phy/ti/phy-ti-pipe3.c +++ b/drivers/phy/ti/phy-ti-pipe3.c @@ -56,14 +56,14 @@ #define SATA_PLL_SOFT_RESET BIT(18) -#define PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000 +#define PIPE3_PHY_PWRCTL_CLK_CMD_MASK GENMASK(21, 14) #define PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 14 -#define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000 +#define PIPE3_PHY_PWRCTL_CLK_FREQ_MASK GENMASK(31, 22) #define PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 22 -#define PIPE3_PHY_TX_RX_POWERON 0x3 -#define PIPE3_PHY_TX_RX_POWEROFF 0x0 +#define PIPE3_PHY_RX_POWERON (0x1 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT) +#define PIPE3_PHY_TX_POWERON (0x2 << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT) #define PCIE_PCS_MASK 0xFF0000 #define PCIE_PCS_DELAY_COUNT_SHIFT 0x10 @@ -328,7 +328,6 @@ static void ti_pipe3_disable_clocks(struct ti_pipe3 *phy); static int ti_pipe3_power_off(struct phy *x) { - u32 val; int ret; struct ti_pipe3 *phy = phy_get_drvdata(x); @@ -337,10 +336,8 @@ static int ti_pipe3_power_off(struct phy *x) return 0; } - val = PIPE3_PHY_TX_RX_POWEROFF << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; - ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg, - PIPE3_PHY_PWRCTL_CLK_CMD_MASK, val); + PIPE3_PHY_PWRCTL_CLK_CMD_MASK, 0); return ret; } @@ -351,6 +348,7 @@ static int ti_pipe3_power_on(struct phy *x) int ret; unsigned long rate; struct ti_pipe3 *phy = phy_get_drvdata(x); + bool rx_pending = false; if (!phy->phy_power_syscon) { omap_control_phy_power(phy->control_dev, 1); @@ -363,14 +361,32 @@ static int ti_pipe3_power_on(struct phy *x) return -EINVAL; } rate = rate / 1000000; - mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK | - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK; - val = PIPE3_PHY_TX_RX_POWERON << PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; - val |= rate << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; - + mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK; + val = rate << OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; ret = regmap_update_bits(phy->phy_power_syscon, phy->power_reg, mask, val); - return ret; + /* + * For PCIe, TX and RX must be powered on simultaneously. + * For USB and SATA, TX must be powered on before RX + */ + mask = OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; + if (phy->mode == PIPE3_MODE_SATA || phy->mode == PIPE3_MODE_USBSS) { + val = PIPE3_PHY_TX_POWERON; + rx_pending = true; + } else { + val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON; + } + + regmap_update_bits(phy->phy_power_syscon, phy->power_reg, + mask, val); + + if (rx_pending) { + val = PIPE3_PHY_TX_POWERON | PIPE3_PHY_RX_POWERON; + regmap_update_bits(phy->phy_power_syscon, phy->power_reg, + mask, val); + } + + return 0; } static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy) From patchwork Fri Mar 22 08:58:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 160882 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp557509jan; Fri, 22 Mar 2019 01:58:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqwLc5uBTPr9VWgbm7VN1P7G+H7yqRgAD2+zQ2EwSIaM/BjOgnOUaooFkwD2JcwUVBreOrrt X-Received: by 2002:a17:902:76c1:: with SMTP id j1mr6760277plt.224.1553245105464; Fri, 22 Mar 2019 01:58:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553245105; cv=none; d=google.com; s=arc-20160816; b=YA8GybzGdDOJjo1noBXuzEcH90/wIlQl6AjTg3aLzjItiAtcJ9/7zFjP5vhcZNisrR tZmP9cMFXImmYOiq1t21AgIGx5MhPC0pEUQxGRw/Lj8g279wwLZd7A/9noeDMKyljlOD alspnmxYk/+WDFYSRyIeNw/BOWj8zY9h488OFy5YEv0HRV0MabMX+zWRXxGgNCESzcm0 bSpalm4bSVTSDuJUXBC/YVAp4atIClrR/VY68li/3oniwV095NjX0YmvJlUsUx9m6vKE En8z5p3Uz1Ez//pAGnkP3I85+VcWlYiVWuLwOzWdfam9d+QMY5Z0TVHKsoE6grTXa3HM Erqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=WYQ3YkHVR4l79yltClpUWyBrd1XOrHVgrBA+RFSZlWw=; b=GJt4/lY8FYh+rIbqKrBsctCok7o9B8y4zwpoo64sgEb36phZb/snJsFTVb8LPHH14s vy+GwK16m5eIfMcWaz+vt9w8xLFyn1HJqWKVLi3JwwvO4TtpLaAjy9HQQG/zJERvd4tX OnuC4pHjiR4Oy9WqphS+4ABcdvmPvtt5PAjiBers4ei3Gdt8x/56fjapfghlJ2YIJs8V J7D2iIKDM76ocPgqhHAWYLMf3FhpbPPxP723j3nocJNKXW7/YXaVqIQs4TQetkycp7CX wLhI6C+qjyaO7dAa9Z9l8sFFcUzihpehAp6XFUxxM5c33+CeZcsv5IkK4mpKJeqXuC+R Cl0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=U0BTqqzZ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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See "Table 26-81. PCIePHY Subsystem Low-Level Programming Sequence". [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf Signed-off-by: Roger Quadros --- drivers/phy/ti/phy-ti-pipe3.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki diff --git a/drivers/phy/ti/phy-ti-pipe3.c b/drivers/phy/ti/phy-ti-pipe3.c index 71a7634c026d..1718ef36d290 100644 --- a/drivers/phy/ti/phy-ti-pipe3.c +++ b/drivers/phy/ti/phy-ti-pipe3.c @@ -341,6 +341,8 @@ static int ti_pipe3_power_off(struct phy *x) return ret; } +static void ti_pipe3_calibrate(struct ti_pipe3 *phy); + static int ti_pipe3_power_on(struct phy *x) { u32 val; @@ -386,6 +388,9 @@ static int ti_pipe3_power_on(struct phy *x) mask, val); } + if (phy->mode == PIPE3_MODE_PCIE) + ti_pipe3_calibrate(phy); + return 0; } @@ -520,12 +525,7 @@ static int ti_pipe3_init(struct phy *x) val = 0x96 << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT; ret = regmap_update_bits(phy->pcs_syscon, phy->pcie_pcs_reg, PCIE_PCS_MASK, val); - if (ret) - return ret; - - ti_pipe3_calibrate(phy); - - return 0; + return ret; } /* Bring it out of IDLE if it is IDLE */