From patchwork Tue Nov 29 20:46:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 629252 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D608BC46467 for ; Tue, 29 Nov 2022 20:47:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236239AbiK2UrC (ORCPT ); Tue, 29 Nov 2022 15:47:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236203AbiK2Uq7 (ORCPT ); Tue, 29 Nov 2022 15:46:59 -0500 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B1D6264AE; Tue, 29 Nov 2022 12:46:58 -0800 (PST) Received: by mail-lf1-x131.google.com with SMTP id g12so23914416lfh.3; Tue, 29 Nov 2022 12:46:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=L0asAoMqwEnbLM8XD1/hLqCKMeXNAQ5meWtedT2j2eo=; b=mC4SrMSQU9Ksm7Z9Zz4jeSxnSoYtCEjCxvFktqIAj+LxH95z+9D/kcRn/sivbsj0pJ m6Ef20QJ3hJyPV0SpJr8TSDW0iofCGBAHDv+HSRNVa9CKihjvv6DQlXDRkP3olec+3iZ AxyBeHJcfmXbdDZrzOn5AaGQTga/gLhTz62cOY75YE0ftZypE9KiTXIJae8IggVONOl/ 2rx7e5gD9MvqzMaSNEWba2lUja6yHzCHFb5ptxvvShDAfHGIGobYrW0D6IK24q+rv5cY JgG44YqwSbFbhA4htr5UgOCHOAjhzoIZRdHlHLo8HPi9rdJdFUbMbPEJvy2f+LbtvZ3Z iW2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=L0asAoMqwEnbLM8XD1/hLqCKMeXNAQ5meWtedT2j2eo=; b=g92lK8ih6wgWxK9ZlElT4r4farJhVhhmffXpSqglK8qmf6eu0KUoANZXp8fHn+oVej IRfC0EQxxViQB0MgCS2eeZwbLK3IR8c1eNie6zqGYm7da060bJXg6hlENHPcOXXKZ4wK Ke5nKMWEzclQitLj23EenX87Ou1yWWO2zQ2dT6q02fsIp41sZ4zqjnCoCXySgCmb6xr7 yJAEVx9bWGO+jM4t4QR3IhL1Gb4vt6kFBgGR/bE0y8CjANK6agA4QQWBGbuQk09ZFfC8 XqBRygLnqKlxt7Ime+nNNeNmWbY0PnEbBVVZz/+HopstNRmAgKxkbz186pbQqlaollby 9WTw== X-Gm-Message-State: ANoB5pmIT3PJ2iypzlqWGoPmMltKZBx/KVVMdg3bKi4P4by6ueF76DVL 8OW2SIX8eC6UzJPTr/2IogkwNANR+Nw= X-Google-Smtp-Source: AA0mqf4sjfz5XraQ8YjoH//addmVdAEiibnccbFxPDlqD/xvyEbpMKoICP3OOzm3EoNjkzLiIeTwEg== X-Received: by 2002:a19:674a:0:b0:4b1:3931:af with SMTP id e10-20020a19674a000000b004b1393100afmr15582699lfj.394.1669754816507; Tue, 29 Nov 2022 12:46:56 -0800 (PST) Received: from localhost.localdomain (ccy110.neoplus.adsl.tpnet.pl. [83.30.148.110]) by smtp.gmail.com with ESMTPSA id o11-20020ac24e8b000000b004ae24368195sm2325620lfr.233.2022.11.29.12.46.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 12:46:56 -0800 (PST) From: Adam Skladowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Loic Poulain , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 02/12] dt-bindings: thermal: tsens: Add SM6115 compatible Date: Tue, 29 Nov 2022 21:46:06 +0100 Message-Id: <20221129204616.47006-3-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221129204616.47006-1-a39.skl@gmail.com> References: <20221129204616.47006-1-a39.skl@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document compatible for tsens on Qualcomm SM6115 platform according to downstream dts it ship v2.4 of IP Signed-off-by: Adam Skladowski --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 038d81338fcf..c41fcf404117 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -53,6 +53,7 @@ properties: - qcom,sc8280xp-tsens - qcom,sdm630-tsens - qcom,sdm845-tsens + - qcom,sm6115-tsens - qcom,sm6350-tsens - qcom,sm8150-tsens - qcom,sm8250-tsens From patchwork Tue Nov 29 20:46:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 629251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8058C4708A for ; Tue, 29 Nov 2022 20:47:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236459AbiK2UrP (ORCPT ); Tue, 29 Nov 2022 15:47:15 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236354AbiK2UrD (ORCPT ); Tue, 29 Nov 2022 15:47:03 -0500 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 94F39275EA; Tue, 29 Nov 2022 12:47:02 -0800 (PST) Received: by mail-lj1-x22f.google.com with SMTP id d3so18675637ljl.1; Tue, 29 Nov 2022 12:47:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=krQiwNIU1oFRdpbjQQ+MleaQuhQqE8OwDSXusURqx9Y=; b=RdETuYO3X/KpK5+RBMsxnPqzsHiwNIa9vB/SnoG99t5NLaUm5jq6e9CnJINRRBgXr8 QZJic4W2bIJbjmOGwnGY4NRiKpwaH2linOQwaspOjcT+2H3xzhV3ZvssIQZ0/h7nWnXk H3ZDySMz1tTWe7b9WtT2bEg9rdCvBrXO2GvO9cMRAnrQgFzCmamNF9tWc6cmstm9E0VT /KHlBGwoX4Qd87RPg2g+jKMDJ77sAKwqL2+wVR+dr96f4uvHzrAhWmhmAcXTCTiBRdZ1 JQJBbE8MpIr6ji3iBi8p42KqMLYHFtygrXAagqYBSbi4P5a6nBnD6zzvpeMhnQp2dAuy WPHQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=krQiwNIU1oFRdpbjQQ+MleaQuhQqE8OwDSXusURqx9Y=; b=Je9ZaivbenolOE6w8ABgQt+6nGMjJaXpP+sPE8tM4QRr4vF5wmWfjGmS9VD3oV7iP2 hjd721ok+o15SaeTGP5OaDuuu9v/enIMGmOJL0ejZSEEzsPM4/XmezZJUziEj2Ji/ItK CMHFBe/P4njhHmpBzQ1Uz+JPo5uYWAPURL4Jkyk6NN+AXsyfzH8UzqQ9CZM4VWMNOG33 q+xiDwa+Ec84Q70kPM7DIGaA3D9JGezw24+ZDPrKDUn/cPw1CJj70vHAoY1A9Pa1ULJF ofWiBEWeYUCmWsnM2WtT0vM1+G3YOI6cfHoTvf1DICdmdqqraHhVyVCGBB0zi7otpz0r DzWA== X-Gm-Message-State: ANoB5plvv02zA79E9r+fg323EWWuK+YhSH9gb6VLCux7WF6LZsuWT9je 1qCdn10j10fGpY0hBaT7DeKeTgYXC6c= X-Google-Smtp-Source: AA0mqf5N0tM4H9nHiMIyzYDHGbwPtDomQY7QeoEp3WC+kPqU5HB8lUqyxzLX0IOMP7k5A4cEkHVzCQ== X-Received: by 2002:a2e:a888:0:b0:277:794:cb84 with SMTP id m8-20020a2ea888000000b002770794cb84mr13023469ljq.7.1669754820922; Tue, 29 Nov 2022 12:47:00 -0800 (PST) Received: from localhost.localdomain (ccy110.neoplus.adsl.tpnet.pl. [83.30.148.110]) by smtp.gmail.com with ESMTPSA id o11-20020ac24e8b000000b004ae24368195sm2325620lfr.233.2022.11.29.12.46.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 12:47:00 -0800 (PST) From: Adam Skladowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Loic Poulain , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 04/12] arm64: dts: qcom: sm6115: Add TSENS node Date: Tue, 29 Nov 2022 21:46:08 +0100 Message-Id: <20221129204616.47006-5-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221129204616.47006-1-a39.skl@gmail.com> References: <20221129204616.47006-1-a39.skl@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add nodes required for TSENS block using the common qcom,tsens-v2 binding. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 2003a2519a54..decbf7ca8a03 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -515,6 +515,17 @@ spmi_bus: spmi@1c40000 { #interrupt-cells = <4>; }; + tsens0: thermal-sensor@4410000 { + compatible = "qcom,sm6115-tsens", "qcom,tsens-v2"; + reg = <0x04411000 0x1ff>, /* TM */ + <0x04410000 0x8>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram"; reg = <0x045f0000 0x7000>; From patchwork Tue Nov 29 20:46:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 629249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8150C4708A for ; Tue, 29 Nov 2022 20:47:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236522AbiK2UrU (ORCPT ); Tue, 29 Nov 2022 15:47:20 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236526AbiK2UrR (ORCPT ); Tue, 29 Nov 2022 15:47:17 -0500 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B24B6A752; Tue, 29 Nov 2022 12:47:11 -0800 (PST) Received: by mail-lj1-x234.google.com with SMTP id h10so1937327ljk.11; Tue, 29 Nov 2022 12:47:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mxN9saAhaHyj6ZPoVgv7tMWvA+bJrGztagX7f0iYRp8=; b=EKOfkRku6K7RAUf9XDjX/bzJEeMBGnJr+YgZZCT2E089whrohH/xepfl97H3rygCBq SSxX2sTPQciwjd83RIArZYSAd1HyGTI5mZ9alPUpHjgIMkgf4GcAr75DnwRyGvxPALWQ m9K2G0MWUvNQ1WhZFDiw2zX8J3pM8cFZlgoVtSOYaV8FMdOUk7VJFpiyy+wnyL8uEyIR QUq2Sw5eBNI1OI6iuLoZZH/MRJTDvWH1rrSfLeDb7tuAV2QNNJoSD4r5KhjHjborxb6e gaALpF8Xne2RnO9LG3uEnssIForFJoZcVATf6Rf3E4ZUDsGq3qZljtU6y2F49Tk1TPMh lzpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mxN9saAhaHyj6ZPoVgv7tMWvA+bJrGztagX7f0iYRp8=; b=MONbwxipWqxQswWXoiOjWZUgJ8lwUUf1RC4sFhW0VYBCU5+pxpj2NtK6qHwvf9/iPC WIS0VNJVogH2yF/ixj+TbqMgr9HE+DLU5068CP2+9R8FZts85+vdP48l/A3Q9G8Q48wa dmn+OavZTpYNgFj2hC2ycQyF5rWTZ3aOF3p6eQSlgeMY0hDaLg/N8N3wI07IcFdQ6/90 12tXhh/vjhZIXXA/beJv15x9Qitszj1PM4nF9l+G7K2t6wQNzsFHunE7OCstkvFu0m33 /owGQiYmSbrmpuS6bnT04A1k0j39GJTd6PbFpeNcZOmjjcJs19XFMUHeLjpJ3u9ywGWU LScw== X-Gm-Message-State: ANoB5pn8IGY5hZlLOadrED5lPpBg5OLPtyHsIKUSn92VVMvQeb/SWRrY NngcIMFrgmbTRjVkiwaWlvE3LUEyhN8= X-Google-Smtp-Source: AA0mqf4Nem329kgRkNkWL4kY5oPzJemV9ZG8Z58VHEC6R2xw4BnxpGydh7FQmoDxjQByrNViKPSraA== X-Received: by 2002:a2e:2c0e:0:b0:279:8d29:193c with SMTP id s14-20020a2e2c0e000000b002798d29193cmr8569437ljs.167.1669754829867; Tue, 29 Nov 2022 12:47:09 -0800 (PST) Received: from localhost.localdomain (ccy110.neoplus.adsl.tpnet.pl. [83.30.148.110]) by smtp.gmail.com with ESMTPSA id o11-20020ac24e8b000000b004ae24368195sm2325620lfr.233.2022.11.29.12.47.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 12:47:09 -0800 (PST) From: Adam Skladowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Loic Poulain , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 08/12] arm64: dts: qcom: sm6115: Add mdss/dpu node Date: Tue, 29 Nov 2022 21:46:12 +0100 Message-Id: <20221129204616.47006-9-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221129204616.47006-1-a39.skl@gmail.com> References: <20221129204616.47006-1-a39.skl@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add mdss and dpu node to enable display support on SM6115. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 183 +++++++++++++++++++++++++++ 1 file changed, 183 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index ea0e0b3c5d84..b459f1746a7f 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -718,6 +718,189 @@ usb_1_dwc3: usb@4e00000 { }; }; + mdss: display-subsystem@5e00000 { + compatible = "qcom,sm6115-mdss"; + reg = <0x05e00000 0x1000>; + reg-names = "mdss"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x420 0x2>, + <&apps_smmu 0x421 0x0>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + mdp: display-controller@5e01000 { + compatible = "qcom,sm6115-dpu"; + reg = <0x05e01000 0x8f000>, + <0x05eb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "iface", + "core", + "lut", + "rot", + "vsync"; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-192000000 { + opp-hz = /bits/ 64 <192000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-256000000 { + opp-hz = /bits/ 64 <256000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-307200000 { + opp-hz = /bits/ 64 <307200000>; + required-opps = <&rpmpd_opp_svs_plus>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + }; + + dsi0: dsi@5e94000 { + compatible = "qcom,dsi-ctrl-6g-qcm2290"; + reg = <0x05e94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmpd SM6115_VDDCX>; + phys = <&dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmpd_opp_min_svs>; + }; + + opp-164000000 { + opp-hz = /bits/ 64 <164000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmpd_opp_svs>; + }; + }; + }; + + dsi0_phy: phy@5e94400 { + compatible = "qcom,dsi-phy-14nm-2290"; + reg = <0x05e94400 0x100>, + <0x05e94500 0x300>, + <0x05e94800 0x188>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + dispcc: clock-controller@5f00000 { compatible = "qcom,sm6115-dispcc"; reg = <0x05f00000 0x20000>; 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[83.30.148.110]) by smtp.gmail.com with ESMTPSA id o11-20020ac24e8b000000b004ae24368195sm2325620lfr.233.2022.11.29.12.47.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 12:47:11 -0800 (PST) From: Adam Skladowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Loic Poulain , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 09/12] arm64: dts: qcom: sm6115: Add GPI DMA Date: Tue, 29 Nov 2022 21:46:13 +0100 Message-Id: <20221129204616.47006-10-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221129204616.47006-1-a39.skl@gmail.com> References: <20221129204616.47006-1-a39.skl@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add GPI DMA node which will be wired to i2c/spi/uart. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index b459f1746a7f..e9de7aa1efdd 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -673,6 +673,26 @@ ufs_mem_phy_lanes: phy@4807400 { }; }; + gpi_dma0: dma-controller@4a00000 { + compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0x04a00000 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0xf>; + iommus = <&apps_smmu 0xf6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + usb_1: usb@4ef8800 { compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; reg = <0x04ef8800 0x400>; From patchwork Tue Nov 29 20:46:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 629248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31416C4708A for ; Tue, 29 Nov 2022 20:47:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236700AbiK2UrY (ORCPT ); Tue, 29 Nov 2022 15:47:24 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236609AbiK2UrS (ORCPT ); Tue, 29 Nov 2022 15:47:18 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48A92264AE; Tue, 29 Nov 2022 12:47:16 -0800 (PST) Received: by mail-lf1-x130.google.com with SMTP id b3so23907052lfv.2; Tue, 29 Nov 2022 12:47:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1Ma9RUQu1JjVVoYty/WmEXDnYuOfQCd9ANuJ3pmUfPM=; b=T/qBBnIruUH/GUG83CcB0NngH2JXSmSIG9cGLShPtFZWw6A4daVJUvP6xwkdgAaFQW MGvObW7ShX2GrYtOjmizAfsy0e0PCGnYrb2D9M3OZ3dGGNnCM4wSQi3G1Adhteesiyvt BWfmhrLjUDB+LLFiRrgcXMksdn2nrX6rwVhuaYUWRubAHBu0FAhONOelr2nAsxzEzVVE xuFF7N/TdqngKU7p5vmUhzd7CEVprhegjCVeT16r9T1HabdsApxZicqPvon1Jxtam2pq PBJkp6LHq5tIzkAdJkq4zq/+nWn4icmNYzOVmrP1F82YW6mYhj8QVYVHRVbgQCdXneLL Wscg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1Ma9RUQu1JjVVoYty/WmEXDnYuOfQCd9ANuJ3pmUfPM=; b=cbHW9YUP9cie7prKr660KopB/qavM2rDobjhB1CQB3VZ7FNO1jpf67XUpyGgElH1Kf 6fsb6zTTLqp+hHfY0Qsdv9f6PI1xC9G9XE2DbOOWZS52VpDYBWB2gdsfOo+ROhrOk56X ak3DEHimwUqA2dJNiSDSaBBOD56/H7xI000eoyC8XRoDcMrovUs6Dom3nnxp/DFgNq/6 IwRq9Tnm5k/1acC1My0rMEuLh18Pu6oO6Z99bp5sbaogPE9gvX0p4zDnP4TibRZksSLh a6kXJGzPIDSBt3sn+sXi/82HjCFHRB52c1fmbaLqiRFBowvOq8pypVvciAGye5JVh0dI cqKA== X-Gm-Message-State: ANoB5plek2aCVgR+f+r5frcK2GcxrhpIXeLeGBF3U5CzLzpDd4ACUzp9 KWuaJWF5Oo2GPCNHmIHSVGcdIQhwos0= X-Google-Smtp-Source: AA0mqf4vieHe53nkDLyouG86tJoxjWakBPNUKhkxYRv0lFIj9pr6eplRQSRLVtOwCbUFwy+SymcKLA== X-Received: by 2002:a19:5211:0:b0:4b5:1e6f:c9d3 with SMTP id m17-20020a195211000000b004b51e6fc9d3mr2074160lfb.659.1669754834500; Tue, 29 Nov 2022 12:47:14 -0800 (PST) Received: from localhost.localdomain (ccy110.neoplus.adsl.tpnet.pl. [83.30.148.110]) by smtp.gmail.com with ESMTPSA id o11-20020ac24e8b000000b004ae24368195sm2325620lfr.233.2022.11.29.12.47.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 12:47:14 -0800 (PST) From: Adam Skladowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Loic Poulain , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 10/12] arm64: dts: qcom: sm6115: Add i2c/spi nodes Date: Tue, 29 Nov 2022 21:46:14 +0100 Message-Id: <20221129204616.47006-11-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221129204616.47006-1-a39.skl@gmail.com> References: <20221129204616.47006-1-a39.skl@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add I2C/SPI nodes for SM6115. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 287 +++++++++++++++++++++++++++ 1 file changed, 287 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index e9de7aa1efdd..d14a4595be8a 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -357,6 +358,90 @@ tlmm: pinctrl@500000 { interrupt-controller; #interrupt-cells = <2>; + qup_i2c0_default: qup-i2c0-default { + pins = "gpio0", "gpio1"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default { + pins = "gpio4", "gpio5"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default { + pins = "gpio6", "gpio7"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_default: qup-i2c3-default { + pins = "gpio8", "gpio9"; + function = "qup3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_default: qup-i2c4-default { + pins = "gpio12", "gpio13"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_default: qup-i2c5-default { + pins = "gpio14", "gpio15"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default { + pins = "gpio0", "gpio1","gpio2", "gpio3"; + function = "qup0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi1_default: qup-spi1-default { + pins = "gpio4", "gpio5", "gpio69", "gpio70"; + function = "qup1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi2_default: qup-spi2-default { + pins = "gpio6", "gpio7", "gpio71", "gpio80"; + function = "qup2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi3_default: qup-spi3-default { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "qup3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi4_default: qup-spi4-default { + pins = "gpio12", "gpio13", "gpio96", "gpio97"; + function = "qup4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi5_default: qup-spi5-default { + pins = "gpio14", "gpio15", "gpio16", "gpio17"; + function = "qup5"; + drive-strength = <2>; + bias-pull-up; + }; + sdc1_state_on: sdc1-on-state { clk-pins { pins = "sdc1_clk"; @@ -693,6 +778,208 @@ gpi_dma0: dma-controller@4a00000 { status = "disabled"; }; + qupv3_id_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x04ac0000 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <1>; + #size-cells = <1>; + iommus = <&apps_smmu 0xe3 0x0>; + ranges; + status = "disabled"; + + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a80000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + interrupts = ; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x04a80000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a84000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_default>; + interrupts = ; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@4a84000 { + compatible = "qcom,geni-spi"; + reg = <0x04a84000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_default>; + interrupts = ; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a88000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + interrupts = ; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x04a88000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi2_default>; + interrupts = ; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@4a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a8c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c3_default>; + interrupts = ; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@4a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x04a8c000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi3_default>; + interrupts = ; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@4a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a90000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_default>; + interrupts = ; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@4a90000 { + compatible = "qcom,geni-spi"; + reg = <0x04a90000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_default>; + interrupts = ; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@4a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x04a94000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_default>; + interrupts = ; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@4a94000 { + compatible = "qcom,geni-spi"; + reg = <0x04a94000 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi5_default>; + interrupts = ; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + usb_1: usb@4ef8800 { compatible = "qcom,sm6115-dwc3", "qcom,dwc3"; reg = <0x04ef8800 0x400>; From patchwork Tue Nov 29 20:46:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Skladowski X-Patchwork-Id: 629247 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D879C4332F for ; Tue, 29 Nov 2022 20:47:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236757AbiK2Urn (ORCPT ); Tue, 29 Nov 2022 15:47:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46622 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236480AbiK2UrX (ORCPT ); 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[83.30.148.110]) by smtp.gmail.com with ESMTPSA id o11-20020ac24e8b000000b004ae24368195sm2325620lfr.233.2022.11.29.12.47.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Nov 2022 12:47:18 -0800 (PST) From: Adam Skladowski Cc: phone-devel@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Adam Skladowski , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Andy Gross , Bjorn Andersson , Konrad Dybcio , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Loic Poulain , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: [PATCH 12/12] arm64: dts: qcom: sm6115: Fallback smmu to qcom generic compatible Date: Tue, 29 Nov 2022 21:46:16 +0100 Message-Id: <20221129204616.47006-13-a39.skl@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221129204616.47006-1-a39.skl@gmail.com> References: <20221129204616.47006-1-a39.skl@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Change fallback to qcom generic compatible in order to prevent reboot during SMMU initialization. Signed-off-by: Adam Skladowski --- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 36d1cff23d10..b00d74055eb1 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1222,7 +1222,7 @@ dispcc: clock-controller@5f00000 { }; apps_smmu: iommu@c600000 { - compatible = "qcom,sm6115-smmu-500", "arm,mmu-500"; + compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0c600000 0x80000>; #iommu-cells = <2>; #global-interrupts = <1>;