From patchwork Mon Nov 28 02:44:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 629134 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D83EC43217 for ; Mon, 28 Nov 2022 02:44:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229568AbiK1Cot (ORCPT ); Sun, 27 Nov 2022 21:44:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229509AbiK1Cos (ORCPT ); Sun, 27 Nov 2022 21:44:48 -0500 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F263A18D for ; Sun, 27 Nov 2022 18:44:45 -0800 (PST) Received: by mail-pg1-x533.google.com with SMTP id w37so3598149pga.5 for ; Sun, 27 Nov 2022 18:44:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Tv1e03FO2qF987UL3rYSZkGVDWpL3dr4bIgnamkaz8k=; b=OGNey52SwCPracCX9H9kykEMys7l+KWvUGpL45jpXgrjzIMiOCLtOs2NlKRZFxwS0C EwEOSeJRFOuZo0aIvt+Q8iefpRR3NrjVq4g6xLvbizsPI2NFs8WOoPBJPo+K5lPLHJLi NxhK+QJMgGijfkqWN3iHxc1CEQNMLAFYXzrtI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tv1e03FO2qF987UL3rYSZkGVDWpL3dr4bIgnamkaz8k=; b=I3hEbGSVYm4gwyzgzLxpKj9U+GLng5wJ+9iwnXSSKr4GUQLYXTCHAxcVe7CQIOHqo0 Um0np7ykbx4nnFKyRR4k0My/LmEqqvUNpd+91QBcmzftQhQyDaZYYTDoZmCRvtr6MolE gr50CDsQJmYUMWi+eCDKpq+nNPTtqyRfSFn2dDp/89J/CdNoK3a3ZFDHIHs3Yehp9yiY x/CsxRSZzLSU3Em8AgVqLuNoIwYUoDjfXKCar1S988pv2pMW7isYXJIRBH6/er9eVdnU WYNrlM4evDdlieAiQ2/xNEqVTDQO0rRG0L9IAH5TjPucB3lSEGPaXXaBfO2Km8+oe8zp e/uQ== X-Gm-Message-State: ANoB5pmShfYGlYitvi06ycWsFx2swuA/LwqhnDqGSWoHAzmAt0/qv34P byq2pKs9KEQEpT5fsgUM+JQBSA== X-Google-Smtp-Source: AA0mqf5/n6iwg6NmZl3VghZbs771G+jDVX2jWINfcJkDxvuGlcchDWA4SndnsAopjkv5zHMHMBFdkA== X-Received: by 2002:aa7:8d8f:0:b0:56b:b112:4a16 with SMTP id i15-20020aa78d8f000000b0056bb1124a16mr52473821pfr.66.1669603484351; Sun, 27 Nov 2022 18:44:44 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id z16-20020aa79910000000b005752201d4ffsm1431568pff.213.2022.11.27.18.44.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 18:44:43 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH 1/8] mmc: sdhci-pxav2: add initial support for PXA168 V1 controller Date: Sun, 27 Nov 2022 18:44:00 -0800 Message-Id: <20221128024407.224393-2-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128024407.224393-1-doug@schmorgal.com> References: <20221128024407.224393-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add a new compatible string for the version 1 controller used in the PXA168, along with necessary quirks. Use a separate ops struct in preparation for a silicon bug workaround only necessary on V1. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index f18906b5575f..2f9fa0ecbddd 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -101,6 +101,14 @@ static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width) writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL); } +static const struct sdhci_ops pxav1_sdhci_ops = { + .set_clock = sdhci_set_clock, + .get_max_clock = sdhci_pltfm_clk_get_max_clock, + .set_bus_width = pxav2_mmc_set_bus_width, + .reset = pxav2_reset, + .set_uhs_signaling = sdhci_set_uhs_signaling, +}; + static const struct sdhci_ops pxav2_sdhci_ops = { .set_clock = sdhci_set_clock, .get_max_clock = sdhci_pltfm_clk_get_max_clock, @@ -114,6 +122,9 @@ static const struct of_device_id sdhci_pxav2_of_match[] = { { .compatible = "mrvl,pxav2-mmc", }, + { + .compatible = "mrvl,pxav1-mmc", + }, {}, }; MODULE_DEVICE_TABLE(of, sdhci_pxav2_of_match); @@ -208,7 +219,12 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) host->mmc->pm_caps |= pdata->pm_caps; } - host->ops = &pxav2_sdhci_ops; + if (match && of_device_is_compatible(dev->of_node, "mrvl,pxav1-mmc")) { + host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ | SDHCI_QUIRK_32BIT_DMA_SIZE; + host->ops = &pxav1_sdhci_ops; + } else { + host->ops = &pxav2_sdhci_ops; + } ret = sdhci_add_host(host); if (ret) From patchwork Mon Nov 28 02:44:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 629133 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1B06C43217 for ; Mon, 28 Nov 2022 02:44:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229509AbiK1Coy (ORCPT ); Sun, 27 Nov 2022 21:44:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229619AbiK1Cow (ORCPT ); Sun, 27 Nov 2022 21:44:52 -0500 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A0F42DF4 for ; Sun, 27 Nov 2022 18:44:48 -0800 (PST) Received: by mail-pf1-x42c.google.com with SMTP id a16so8738832pfg.4 for ; Sun, 27 Nov 2022 18:44:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=10C9l5cM9Gx+6A1r6iqoMzAy/dFS6z3guP1T2Uf7DqQ=; b=TzBcy4nze14e3VK8qk9Vn+oKWTOVmmiAYi2YP/56bEjInTRbOpIeA41cLwD8pzVUk4 KzCdnA5yXc9RPsiHm7U4CSy5JdPHs7nWwd39kH2HaT2ShTAKLT5+bTT/B23Lo7189Vm2 T2hf2Tfmwi9NVzj2Kvn9Z71RyvTWOu+MH29MU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=10C9l5cM9Gx+6A1r6iqoMzAy/dFS6z3guP1T2Uf7DqQ=; b=UqkrtC4TBHkZp8BktE3urDI6n2mlsv9T5XnGyyw/D/R4wW6TdsxIypmTWRJWq1kudV CT3Bw1iP6k7peC79alPGdJXqPxmIci4kZrpCWnD9SSQeX37iqVCsEuOrWNWptfCshFN4 l6s1eQ9fmF4cpWDhRa4a+3JXKCZfJw9e4Syyh9qdiXL1P0qLHRFDyZnm5FM1b8Srj09b hUPA+4aFem6Z1mO4MjOhWx/MtDkUWGP1OmOLtLcGkVHaBq2VJNJMIU+QAVsgK+Kquw+7 SKOv15U5KKlKoKIiMP/DxSO95LoW7gXWW7eaEuYEcpCJ+p9HxNkiGecAB75daZSaeYeA fb8g== X-Gm-Message-State: ANoB5pmm79I5DaYc5fj6CU/RgsZ1+Go3kE7UEcn4tB1cK8MgcS+A632+ SfcLDN+IVM+mLCGlwT5cscGImw== X-Google-Smtp-Source: AA0mqf4wEG3Y0VAbLcuqmet6VRWOB3QCpK1YuSNDfiUOVFN9yKT3gYncIWlBfV5R0ycdyechcMpwzQ== X-Received: by 2002:a63:f253:0:b0:434:afab:5ff9 with SMTP id d19-20020a63f253000000b00434afab5ff9mr24630939pgk.349.1669603487556; Sun, 27 Nov 2022 18:44:47 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id z16-20020aa79910000000b005752201d4ffsm1431568pff.213.2022.11.27.18.44.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 18:44:47 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH 2/8] mmc: sdhci-pxav2: enable CONFIG_MMC_SDHCI_IO_ACCESSORS Date: Sun, 27 Nov 2022 18:44:01 -0800 Message-Id: <20221128024407.224393-3-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128024407.224393-1-doug@schmorgal.com> References: <20221128024407.224393-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Enable CONFIG_MMC_SDHCI_IO_ACCESSORS for the pxav2 driver. The read_w callback is needed for a silicon bug workaround in the PXA168. Signed-off-by: Doug Brown --- drivers/mmc/host/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 5e19a961c34d..b9e9185c86a6 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -360,6 +360,7 @@ config MMC_SDHCI_PXAV2 depends on MMC_SDHCI_PLTFM depends on ARCH_MMP || COMPILE_TEST default CPU_PXA910 + select MMC_SDHCI_IO_ACCESSORS help This selects the Marvell(R) PXAV2 SD Host Controller. If you have a PXA9XX platform with SD Host Controller From patchwork Mon Nov 28 02:44:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 630546 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7FB4BC43217 for ; Mon, 28 Nov 2022 02:44:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229534AbiK1Cov (ORCPT ); Sun, 27 Nov 2022 21:44:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45142 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229509AbiK1Cov (ORCPT ); Sun, 27 Nov 2022 21:44:51 -0500 Received: from mail-pj1-x102d.google.com (mail-pj1-x102d.google.com [IPv6:2607:f8b0:4864:20::102d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 791CA11478 for ; Sun, 27 Nov 2022 18:44:50 -0800 (PST) Received: by mail-pj1-x102d.google.com with SMTP id t11-20020a17090a024b00b0021932afece4so1696050pje.5 for ; Sun, 27 Nov 2022 18:44:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h52LC2fcwXDHkqty7e4d/orwaU1LTOLaC2O9W0blfKw=; b=dUil7Im7K9hDFEl6/RqJQ3C1or9z9wnS+K+BCw8nkXpcE7Rz5toyfAsfBGwJTAxbbz dhrVb2nyvwnatHp/t1Xd9kgtKVZkHOhImPyo2l5lA38sO0S2+AG1UduIbKxTdk/u6gzh ps7eAoOz4t4A9lTyFQ1jrnVWF2Bkl2RAo4/Yo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h52LC2fcwXDHkqty7e4d/orwaU1LTOLaC2O9W0blfKw=; b=N1DsUw7g+uIYdCRSJgz1Hb0ef/fBeg/lmAYFLFHJGPHbh3y/WDO5F8lf4IRvlP2rMM H5WVq1iRwcb9rt3IfSgFYe45CKAixBNSm0pYR+BW03uyQDlFlpzxGk8QHuNXXnwbZBoM N8g6ZR4KYle0IRn0yyZgBGz7qE6prYjoLoLHYk6nGHjkV1m5xoovYCKbkS45INk8L+aZ vp4ZaVqjCW3bMyzNVlfNJcQ1YwD2XtwyQWbbA9BEZG0F+gYkR8RF+TG6xlKZylsQh6XL 0xB7ExfbELpz5lTbVCzGjuRoxp/cziQ3GGPBhi6eFtPq+JfbRW9hsnlG9sejEVHlg4lp Hfnw== X-Gm-Message-State: ANoB5pl2dsMCTip9w+80+UfsKdSBT6bzmcWQd7LuVeUhwNFgfH1WKzHJ 1lF1ksmCrFVHGr2fFNv8CIJ6SA== X-Google-Smtp-Source: AA0mqf6jSTk+LA+IeG/Mo4dhpMkPCsh+cCqAcVq9KbtzplY2gFQRos89PHoCPbLa+dhO6dckTa0kgg== X-Received: by 2002:a17:90a:7003:b0:212:f169:140e with SMTP id f3-20020a17090a700300b00212f169140emr50593366pjk.215.1669603489882; Sun, 27 Nov 2022 18:44:49 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id z16-20020aa79910000000b005752201d4ffsm1431568pff.213.2022.11.27.18.44.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 18:44:49 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH 3/8] mmc: sdhci-pxav2: add register workaround for PXA168 silicon bug Date: Sun, 27 Nov 2022 18:44:02 -0800 Message-Id: <20221128024407.224393-4-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128024407.224393-1-doug@schmorgal.com> References: <20221128024407.224393-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The PXA168 has a documented silicon bug that results in a data abort exception when accessing the SDHCI_HOST_VERSION register on SDH2 and SDH4 through a 16-bit read. Implement the workaround described in the errata, which performs a 32-bit read from a lower address instead. This is safe to use on all four SDH peripherals. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index 2f9fa0ecbddd..d76131b8986b 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -80,6 +80,18 @@ static void pxav2_reset(struct sdhci_host *host, u8 mask) } } +static inline u16 pxav1_readw(struct sdhci_host *host, int reg) +{ + u32 temp; + /* Workaround for data abort exception on SDH2 and SDH4 on PXA168 */ + if (reg == SDHCI_HOST_VERSION) { + temp = readl(host->ioaddr + SDHCI_HOST_VERSION - 2) >> 16; + return temp & 0xffff; + } + + return readw(host->ioaddr + reg); +} + static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width) { u8 ctrl; @@ -102,6 +114,7 @@ static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width) } static const struct sdhci_ops pxav1_sdhci_ops = { + .read_w = pxav1_readw, .set_clock = sdhci_set_clock, .get_max_clock = sdhci_pltfm_clk_get_max_clock, .set_bus_width = pxav2_mmc_set_bus_width, From patchwork Mon Nov 28 02:44:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 630545 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EAD4C47089 for ; Mon, 28 Nov 2022 02:44:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229646AbiK1Coz (ORCPT ); Sun, 27 Nov 2022 21:44:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45186 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229601AbiK1Coy (ORCPT ); Sun, 27 Nov 2022 21:44:54 -0500 Received: from mail-pf1-x429.google.com (mail-pf1-x429.google.com [IPv6:2607:f8b0:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8B1D634D for ; Sun, 27 Nov 2022 18:44:52 -0800 (PST) Received: by mail-pf1-x429.google.com with SMTP id o1so4609561pfp.12 for ; Sun, 27 Nov 2022 18:44:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Kwkzsxls5ZWblSq857VINffaoA+3YsLSkG7RdKigW24=; b=E65i522lAPGxtB0Jjp9iAOdnEHGT70IwSQZ8r+AQKPbRARFTOp9riib2vgA6OXFuQd hYSuUZZS0BbKykDE8MKRhMr8DDBd6zPUH5j0t+XrRufd4eaJsskG2WuZARBn7UA8zUhu 4Xq9zVqu25ATDLJw3Ge2WkCK9I/4PsDzvEoY0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Kwkzsxls5ZWblSq857VINffaoA+3YsLSkG7RdKigW24=; b=UXmWDc5tK26hT4Q+c67Kcl60biZL/UWYXh0TXK03/XGIMzPMCdnBnBuXVgVoXPACRZ LnCImqOMUmnM2Z5xEHMlchoiUF0OE9/DCVBZy25CzLTsWif0SxkDBTJQJwxKG230iUVD GgZXGY/SEXUvPYWO+QcVacF6siMqc96dAfUDhjEy5PhlxNoxY0BjRmoA9vW8aJA7oTJZ GsJlU/8UNttRir252qVmCrxuwlPy3irM1LLxMyWOghZK57D3gGTosq049PdMMS55BRj/ Up+X59R7W0FcG+ouOdxJbcd+4H8KW14rrLPXRvuqfTrsmJsKv7ZNK81FQf35r4ljDIbo jc3g== X-Gm-Message-State: ANoB5pnaSqGDZEPIR6wF498HaDiOkM1YEqGot96ZSDsDhiDcUDv32fOV 5WO4NETynX+4BPWfeWEOnpLNtA== X-Google-Smtp-Source: AA0mqf4BeNiJxg1a+9CVbsFBMOpOCIpJF+fUVWmNi6djSdwWpDpvsDlucTpIcmcm078pnnI0z3hvgQ== X-Received: by 2002:a05:6a00:26c8:b0:574:c159:ce3b with SMTP id p8-20020a056a0026c800b00574c159ce3bmr13624667pfw.74.1669603492220; Sun, 27 Nov 2022 18:44:52 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id z16-20020aa79910000000b005752201d4ffsm1431568pff.213.2022.11.27.18.44.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 18:44:51 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH 4/8] mmc: sdhci-pxav2: change clock name to match DT bindings Date: Sun, 27 Nov 2022 18:44:03 -0800 Message-Id: <20221128024407.224393-5-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128024407.224393-1-doug@schmorgal.com> References: <20221128024407.224393-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The devicetree bindings for this driver specify that the two allowed clock names are io and core. Change this driver to look for io, but allow any name if it fails for backwards compatibility. Follow the same pattern used in sdhci-pxav3. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index d76131b8986b..a0c882d03d0b 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -192,7 +192,9 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) pltfm_host = sdhci_priv(host); - clk = devm_clk_get(dev, "PXA-SDHCLK"); + clk = devm_clk_get(dev, "io"); + if (IS_ERR(clk)) + clk = devm_clk_get(dev, NULL); if (IS_ERR(clk)) { dev_err(dev, "failed to get io clock\n"); ret = PTR_ERR(clk); From patchwork Mon Nov 28 02:44:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 629132 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52833C433FE for ; Mon, 28 Nov 2022 02:45:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229723AbiK1CpD (ORCPT ); Sun, 27 Nov 2022 21:45:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229683AbiK1Co5 (ORCPT ); Sun, 27 Nov 2022 21:44:57 -0500 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E45011478 for ; Sun, 27 Nov 2022 18:44:55 -0800 (PST) Received: by mail-pl1-x62b.google.com with SMTP id p24so5126723plw.1 for ; Sun, 27 Nov 2022 18:44:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rmieg4CE/yoWW/WbGieBOpB3jed5cPBDcr27QQC3wwY=; b=j08gU2WeURSZo53HKsrDD3F+UwpgZCpHsM0JNBKzw2rqwUKSx2cgEbWfpcscSPe0cI x7psbdN4gH4vVgsbQ5cOxtUM/x+MA/loIOmD0qwgid2RrfzeRCfDj2MaziblPJx3dSpK FSj+ULhc6NlDCmpju0lwOFO1wU6wGjeuxTWQM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rmieg4CE/yoWW/WbGieBOpB3jed5cPBDcr27QQC3wwY=; b=C8HpltjipYXSqXXRDwTnd6UmfZrO2obEE+z35lir7mTUtV6FnMuRPHCT7pOnHp/qjb u0LVvIgl9W4fkXU2i/G4+al/riqZ8g1J1JTpliWP007aEmOi0Wv/L40L3fm4wS3YQWfx R4b+TsZtNcq3+PvmZYkrtqBkctpwDl3foCJSsmusrjTiJCdUqsSYa2jLKQA9J5dkCrAG fwyZ4Cn1LJBbww/+wG+AYu9jq/yLOj9uCfxKrtl7N9M3l1Yv57Rcc5cyr3kh9ZdyXIfo NuxObyn6u8Tz0sC8l23aMp31O5SIJzbYS9jXMnQJZfisQE46q8Wk9nPWAgggaNkqiae0 RmBw== X-Gm-Message-State: ANoB5pnjOgg4G6zRzVBxpR5im92mmqPOTiizfB45J3uWVf5GEcG4Di29 L+ER5YtYzd2WClHU8uyHMEQEvw== X-Google-Smtp-Source: AA0mqf7LHYFLOyGdWhwGPyihDaFmJjsXwiN/hxawjLBy+DITiSop8QdyRAdyrn9GBIk3a1Zw+Dk25w== X-Received: by 2002:a17:90a:8a07:b0:20a:c032:da66 with SMTP id w7-20020a17090a8a0700b0020ac032da66mr56668781pjn.19.1669603494767; Sun, 27 Nov 2022 18:44:54 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id z16-20020aa79910000000b005752201d4ffsm1431568pff.213.2022.11.27.18.44.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 18:44:54 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH 5/8] mmc: sdhci-pxav2: add optional core clock Date: Sun, 27 Nov 2022 18:44:04 -0800 Message-Id: <20221128024407.224393-6-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128024407.224393-1-doug@schmorgal.com> References: <20221128024407.224393-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add ability to have an optional core clock just like the pxav3 driver. The PXA168 needs this because its SDHC controllers have separate core and io clocks that both need to be enabled. This also correctly matches the documented devicetree bindings for this driver. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 40 ++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index a0c882d03d0b..4996d72c6d23 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -41,6 +41,10 @@ #define MMC_CARD 0x1000 #define MMC_WIDTH 0x0100 +struct sdhci_pxav2_host { + struct clk *clk_core; +}; + static void pxav2_reset(struct sdhci_host *host, u8 mask) { struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); @@ -179,6 +183,7 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) { struct sdhci_pltfm_host *pltfm_host; struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; + struct sdhci_pxav2_host *pxav2_host; struct device *dev = &pdev->dev; struct sdhci_host *host = NULL; const struct of_device_id *match; @@ -186,11 +191,12 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) int ret; struct clk *clk; - host = sdhci_pltfm_init(pdev, NULL, 0); + host = sdhci_pltfm_init(pdev, NULL, sizeof(*pxav2_host)); if (IS_ERR(host)) return PTR_ERR(host); pltfm_host = sdhci_priv(host); + pxav2_host = sdhci_pltfm_priv(pltfm_host); clk = devm_clk_get(dev, "io"); if (IS_ERR(clk)) @@ -207,6 +213,15 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) goto free; } + pxav2_host->clk_core = devm_clk_get(dev, "core"); + if (!IS_ERR(pxav2_host->clk_core)) { + ret = clk_prepare_enable(pxav2_host->clk_core); + if (ret) { + dev_err(&pdev->dev, "failed to enable core clock\n"); + goto disable_io_clk; + } + } + host->quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN; @@ -243,17 +258,34 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) ret = sdhci_add_host(host); if (ret) - goto disable_clk; + goto disable_core_clk; return 0; -disable_clk: +disable_core_clk: + if (!IS_ERR(pxav2_host->clk_core)) + clk_disable_unprepare(pxav2_host->clk_core); +disable_io_clk: clk_disable_unprepare(clk); free: sdhci_pltfm_free(pdev); return ret; } +static int sdhci_pxav2_remove(struct platform_device *pdev) +{ + struct sdhci_host *host = platform_get_drvdata(pdev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_pxav2_host *pxav2_host = sdhci_pltfm_priv(pltfm_host); + + int ret = sdhci_pltfm_unregister(pdev); + + if (!IS_ERR(pxav2_host->clk_core)) + clk_disable_unprepare(pxav2_host->clk_core); + + return ret; +} + static struct platform_driver sdhci_pxav2_driver = { .driver = { .name = "sdhci-pxav2", @@ -262,7 +294,7 @@ static struct platform_driver sdhci_pxav2_driver = { .pm = &sdhci_pltfm_pmops, }, .probe = sdhci_pxav2_probe, - .remove = sdhci_pltfm_unregister, + .remove = sdhci_pxav2_remove, }; module_platform_driver(sdhci_pxav2_driver); From patchwork Mon Nov 28 02:44:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 630544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D378FC46467 for ; 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([192.183.212.197]) by smtp.gmail.com with ESMTPSA id z16-20020aa79910000000b005752201d4ffsm1431568pff.213.2022.11.27.18.44.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 18:44:57 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH 6/8] mmc: sdhci-pxav2: add SDIO card IRQ workaround for PXA168 V1 controller Date: Sun, 27 Nov 2022 18:44:05 -0800 Message-Id: <20221128024407.224393-7-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128024407.224393-1-doug@schmorgal.com> References: <20221128024407.224393-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The PXA168 has a documented silicon bug that causes SDIO card IRQs to be missed. Implement the first half of the suggested workaround, which involves resetting the data port logic and issuing a dummy CMD0 to restart the clock. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 36 ++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index 4996d72c6d23..0b9b2e4b2153 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -20,6 +20,8 @@ #include #include #include +#include +#include #include "sdhci.h" #include "sdhci-pltfm.h" @@ -43,6 +45,7 @@ struct sdhci_pxav2_host { struct clk *clk_core; + void (*orig_post_req)(struct mmc_host *mmc, struct mmc_request *mrq, int err); }; static void pxav2_reset(struct sdhci_host *host, u8 mask) @@ -96,6 +99,37 @@ static inline u16 pxav1_readw(struct sdhci_host *host, int reg) return readw(host->ioaddr + reg); } +static void pxav1_post_req(struct mmc_host *mmc, struct mmc_request *mrq, int err) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_pxav2_host *pxav2_host; + struct mmc_command dummy_cmd = {}; + u16 tmp; + + /* If this is an SDIO command, perform errata workaround for silicon bug. */ + if (!err && mrq->cmd && !mrq->cmd->error && + (mrq->cmd->opcode == SD_IO_RW_DIRECT || + mrq->cmd->opcode == SD_IO_RW_EXTENDED)) { + /* Reset data port */ + tmp = readw(host->ioaddr + SDHCI_TIMEOUT_CONTROL); + tmp |= 0x400; + writew(tmp, host->ioaddr + SDHCI_TIMEOUT_CONTROL); + + /* Clock is now stopped, so restart it by sending a dummy CMD0. */ + pxav2_host = sdhci_pltfm_priv(sdhci_priv(host)); + + dummy_cmd.opcode = MMC_GO_IDLE_STATE; + dummy_cmd.arg = 0; + dummy_cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_NONE | MMC_CMD_BC; + + mmc_wait_for_cmd(host->mmc, &dummy_cmd, 0); + } + + /* Pass onto SDHCI host driver now */ + if (pxav2_host->orig_post_req) + pxav2_host->orig_post_req(mmc, mrq, err); +} + static void pxav2_mmc_set_bus_width(struct sdhci_host *host, int width) { u8 ctrl; @@ -252,6 +286,8 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) if (match && of_device_is_compatible(dev->of_node, "mrvl,pxav1-mmc")) { host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ | SDHCI_QUIRK_32BIT_DMA_SIZE; host->ops = &pxav1_sdhci_ops; + pxav2_host->orig_post_req = host->mmc_host_ops.post_req; + host->mmc_host_ops.post_req = pxav1_post_req; } else { host->ops = &pxav2_sdhci_ops; } From patchwork Mon Nov 28 02:44:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 629131 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF233C47089 for ; Mon, 28 Nov 2022 02:45:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229652AbiK1CpG (ORCPT ); Sun, 27 Nov 2022 21:45:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45226 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229722AbiK1CpD (ORCPT ); Sun, 27 Nov 2022 21:45:03 -0500 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6885011464 for ; Sun, 27 Nov 2022 18:45:00 -0800 (PST) Received: by mail-pf1-x42c.google.com with SMTP id z17so4348396pff.1 for ; Sun, 27 Nov 2022 18:45:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pIe89DUhig3QJVCJKZqXjKN+60deyyb1lybzcqxylE0=; b=U7EKtrv//D6dBt4f9FyQFCVaQ2qVEWb3fRejkrh6QboNccNgXNyA6OgPzJOHhDQPeK j+XzVoIkBGH1XiRxUK17OoVAZ4nYtvpz5bTED60PKfwYvJpAEhdtjuFZjZD84+dZAqOx QvI0shx4i7bZ/AhQOkF2H/PD/Ooepo5WKxuzo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pIe89DUhig3QJVCJKZqXjKN+60deyyb1lybzcqxylE0=; b=RFPbdcxSVrz0zRJi96vA19WDIr/eVZsDD7ldAKizd4KmTshZ8PD3GCqABwoa6oltMO OfJIfG6WJlGbCj9S7EOJqRCi0e4J+CvZDxzvRnu9GFFBdqoczhw0mgX8ve+caS/jjsm0 AhxIv+qikMsFCDA1p5bl2P8/90bf8c8tsqXc0gEpvvdSsAdn5A7cqHGq3I3993czwTnM ZSpOkAV4nXq76o53mRHWwR3+Uj7t/Tg+Ruu6Lb/1oV+r99i8xSomfWGcMAPvNBWxEV0d 79kJqxnEHoMOXoecKN+84m8uy/KUpZhw3oCfW6p4+IDHyh8eMCQ6A8JAsj4a2tlcfQQz r5rw== X-Gm-Message-State: ANoB5pnvmA2pR4aSZca/MkQ3wY+dEAND67EluCd0HjbOeM/U5H4619OI F8P9FLZHiQMLyJMQXA+8ee8thQ== X-Google-Smtp-Source: AA0mqf4ZSbm165/6Kx52NdTkA9yUuTOPiKUp9ho6phMuoMGFoyT/bQaB95CDSWf4/mJz6m2t9rI2jg== X-Received: by 2002:a63:a0b:0:b0:46f:53cb:65b5 with SMTP id 11-20020a630a0b000000b0046f53cb65b5mr24726610pgk.507.1669603499800; Sun, 27 Nov 2022 18:44:59 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id z16-20020aa79910000000b005752201d4ffsm1431568pff.213.2022.11.27.18.44.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 18:44:59 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH 7/8] mmc: sdhci-pxav2: add optional pinctrl for SDIO IRQ workaround Date: Sun, 27 Nov 2022 18:44:06 -0800 Message-Id: <20221128024407.224393-8-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128024407.224393-1-doug@schmorgal.com> References: <20221128024407.224393-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org The PXA168 errata recommends that the CMD signal should be detached from the SD bus while performing the dummy CMD0 to restart the clock. Implement this using pinctrl states. Signed-off-by: Doug Brown --- drivers/mmc/host/sdhci-pxav2.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c index 0b9b2e4b2153..6b30f70675e2 100644 --- a/drivers/mmc/host/sdhci-pxav2.c +++ b/drivers/mmc/host/sdhci-pxav2.c @@ -22,6 +22,7 @@ #include #include #include +#include #include "sdhci.h" #include "sdhci-pltfm.h" @@ -46,6 +47,9 @@ struct sdhci_pxav2_host { struct clk *clk_core; void (*orig_post_req)(struct mmc_host *mmc, struct mmc_request *mrq, int err); + struct pinctrl *pinctrl; + struct pinctrl_state *pins_default; + struct pinctrl_state *pins_cmd_gpio; }; static void pxav2_reset(struct sdhci_host *host, u8 mask) @@ -118,11 +122,19 @@ static void pxav1_post_req(struct mmc_host *mmc, struct mmc_request *mrq, int er /* Clock is now stopped, so restart it by sending a dummy CMD0. */ pxav2_host = sdhci_pltfm_priv(sdhci_priv(host)); + /* Set CMD as high output rather than MMC function while we do CMD0 */ + if (pxav2_host->pinctrl && pxav2_host->pins_cmd_gpio) + pinctrl_select_state(pxav2_host->pinctrl, pxav2_host->pins_cmd_gpio); + dummy_cmd.opcode = MMC_GO_IDLE_STATE; dummy_cmd.arg = 0; dummy_cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_NONE | MMC_CMD_BC; mmc_wait_for_cmd(host->mmc, &dummy_cmd, 0); + + /* Set as MMC function after dummy command is complete */ + if (pxav2_host->pinctrl && pxav2_host->pins_default) + pinctrl_select_state(pxav2_host->pinctrl, pxav2_host->pins_default); } /* Pass onto SDHCI host driver now */ @@ -288,6 +300,21 @@ static int sdhci_pxav2_probe(struct platform_device *pdev) host->ops = &pxav1_sdhci_ops; pxav2_host->orig_post_req = host->mmc_host_ops.post_req; host->mmc_host_ops.post_req = pxav1_post_req; + + /* Set up optional pinctrl for PXA168 SDIO IRQ fix */ + pxav2_host->pinctrl = devm_pinctrl_get(&pdev->dev); + if (!IS_ERR(pxav2_host->pinctrl)) { + pxav2_host->pins_cmd_gpio = pinctrl_lookup_state(pxav2_host->pinctrl, + "state_cmd_gpio"); + if (IS_ERR(pxav2_host->pins_cmd_gpio)) + pxav2_host->pins_cmd_gpio = NULL; + pxav2_host->pins_default = pinctrl_lookup_state(pxav2_host->pinctrl, + "default"); + if (IS_ERR(pxav2_host->pins_default)) + pxav2_host->pins_default = NULL; + } else { + pxav2_host->pinctrl = NULL; + } } else { host->ops = &pxav2_sdhci_ops; } From patchwork Mon Nov 28 02:44:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Brown X-Patchwork-Id: 630543 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E43FEC4708A for ; Mon, 28 Nov 2022 02:45:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229674AbiK1CpH (ORCPT ); Sun, 27 Nov 2022 21:45:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229737AbiK1CpE (ORCPT ); Sun, 27 Nov 2022 21:45:04 -0500 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E8DC11466 for ; Sun, 27 Nov 2022 18:45:03 -0800 (PST) Received: by mail-pg1-x52d.google.com with SMTP id h193so8722241pgc.10 for ; Sun, 27 Nov 2022 18:45:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=schmorgal.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QblcRigJwoZRgJNZ6iEUB9TwI9CjJLNnmBpOtD0NOv4=; b=X3sSZ+vFG6pKcKMZiHZGfHhEOFIOeF/8wlewh8ih5nKEHqeWHGRbNzi7PT3jvF2Zep gL4Yqon1S38u2PIODz45DeUfheiQLdKs5WcMngFJHGdY9DH+fNXqB0G5r76thAU0cuN8 lVtRjMTVe7nPolWSbVdIATDJx0CrgN4ovsMHk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QblcRigJwoZRgJNZ6iEUB9TwI9CjJLNnmBpOtD0NOv4=; b=lHP50i8+XK7AxY5cv1+HpPNbSYwq683cDJkMpXdzK3eU+6ceA2F62EfMvIbPZ3wGpe jUQBUX5EA2USv9ArEwGYUTRtmSqpDdUMwj50NkPpZ3QuqWlze5HukPHBhKkfhNOZwhEC HeDlhrxmQVkbsckJVEQlQF/gPk7gCkdl4vPRDdu18JkSkBZxr7uyE3GGCk2AD8rQgbvQ BgvJ4T2GVtuldHUgT6zAmTnShE7OyixghU716Hx9S0AMnqn1bBVL3EgyWKLTwaCGrYoR AZN5PpLCbscImtQa0bCBi2kAEwiWA4AduKF4+8w80lMweATiw4zyZRIqg9WuVFmCIWDI y8rQ== X-Gm-Message-State: ANoB5pkKy+yFRoYpnVgaJHIAHljiAawgGh10i/FTMGUAyC2s4fWpgdOi 4/mz92spL2imZZQuYnzz1MA0kw== X-Google-Smtp-Source: AA0mqf6H2EO/npUQnxPso24DXuIYncg32lomcwgcRx/74I+rJHmoea/NN4qLk23bdx3Tq/BPyk+ylA== X-Received: by 2002:a63:1f0f:0:b0:439:4c73:821c with SMTP id f15-20020a631f0f000000b004394c73821cmr25484433pgf.109.1669603502519; Sun, 27 Nov 2022 18:45:02 -0800 (PST) Received: from doug-ryzen-5700G.. ([192.183.212.197]) by smtp.gmail.com with ESMTPSA id z16-20020aa79910000000b005752201d4ffsm1431568pff.213.2022.11.27.18.45.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Nov 2022 18:45:02 -0800 (PST) From: Doug Brown To: Ulf Hansson , Adrian Hunter Cc: Rob Herring , Krzysztof Kozlowski , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, Doug Brown Subject: [PATCH 8/8] dt-bindings: mmc: sdhci-pxa: add pxav1 Date: Sun, 27 Nov 2022 18:44:07 -0800 Message-Id: <20221128024407.224393-9-doug@schmorgal.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221128024407.224393-1-doug@schmorgal.com> References: <20221128024407.224393-1-doug@schmorgal.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add a compatible for the pxav1 controller in the PXA168, along with optional pinctrl properties to use for an errata workaround. Signed-off-by: Doug Brown --- .../devicetree/bindings/mmc/sdhci-pxa.yaml | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml index 1c87f4218e18..e3fb34853921 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Marvell PXA SDHCI v2/v3 bindings +title: Marvell PXA SDHCI v1/v2/v3 bindings maintainers: - Ulf Hansson @@ -34,6 +34,7 @@ allOf: properties: compatible: enum: + - mrvl,pxav1-mmc - mrvl,pxav2-mmc - mrvl,pxav3-mmc - marvell,armada-380-sdhci @@ -61,6 +62,25 @@ properties: - const: io - const: core + pinctrl-names: + description: + Optional for supporting PXA168 SDIO IRQ errata to switch CMD pin between SDIO CMD and + GPIO mode. + minItems: 2 + items: + - const: default + - const: state_cmd_gpio + + pinctrl-0: + description: + should contain default pinctrl. + maxItems: 1 + + pinctrl-1: + description: + should switch CMD pin to GPIO mode as a high output. + maxItems: 1 + mrvl,clk-delay-cycles: description: Specify a number of cycles to delay for tuning. $ref: /schemas/types.yaml#/definitions/uint32