From patchwork Sat Nov 26 19:13:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 628832 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5DF95C4708B for ; Sat, 26 Nov 2022 19:13:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229679AbiKZTNa (ORCPT ); Sat, 26 Nov 2022 14:13:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229657AbiKZTN1 (ORCPT ); Sat, 26 Nov 2022 14:13:27 -0500 Received: from out5-smtp.messagingengine.com (out5-smtp.messagingengine.com [66.111.4.29]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 17541B7EC; Sat, 26 Nov 2022 11:13:26 -0800 (PST) Received: from compute2.internal (compute2.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 836435C00A2; Sat, 26 Nov 2022 14:13:25 -0500 (EST) Received: from mailfrontend2 ([10.202.2.163]) by compute2.internal (MEProxy); Sat, 26 Nov 2022 14:13:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm2; t=1669490005; x=1669576405; bh=5+ 2cpxT9OMwkKRjZz9E1L3Vr/vQhE8GfSwdHcjXgklc=; b=HQakI9OjXZzrgnmI3R wqBkQBvTbY0Ij6NPV6gzKIuAZjCMku1ETpNhDI75cj0HMnq1xf3F1QY1OB9mgzeG p0iP8tsSCcLulMswkHbAsYDD+P014ITZSAjZc4f5vj142Z45hHNBOiJjKZt5UIbZ diMWWQYTFplqCZdh4yxK+Bcm0mcY+M0zIvvd88HXFTgxp695219wJI/hOdIsINQV OOULH+ucIKsdDtiXC0wxvlViM+IywOWHj6ZqmLtXVaMiMcm2d/dpjVkiOB6va8Zo MlvXlh8YmGPZPmdCHOOP30ly5rvNA4SkMbYEYDMNdf5wG7pMloNJWrd++I/fZ2qr GNZQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm1; t=1669490005; x=1669576405; bh=5+2cpxT9OMwkK RjZz9E1L3Vr/vQhE8GfSwdHcjXgklc=; b=GSS1+VttQdaaaavZB4rd3Xt8cLQ9Q uthYlnEaGxyPbYJcIinSoux1/KvZ80yzypFOxj+dOsLZ9GY7oIJg/rKLWHK4Re/E YA5tA3FYAwAdSrBSkefMXmRwFBLUapJebcZci97rJANXxwP+dvZAM9Hb14m9E9GP ylWfHGhzKHh0U4nZMhd34GVxetwHdNXAUH5FFCw+iwdwrWlF+jEwfDBcXnj1GdIF hGpt5YJfK/ji24wbfcCa0slUn4Ex39EeJrTmxXnNBHtRK6DtCS+Y9qIeZCi4Nz74 RkN3i+1Ql5zSmtl2Guoq6/w2JKDRyLj4aL/VqJGQNj9wM4xbO3KMbwOEQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvgedrieejgdduvdegucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepudekteeuudehtdelteevgfduvddvjefhfedulefgudevgeeghefg udefiedtveetnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sat, 26 Nov 2022 14:13:24 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Michael Turquette , Stephen Boyd Cc: Samuel Holland , Krzysztof Kozlowski , Philipp Zabel , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev Subject: [PATCH 3/5] clk: sunxi-ng: d1: Allow building for R528/T113 Date: Sat, 26 Nov 2022 13:13:17 -0600 Message-Id: <20221126191319.6404-4-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20221126191319.6404-1-samuel@sholland.org> References: <20221126191319.6404-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Allwinner released some 32-bit ARM (sun8i) SoCs which use the same CCU as D1. Allow them to reuse the driver. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara --- drivers/clk/sunxi-ng/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 78deee2996ce..b547198a2c65 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -13,14 +13,14 @@ config SUNIV_F1C100S_CCU depends on MACH_SUNIV || COMPILE_TEST config SUN20I_D1_CCU - tristate "Support for the Allwinner D1 CCU" + tristate "Support for the Allwinner D1/R528/T113 CCU" default y - depends on RISCV || COMPILE_TEST + depends on MACH_SUN8I || RISCV || COMPILE_TEST config SUN20I_D1_R_CCU - tristate "Support for the Allwinner D1 PRCM CCU" + tristate "Support for the Allwinner D1/R528/T113 PRCM CCU" default y - depends on RISCV || COMPILE_TEST + depends on MACH_SUN8I || RISCV || COMPILE_TEST config SUN50I_A64_CCU tristate "Support for the Allwinner A64 CCU" From patchwork Sat Nov 26 19:13:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 628831 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0027AC47088 for ; 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Sat, 26 Nov 2022 14:13:26 -0500 (EST) From: Samuel Holland To: Chen-Yu Tsai , Jernej Skrabec , Michael Turquette , Stephen Boyd Cc: Samuel Holland , Krzysztof Kozlowski , Philipp Zabel , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@lists.linux.dev, Fabien Poussin Subject: [PATCH 5/5] clk: sunxi-ng: d1: Add CAN bus gates and resets Date: Sat, 26 Nov 2022 13:13:19 -0600 Message-Id: <20221126191319.6404-6-samuel@sholland.org> X-Mailer: git-send-email 2.37.4 In-Reply-To: <20221126191319.6404-1-samuel@sholland.org> References: <20221126191319.6404-1-samuel@sholland.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Fabien Poussin The D1 CCU contains gates and resets for two CAN buses. While the CAN bus controllers are only documented for the T113 SoC, the CCU is the same across all SoC variants. Signed-off-by: Fabien Poussin Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara --- drivers/clk/sunxi-ng/ccu-sun20i-d1.c | 11 +++++++++++ drivers/clk/sunxi-ng/ccu-sun20i-d1.h | 2 +- include/dt-bindings/clock/sun20i-d1-ccu.h | 2 ++ include/dt-bindings/reset/sun20i-d1-ccu.h | 2 ++ 4 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun20i-d1.c b/drivers/clk/sunxi-ng/ccu-sun20i-d1.c index c5a7df93602c..48a8fb2c43b7 100644 --- a/drivers/clk/sunxi-ng/ccu-sun20i-d1.c +++ b/drivers/clk/sunxi-ng/ccu-sun20i-d1.c @@ -469,6 +469,11 @@ static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws, static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws, 0x91c, BIT(3), 0); +static SUNXI_CCU_GATE_HWS(bus_can0_clk, "bus-can0", apb1_hws, + 0x92c, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_can1_clk, "bus-can1", apb1_hws, + 0x92c, BIT(1), 0); + static const struct clk_parent_data spi_parents[] = { { .fw_name = "hosc" }, { .hw = &pll_periph0_clk.hw }, @@ -997,6 +1002,8 @@ static struct ccu_common *sun20i_d1_ccu_clks[] = { &bus_i2c1_clk.common, &bus_i2c2_clk.common, &bus_i2c3_clk.common, + &bus_can0_clk.common, + &bus_can1_clk.common, &spi0_clk.common, &spi1_clk.common, &bus_spi0_clk.common, @@ -1147,6 +1154,8 @@ static struct clk_hw_onecell_data sun20i_d1_hw_clks = { [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw, + [CLK_BUS_CAN0] = &bus_can0_clk.common.hw, + [CLK_BUS_CAN1] = &bus_can1_clk.common.hw, [CLK_SPI0] = &spi0_clk.common.hw, [CLK_SPI1] = &spi1_clk.common.hw, [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, @@ -1252,6 +1261,8 @@ static struct ccu_reset_map sun20i_d1_ccu_resets[] = { [RST_BUS_I2C1] = { 0x91c, BIT(17) }, [RST_BUS_I2C2] = { 0x91c, BIT(18) }, [RST_BUS_I2C3] = { 0x91c, BIT(19) }, + [RST_BUS_CAN0] = { 0x92c, BIT(16) }, + [RST_BUS_CAN1] = { 0x92c, BIT(17) }, [RST_BUS_SPI0] = { 0x96c, BIT(16) }, [RST_BUS_SPI1] = { 0x96c, BIT(17) }, [RST_BUS_EMAC] = { 0x97c, BIT(16) }, diff --git a/drivers/clk/sunxi-ng/ccu-sun20i-d1.h b/drivers/clk/sunxi-ng/ccu-sun20i-d1.h index e303176f0d4e..b14da36e2537 100644 --- a/drivers/clk/sunxi-ng/ccu-sun20i-d1.h +++ b/drivers/clk/sunxi-ng/ccu-sun20i-d1.h @@ -10,6 +10,6 @@ #include #include -#define CLK_NUMBER (CLK_FANOUT2 + 1) +#define CLK_NUMBER (CLK_BUS_CAN1 + 1) #endif /* _CCU_SUN20I_D1_H_ */ diff --git a/include/dt-bindings/clock/sun20i-d1-ccu.h b/include/dt-bindings/clock/sun20i-d1-ccu.h index e3ac53315e1a..e143b9929763 100644 --- a/include/dt-bindings/clock/sun20i-d1-ccu.h +++ b/include/dt-bindings/clock/sun20i-d1-ccu.h @@ -152,5 +152,7 @@ #define CLK_FANOUT0 142 #define CLK_FANOUT1 143 #define CLK_FANOUT2 144 +#define CLK_BUS_CAN0 145 +#define CLK_BUS_CAN1 146 #endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun20i-d1-ccu.h b/include/dt-bindings/reset/sun20i-d1-ccu.h index de9ff5203239..f8001cf50bf1 100644 --- a/include/dt-bindings/reset/sun20i-d1-ccu.h +++ b/include/dt-bindings/reset/sun20i-d1-ccu.h @@ -73,5 +73,7 @@ #define RST_BUS_DSP_CFG 63 #define RST_BUS_DSP_DBG 64 #define RST_BUS_RISCV_CFG 65 +#define RST_BUS_CAN0 66 +#define RST_BUS_CAN1 67 #endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */