From patchwork Wed Mar 20 13:17:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 160668 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp281703jan; Wed, 20 Mar 2019 06:18:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqyUNlqTU8vgj8M/VYZayjbD8bR/pocw7LiKgYxdChBBm6kVwWuVoowgzUwnxGeFOiqQKDbR X-Received: by 2002:a63:5415:: with SMTP id i21mr7349928pgb.106.1553087908601; Wed, 20 Mar 2019 06:18:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553087908; cv=none; d=google.com; s=arc-20160816; b=pyCQWnUdcer1GqK78OX3vxjCJ/lbqJFitfKCMRH/kx04yJ50AxXyIXpnIktKlwg3nh 0KFpgnObNwfDLd7xWCO8CFnus+4EBnZQt+IsBt56aicb+2JtK/4SDJkmKUs1oBqXW2cZ VnmcGUjfRYPe2ww8QaxvFOyZkqUHkkeLkx7rkxJeNWBBVpPjLgHDIdAIl2TfwbI9fHkY 4T0/XhrHu3TmJcZLAqQXBYYMJNfA63elUbBoQfSlrU59Sb3Z8+Dco2Y5V5UykzHwnytG ZhP2vG+dq8/0MmpML+cS6u/PSQTPV/80hgjwonAwQWBbD77lqOB8YA6Cc0cF/dp5GhmM iaTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=H2crl7RmZMvIJT00kHO5k98tCahG1bLmtk7Nv322/6A=; b=W4bAmKcgAOn5hopr5FxgC/ASRGSBxfrk8BYv+VAXYCTDAvwTIwOSQB9OvIIs6H2eSn 5lSXNzMdswlrS+yzBMCn3HE7xgVsco1Q7rtT4yQHLht/BjZYDj+Id0DfTDNU7L18ROCq zZk/qu1DhhTRcMJMk9p5pJlfwr9OJm/F2sQrGPO8B+9rFqH7JflDraiwUk7HUj6QKm/6 feITk1cuQ8BP4vWypVKPwUYgQ9BpAY4p68sXI5jEs3F2vago/LfEx/8UwuqzfnudHVlb PVUG3Q4kjMt48ygINlUIEHbjzNr73JcfQoaG2+H2xK/C5MkIPPFrSGrC2irG3AIBxBYp rB2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MSmDp5uW; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Wed, 20 Mar 2019 06:18:24 -0700 (PDT) Received: from localhost ([114.143.122.221]) by smtp.gmail.com with ESMTPSA id u62sm7579877pfa.124.2019.03.20.06.18.23 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Mar 2019 06:18:23 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, Daniel Lezcano , David Brown , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCHv3 01/23] drivers: thermal: tsens: Document the data structures Date: Wed, 20 Mar 2019 18:47:41 +0530 Message-Id: <643831e7268ec289adcb6817b348689ff029ae46.1553086065.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Describe how the TSENS device and the various sensors connected to it are described in the driver Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens.h | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 7b7feee5dc46..89318523c848 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -14,6 +14,16 @@ struct tsens_device; +/** + * struct tsens_sensor - data for each sensor connected to the tsens device + * @tmdev: tsens device instance that this sensor is connected to + * @tzd: pointer to the thermal zone that this sensor is in + * @offset: offset of temperature adjustment curve + * @id: Sensor ID + * @hw_id: HW ID can be used in case of platform-specific IDs + * @slope: slope of temperature adjustment curve + * @status: 8960-specific variable to track 8960 and 8660 status register offset + */ struct tsens_sensor { struct tsens_device *tmdev; struct thermal_zone_device *tzd; @@ -55,8 +65,8 @@ enum reg_list { }; /** - * struct tsens_data - tsens instance specific data - * @num_sensors: Max number of sensors supported by platform + * struct tsens_data - tsens platform data + * @num_sensors: Number of sensors supported by platform * @ops: operations the tsens instance supports * @hw_ids: Subset of sensors ids supported by platform, if not the first n * @reg_offsets: Register offsets for commonly used registers @@ -68,12 +78,27 @@ struct tsens_data { unsigned int *hw_ids; }; -/* Registers to be saved/restored across a context loss */ +/** + * struct tsens_context - Registers to be saved/restored across a context loss + */ struct tsens_context { int threshold; int control; }; +/** + * struct tsens_device - private data for each instance of the tsens IP + * @dev: pointer to struct device + * @num_sensors: number of sensors enabled on this device + * @tm_map: pointer to TM register address space + * @srot_map: pointer to SROT register address space + * @tm_offset: deal with old device trees that don't address TM and SROT + * address space separately + * @reg_offsets: array of offsets to important regs for this version of IP + * @ctx: registers to be saved and restored during suspend/resume + * @ops: pointer to list of callbacks supported by this device + * @sensor: list of sensors attached to this device + */ struct tsens_device { struct device *dev; u32 num_sensors; From patchwork Wed Mar 20 13:17:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 160669 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp281800jan; 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Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens-8916.c | 2 +- drivers/thermal/qcom/tsens-8960.c | 2 +- drivers/thermal/qcom/tsens-8974.c | 2 +- drivers/thermal/qcom/tsens-v2.c | 4 ++-- drivers/thermal/qcom/tsens.c | 2 +- drivers/thermal/qcom/tsens.h | 8 ++++---- 6 files changed, 10 insertions(+), 10 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-8916.c b/drivers/thermal/qcom/tsens-8916.c index c6dd620ac029..66edcfca1526 100644 --- a/drivers/thermal/qcom/tsens-8916.c +++ b/drivers/thermal/qcom/tsens-8916.c @@ -97,7 +97,7 @@ static const struct tsens_ops ops_8916 = { .get_temp = get_temp_common, }; -const struct tsens_data data_8916 = { +const struct tsens_plat_data data_8916 = { .num_sensors = 5, .ops = &ops_8916, .reg_offsets = { [SROT_CTRL_OFFSET] = 0x0 }, diff --git a/drivers/thermal/qcom/tsens-8960.c b/drivers/thermal/qcom/tsens-8960.c index 0f0adb302a7b..f3c3820e6e8e 100644 --- a/drivers/thermal/qcom/tsens-8960.c +++ b/drivers/thermal/qcom/tsens-8960.c @@ -277,7 +277,7 @@ static const struct tsens_ops ops_8960 = { .resume = resume_8960, }; -const struct tsens_data data_8960 = { +const struct tsens_plat_data data_8960 = { .num_sensors = 11, .ops = &ops_8960, }; diff --git a/drivers/thermal/qcom/tsens-8974.c b/drivers/thermal/qcom/tsens-8974.c index 3d3fda3d731b..5023f20afc14 100644 --- a/drivers/thermal/qcom/tsens-8974.c +++ b/drivers/thermal/qcom/tsens-8974.c @@ -229,7 +229,7 @@ static const struct tsens_ops ops_8974 = { .get_temp = get_temp_common, }; -const struct tsens_data data_8974 = { +const struct tsens_plat_data data_8974 = { .num_sensors = 11, .ops = &ops_8974, .reg_offsets = { [SROT_CTRL_OFFSET] = 0x0 }, diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index 381a212872bf..cc98a61e093b 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -66,13 +66,13 @@ static const struct tsens_ops ops_generic_v2 = { .get_temp = get_temp_tsens_v2, }; -const struct tsens_data data_tsens_v2 = { +const struct tsens_plat_data data_tsens_v2 = { .ops = &ops_generic_v2, .reg_offsets = { [SROT_CTRL_OFFSET] = 0x4 }, }; /* Kept around for backward compatibility with old msm8996.dtsi */ -const struct tsens_data data_8996 = { +const struct tsens_plat_data data_8996 = { .num_sensors = 13, .ops = &ops_generic_v2, .reg_offsets = { [SROT_CTRL_OFFSET] = 0x4 }, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index f1ec9bbe4717..065ec2189bd3 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -102,7 +102,7 @@ static int tsens_probe(struct platform_device *pdev) struct device *dev; struct device_node *np; struct tsens_device *tmdev; - const struct tsens_data *data; + const struct tsens_plat_data *data; const struct of_device_id *id; u32 num_sensors; diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 89318523c848..232376c690cc 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -65,13 +65,13 @@ enum reg_list { }; /** - * struct tsens_data - tsens platform data + * struct tsens_plat_data - tsens compile-time platform data * @num_sensors: Number of sensors supported by platform * @ops: operations the tsens instance supports * @hw_ids: Subset of sensors ids supported by platform, if not the first n * @reg_offsets: Register offsets for commonly used registers */ -struct tsens_data { +struct tsens_plat_data { const u32 num_sensors; const struct tsens_ops *ops; const u16 reg_offsets[REG_ARRAY_SIZE]; @@ -117,8 +117,8 @@ int init_common(struct tsens_device *); int get_temp_common(struct tsens_device *, int, int *); /* TSENS v1 targets */ -extern const struct tsens_data data_8916, data_8974, data_8960; +extern const struct tsens_plat_data data_8916, data_8974, data_8960; /* TSENS v2 targets */ -extern const struct tsens_data data_8996, data_tsens_v2; +extern const struct tsens_plat_data data_8996, data_tsens_v2; #endif /* __QCOM_TSENS_H__ */ From patchwork Wed Mar 20 13:17:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 160674 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp282302jan; Wed, 20 Mar 2019 06:18:58 -0700 (PDT) X-Google-Smtp-Source: APXvYqxEmkwVkDsaQZCN0TzOfKS6JY6syMEHuIWYAh6qT0vrRkxtF7/SjCnl9hhyW4LmqIDEg1oI X-Received: by 2002:a62:39c2:: with SMTP id u63mr7911436pfj.11.1553087938789; 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[209.132.180.67]) by mx.google.com with ESMTP id l14si1700121pfj.112.2019.03.20.06.18.58; Wed, 20 Mar 2019 06:18:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UA6IDtRG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728194AbfCTNS5 (ORCPT + 31 others); Wed, 20 Mar 2019 09:18:57 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:46142 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727873AbfCTNS4 (ORCPT ); Wed, 20 Mar 2019 09:18:56 -0400 Received: by mail-pf1-f193.google.com with SMTP id 9so1673650pfj.13 for ; Wed, 20 Mar 2019 06:18:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=xvoojo3eKvN4L9IBWkrmUvvE40O1kNL0V6YvK2/qLWI=; b=UA6IDtRGG1iSXnGLCyBPaG1oaix6XoSFsMXsBU/HaGX/lRyR3s8eO7kDJh7A2Aziaw mSpDWFxMetNqY8YMvDCMz6zrHbMuO7u20p+1HlfN9JsoHVVbopHjQM8SzpJZF2kyx8mY uJaBB8e2K21w2MHHkgo87ne6eaGvpGv9ZyzjjXYtj2C6SV4wz/s9WsURw2f0D7kswzyY //s+Tc4UOFyZMauskzGFdPOWF8Qv+7sgrc+1EHPTV/IBgt2Rt1MJAK9lveTRSzQ5abXo zcAepPC9NE1Swcc50zRHPokuz+uLNRl0wU3rGklX7O+v9Xc8BzFsBnaytIH89luyIhNi TOEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=xvoojo3eKvN4L9IBWkrmUvvE40O1kNL0V6YvK2/qLWI=; b=Lm2jnrMrlYHdDpxcdFAw0M3ac1ekn82jNYim+KoNDOqkJ6qNiW4xyg2DeFnJTg3lzI MOS0tUIJDAo/LKnZrNdI34HRY69M+2+u8jt9uaUsAgMBrmSK2C6ehqbdtBIhnqBhHWUY wUTIP35s6mV/Akh7CV5PrLg70g+Qpt5JL9Lz54iYbMDDL7FVOs3JShpo9Ae+ViIqmLp8 aquRj2w8iVFYULDkc79wTn2DX6K7SrvWNMlR2BmSv/Ld93V13/vxVGAXdpWdfJY6AM0j wXU73hlEJ0LFk+HY+vavaYwsIucgoR2FPTQDSw/fyjg4Kiacqwzh6qaAuy3DLQ2hrTyx CpGw== X-Gm-Message-State: APjAAAUKtd9Wx46CVpq0/BZa6Ya1Y82qKBN/WaNm2CWTwSOEGUiaSq+/ mdv84WrNagbpEKiaXqkFEoj6X9TOSk8= X-Received: by 2002:a63:4e64:: with SMTP id o36mr673064pgl.213.1553087935197; Wed, 20 Mar 2019 06:18:55 -0700 (PDT) Received: from localhost ([114.143.122.221]) by smtp.gmail.com with ESMTPSA id e14sm7704140pga.61.2019.03.20.06.18.53 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Mar 2019 06:18:54 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, Daniel Lezcano , David Brown , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCHv3 07/23] drivers: thermal: tsens: Rename tsens-8916 to prepare to merge with tsens-8974 Date: Wed, 20 Mar 2019 18:47:47 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 8916 and 8974 use v0.1.0 of the TSENS IP. Rename tsens-8916 to prepare it for merging with tsens-8974 in a later commit. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/Makefile | 2 +- drivers/thermal/qcom/{tsens-8916.c => tsens-v0_1.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/thermal/qcom/{tsens-8916.c => tsens-v0_1.c} (100%) -- 2.17.1 diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index 717a08600bb5..1f2fafd43dff 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -1,3 +1,3 @@ obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o -qcom_tsens-y += tsens.o tsens-common.o tsens-8916.o tsens-8974.o tsens-8960.o tsens-v2.o +qcom_tsens-y += tsens.o tsens-common.o tsens-v0_1.o tsens-8974.o tsens-8960.o tsens-v2.o obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o diff --git a/drivers/thermal/qcom/tsens-8916.c b/drivers/thermal/qcom/tsens-v0_1.c similarity index 100% rename from drivers/thermal/qcom/tsens-8916.c rename to drivers/thermal/qcom/tsens-v0_1.c From patchwork Wed Mar 20 13:17:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 160681 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp282921jan; Wed, 20 Mar 2019 06:19:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqw2lCaujspWfzk5i6YjaPA13A7yNT7j/jtFl3XjxpVCfrK2YMsJLofONZcYPF7SSIrHgPPi X-Received: by 2002:a62:4649:: with SMTP id t70mr7883319pfa.100.1553087971678; Wed, 20 Mar 2019 06:19:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553087971; cv=none; d=google.com; s=arc-20160816; b=QIWJBhH657NiqYt63FH7aEkYGB9TUZD2/vnmhnckP4hikR5E5n4nr64wRymMxT+Peo 2kVZ/4RGQgWNokYtGQlc42/FmHrKRPtNz55P+x3D2kY7riLhe3S38ifBYyJI+OJ6PWEP 37LatAyMQI+cQM/3kkXXRGhmnUf24B7xekXX5kEfKzrGok1jYDmCQ0lBb+3V7hiapO7l /7b23dF2wl1XVVWramRRSFEqzHsTPo9eqq4uSArc3Legpw8Ulm2jqLnWj6s4DxGhy0VT D9IKWSqJtlnTvTtjjUx0EuAB4VRMGSZjZidakKiyjLP9HduWB6dxod1Olt76iJvgscXY J07w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=iB+qXWUd5MH36EuKW0QX1Zz13dgt3ZzYo72RTOcmlkQ=; b=OVFgJ0ns5lsTBnkznWezr+nfF5soF9FZrJ6ruPb88iDYmcSKt+e2YH9cR91V7vajCs yB47/5WP8jhR4P5KZSoYcT4EDF6xPlB71FhyJYpbC6jBtF1JFkmhbZziXT5SsgyYsPBr dJjvO5KZPGUmCNLIDy37rQytWTqKHxrRA/Isb0YXYsw1Db1wIkukJo8fEMIrk8VfoPMF j5L4W2yJC7Z8Hhh6P4MwIbzNDuOK0kxtjuVkSGdAxahv4AK8jV8LyF0AT1pOkTLztzhN soFYQAxdpG+lBrRhD8D7PkSqnX3MvfCdzxnXrPemSvKJnNQo48+e1x4aGZuZ1Xy7K+56 SKUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DY6eu9Mc; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index a3bf7de88ae8..527c42cfd2d5 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -35,8 +35,8 @@ struct tsens_sensor { struct tsens_priv *priv; struct thermal_zone_device *tzd; int offset; - int id; - int hw_id; + unsigned int id; + unsigned int hw_id; int slope; u32 status; }; From patchwork Wed Mar 20 13:18:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 160687 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp283379jan; Wed, 20 Mar 2019 06:19:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqwI7D7iyv9CrLhJjlTJXrD3iY97M/sV3QgT6mvK1dx0BBoGsYHItxJBDywql9yGtuFV53nk X-Received: by 2002:a17:902:1744:: with SMTP id i62mr7788916pli.24.1553087996476; Wed, 20 Mar 2019 06:19:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553087996; cv=none; d=google.com; s=arc-20160816; b=flW1QbTL1P9kqrXTkC2s+0DN/MuEFpE/Tp92419YJtrG9KniJeYEfMS+mbPGKzsvdv 1em12oTSqJNroJLLr8AHCbZLis/GdVsUNWXQhultRKJLz07PV+vENZMe6kxyv9zb6IlL DC1YVSj23qhY7D/f0g7K66dJkQMm/tLcgDo59+uEDPGRoTv7SaQfkjXgweVAIXgoMrrU LFgvc9XMQ2/j0T660E7kiSyUcqUQfC9KTT3rtoZ1AnP4kwTMAI38YoTchk9loChiSFQk GwlNTiOp6iRFBCA/h60qAl2Tuy/6EeDiZ5YufiZc8vcqo8TqDBwmgUtwQ2PfeNE5tEh1 hn3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=8Bs4kKc2Hg0hH5YpBzAGZ8vEGwKzsO6jmmrcnu918/Y=; b=kPNHns/CiX7jziBtUjG0eAlMc/meHTx9VcZBw0Et9dj/zydcY5f6oK2VSxRV22yGHK JaTehpGIgqHclyMmXAYKfQTXdCYIyfhw0fOJJJtQzmOeXdeY6YxI3LRNvIMxeZG5A5sl DbvtdZ7Ge6EII8OJSFgfx708IjRlPO8vD7+mj1tAOnwH18Q+Y8RnpG3yADVkDIYGZ+IK CuXylE2TW6gLwKh8Xd/hl4g71svf7xpl9hQGJ79vJFtWO4AYQrBwgS6SXWgA1Fr7F5Nc egd4kZzfGjnvFGzUObVseQrZGuoJWriQDw7hIjoypUiH6Cxu1q11WrF+xo0iNZZpjmPv i+0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=McpGFvqG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 38si1709949pgn.121.2019.03.20.06.19.55; Wed, 20 Mar 2019 06:19:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=McpGFvqG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728379AbfCTNTy (ORCPT + 31 others); Wed, 20 Mar 2019 09:19:54 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:43929 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728367AbfCTNTw (ORCPT ); Wed, 20 Mar 2019 09:19:52 -0400 Received: by mail-pg1-f193.google.com with SMTP id l11so1781434pgq.10 for ; Wed, 20 Mar 2019 06:19:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=8Bs4kKc2Hg0hH5YpBzAGZ8vEGwKzsO6jmmrcnu918/Y=; b=McpGFvqG+X9KOmvBTFwZ1EBNyNvEg8Q1ujbn5y75452d+O2uVJ21zsGEIF3jAamDQ+ d1AThVx6LqNt3dMGxGGW6aALH0xxJ4E3fa/vRro6LcAKaYLBLctH+UxO3P8P2cZwYFlv rnuI8whzgwa9+eP7c10hVihKDTBHJTAOwHmVQqDtXm38WVgOf8etxyOWI8rldUyUrWcP 8dr/jmWErTiYo8msbBhA+61BrpkQBnOhIJM4JS7JhjKtXy2SL5F6KNrx6ek/feiks4Hc bmteEHW2lxFyhm+kfUhhcwWG8b2jnY629PUAXEK7/8y01ABCtMiXlKbR8B18hC2hlUfC 7BoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=8Bs4kKc2Hg0hH5YpBzAGZ8vEGwKzsO6jmmrcnu918/Y=; b=Cq/11A4SoK/yxS9f4WYv9kJZZdJVy0bEdy6xnz9CfJTrAWClnF6pKbmnWkVPb5o0D+ q1VIGpBCEAiOZVDWqqvukUL4jUErGUHohyrcDPl8sUnfa9aMntqDPrLKudHYtnBkGxdt y+pYWu8FbjXDFgLlDWsPmPIVJliEmMWI+GQfCH+M6iZ0GLh9M0SXiLuM0OVQGNe5oNsW BOooFwAI/bUrqAL6p0M64TBFqbQ2HPJ67Cu3/lGeg2CG2jiNWyBJsw90OVMuUvHGdZf7 fw0lQbEUHkDHD0Dov3tc0MMdWlhRpiBGXk4xZ/BFFe6As+Mevd+gYBhDr7IPxslJH2FD 1bvw== X-Gm-Message-State: APjAAAW78k5+Do5RtiOAukc8dLzWFNtgqnxos7cw21zrdIbHzF0QIU9A Jh2MHew1X/8uzLmoThRWVqIYBW1Q+VQ= X-Received: by 2002:a63:e106:: with SMTP id z6mr28405775pgh.418.1553087991269; Wed, 20 Mar 2019 06:19:51 -0700 (PDT) Received: from localhost ([114.143.122.221]) by smtp.gmail.com with ESMTPSA id q86sm7319349pfi.171.2019.03.20.06.19.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Mar 2019 06:19:50 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, Daniel Lezcano , David Brown , Zhang Rui Cc: linux-pm@vger.kernel.org Subject: [PATCHv3 20/23] drivers: thermal: tsens: Add generic support for TSENS v1 IP Date: Wed, 20 Mar 2019 18:48:00 +0530 Message-Id: <6ff45cf459beade7f71eb9323d84a872b6ba1021.1553086065.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org qcs404 has a single TSENS IP block with 10 sensors. It uses version 1.4 of the TSENS IP, functionality for which is encapsulated inside the qcom,tsens-v1 compatible. Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/Makefile | 4 +- drivers/thermal/qcom/tsens-v1.c | 193 ++++++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.c | 3 + drivers/thermal/qcom/tsens.h | 3 + 4 files changed, 202 insertions(+), 1 deletion(-) create mode 100644 drivers/thermal/qcom/tsens-v1.c -- 2.17.1 diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile index 7fa3cadce760..fc6fe50cdde4 100644 --- a/drivers/thermal/qcom/Makefile +++ b/drivers/thermal/qcom/Makefile @@ -1,3 +1,5 @@ obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o -qcom_tsens-y += tsens.o tsens-common.o tsens-v0_1.o tsens-8960.o tsens-v2.o + +qcom_tsens-y += tsens.o tsens-common.o tsens-v0_1.o \ + tsens-8960.o tsens-v2.o tsens-v1.o obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c new file mode 100644 index 000000000000..a1221efd1ddc --- /dev/null +++ b/drivers/thermal/qcom/tsens-v1.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019, Linaro Limited + */ + +#include +#include +#include +#include "tsens.h" + +/* ----- SROT ------ */ +#define SROT_HW_VER_OFF 0x0000 +#define SROT_CTRL_OFF 0x0004 + +/* ----- TM ------ */ +#define TM_INT_EN_OFF 0x0000 +#define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004 +#define TM_Sn_STATUS_OFF 0x0044 +#define TM_TRDY_OFF 0x0084 + +/* eeprom layout data for qcs404/405 (v1) */ +#define BASE0_MASK 0x000007f8 +#define BASE1_MASK 0x0007f800 +#define BASE0_SHIFT 3 +#define BASE1_SHIFT 11 + +#define S0_P1_MASK 0x0000003f +#define S1_P1_MASK 0x0003f000 +#define S2_P1_MASK 0x3f000000 +#define S3_P1_MASK 0x000003f0 +#define S4_P1_MASK 0x003f0000 +#define S5_P1_MASK 0x0000003f +#define S6_P1_MASK 0x0003f000 +#define S7_P1_MASK 0x3f000000 +#define S8_P1_MASK 0x000003f0 +#define S9_P1_MASK 0x003f0000 + +#define S0_P2_MASK 0x00000fc0 +#define S1_P2_MASK 0x00fc0000 +#define S2_P2_MASK_1_0 0xc0000000 +#define S2_P2_MASK_5_2 0x0000000f +#define S3_P2_MASK 0x0000fc00 +#define S4_P2_MASK 0x0fc00000 +#define S5_P2_MASK 0x00000fc0 +#define S6_P2_MASK 0x00fc0000 +#define S7_P2_MASK_1_0 0xc0000000 +#define S7_P2_MASK_5_2 0x0000000f +#define S8_P2_MASK 0x0000fc00 +#define S9_P2_MASK 0x0fc00000 + +#define S0_P1_SHIFT 0 +#define S0_P2_SHIFT 6 +#define S1_P1_SHIFT 12 +#define S1_P2_SHIFT 18 +#define S2_P1_SHIFT 24 +#define S2_P2_SHIFT_1_0 30 + +#define S2_P2_SHIFT_5_2 0 +#define S3_P1_SHIFT 4 +#define S3_P2_SHIFT 10 +#define S4_P1_SHIFT 16 +#define S4_P2_SHIFT 22 + +#define S5_P1_SHIFT 0 +#define S5_P2_SHIFT 6 +#define S6_P1_SHIFT 12 +#define S6_P2_SHIFT 18 +#define S7_P1_SHIFT 24 +#define S7_P2_SHIFT_1_0 30 + +#define S7_P2_SHIFT_5_2 0 +#define S8_P1_SHIFT 4 +#define S8_P2_SHIFT 10 +#define S9_P1_SHIFT 16 +#define S9_P2_SHIFT 22 + +#define CAL_SEL_MASK 7 +#define CAL_SEL_SHIFT 0 + +static int calibrate_v1(struct tsens_priv *priv) +{ + u32 base0 = 0, base1 = 0; + u32 p1[10], p2[10]; + u32 mode = 0, lsb = 0, msb = 0; + u32 *qfprom_cdata; + int i; + + qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); + if (IS_ERR(qfprom_cdata)) + return PTR_ERR(qfprom_cdata); + + mode = (qfprom_cdata[4] & CAL_SEL_MASK) >> CAL_SEL_SHIFT; + dev_dbg(priv->dev, "calibration mode is %d\n", mode); + + switch (mode) { + case TWO_PT_CALIB: + base1 = (qfprom_cdata[4] & BASE1_MASK) >> BASE1_SHIFT; + p2[0] = (qfprom_cdata[0] & S0_P2_MASK) >> S0_P2_SHIFT; + p2[1] = (qfprom_cdata[0] & S1_P2_MASK) >> S1_P2_SHIFT; + /* This value is split over two registers, 2 bits and 4 bits */ + lsb = (qfprom_cdata[0] & S2_P2_MASK_1_0) >> S2_P2_SHIFT_1_0; + msb = (qfprom_cdata[1] & S2_P2_MASK_5_2) >> S2_P2_SHIFT_5_2; + p2[2] = msb << 2 | lsb; + p2[3] = (qfprom_cdata[1] & S3_P2_MASK) >> S3_P2_SHIFT; + p2[4] = (qfprom_cdata[1] & S4_P2_MASK) >> S4_P2_SHIFT; + p2[5] = (qfprom_cdata[2] & S5_P2_MASK) >> S5_P2_SHIFT; + p2[6] = (qfprom_cdata[2] & S6_P2_MASK) >> S6_P2_SHIFT; + /* This value is split over two registers, 2 bits and 4 bits */ + lsb = (qfprom_cdata[2] & S7_P2_MASK_1_0) >> S7_P2_SHIFT_1_0; + msb = (qfprom_cdata[3] & S7_P2_MASK_5_2) >> S7_P2_SHIFT_5_2; + p2[7] = msb << 2 | lsb; + p2[8] = (qfprom_cdata[3] & S8_P2_MASK) >> S8_P2_SHIFT; + p2[9] = (qfprom_cdata[3] & S9_P2_MASK) >> S9_P2_SHIFT; + for (i = 0; i < priv->num_sensors; i++) + p2[i] = ((base1 + p2[i]) << 2); + /* Fall through */ + case ONE_PT_CALIB2: + base0 = (qfprom_cdata[4] & BASE0_MASK) >> BASE0_SHIFT; + p1[0] = (qfprom_cdata[0] & S0_P1_MASK) >> S0_P1_SHIFT; + p1[1] = (qfprom_cdata[0] & S1_P1_MASK) >> S1_P1_SHIFT; + p1[2] = (qfprom_cdata[0] & S2_P1_MASK) >> S2_P1_SHIFT; + p1[3] = (qfprom_cdata[1] & S3_P1_MASK) >> S3_P1_SHIFT; + p1[4] = (qfprom_cdata[1] & S4_P1_MASK) >> S4_P1_SHIFT; + p1[5] = (qfprom_cdata[2] & S5_P1_MASK) >> S5_P1_SHIFT; + p1[6] = (qfprom_cdata[2] & S6_P1_MASK) >> S6_P1_SHIFT; + p1[7] = (qfprom_cdata[2] & S7_P1_MASK) >> S7_P1_SHIFT; + p1[8] = (qfprom_cdata[3] & S8_P1_MASK) >> S8_P1_SHIFT; + p1[9] = (qfprom_cdata[3] & S9_P1_MASK) >> S9_P1_SHIFT; + for (i = 0; i < priv->num_sensors; i++) + p1[i] = (((base0) + p1[i]) << 2); + break; + default: + for (i = 0; i < priv->num_sensors; i++) { + p1[i] = 500; + p2[i] = 780; + } + break; + } + + compute_intercept_slope(priv, p1, p2, mode); + + return 0; +} + +/* v1.x: qcs404,405 */ + +const struct tsens_features tsens_v1_feat = { + .ver_major = VER_1_X, + .crit_int = 0, + .adc = 1, + .srot_split = 1, + .max_sensors = 11, +}; + +const struct reg_field tsens_v1_regfields[MAX_REGFIELDS] = { + /* ----- SROT ------ */ + /* VERSION */ + [VER_MAJOR] = REG_FIELD(SROT_HW_VER_OFF, 28, 31), + [VER_MINOR] = REG_FIELD(SROT_HW_VER_OFF, 16, 27), + [VER_STEP] = REG_FIELD(SROT_HW_VER_OFF, 0, 15), + /* CTRL_OFFSET */ + [TSENS_EN] = REG_FIELD(SROT_CTRL_OFF, 0, 0), + [TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF, 1, 1), + [SENSOR_EN] = REG_FIELD(SROT_CTRL_OFF, 3, 13), + + /* ----- TM ------ */ + /* INTERRUPT ENABLE */ + [INT_EN] = REG_FIELD(TM_INT_EN_OFF, 0, 0), + + /* Sn_STATUS */ + REG_FIELD_FOR_EACH_SENSOR11(LAST_TEMP, TM_Sn_STATUS_OFF, 0, 9), + REG_FIELD_FOR_EACH_SENSOR11(VALID, TM_Sn_STATUS_OFF, 14, 14), + REG_FIELD_FOR_EACH_SENSOR11(MIN_STATUS, TM_Sn_STATUS_OFF, 10, 10), + REG_FIELD_FOR_EACH_SENSOR11(LOWER_STATUS, TM_Sn_STATUS_OFF, 11, 11), + REG_FIELD_FOR_EACH_SENSOR11(UPPER_STATUS, TM_Sn_STATUS_OFF, 12, 12), + /* No CRITICAL field on v1.x */ + REG_FIELD_FOR_EACH_SENSOR11(MAX_STATUS, TM_Sn_STATUS_OFF, 13, 13), + + /* TRDY: 1=ready, 0=in progress */ + [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0), +}; + +static const struct tsens_ops ops_generic_v1 = { + .init = init_common, + .calibrate = calibrate_v1, + .get_temp = get_temp_tsens_valid, +}; + +const struct tsens_plat_data data_tsens_v1 = { + .ops = &ops_generic_v1, + .feat = &tsens_v1_feat, + .fields = tsens_v1_regfields, +}; diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index fc44cac31fa5..36b0b52db524 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -63,6 +63,9 @@ static const struct of_device_id tsens_table[] = { }, { .compatible = "qcom,msm8996-tsens", .data = &data_8996, + }, { + .compatible = "qcom,tsens-v1", + .data = &data_tsens_v1, }, { .compatible = "qcom,tsens-v2", .data = &data_tsens_v2, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index f14a87aa1a47..d648fba235cf 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -318,6 +318,9 @@ extern const struct tsens_plat_data data_8960; /* TSENS v0.1 targets */ extern const struct tsens_plat_data data_8916, data_8974; +/* TSENS v1 targets */ +extern const struct tsens_plat_data data_tsens_v1; + /* TSENS v2 targets */ extern const struct tsens_plat_data data_8996, data_tsens_v2; From patchwork Wed Mar 20 13:18:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 160688 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp283445jan; Wed, 20 Mar 2019 06:20:00 -0700 (PDT) X-Google-Smtp-Source: APXvYqz9W0iBT8Qj16HU6F0P8vVdUKt1AzS1OmYzoavyACB71TmZaKzoHfQt9Bqc9KFZOACniEGZ X-Received: by 2002:a17:902:aa90:: with SMTP id d16mr7816357plr.250.1553087999930; Wed, 20 Mar 2019 06:19:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553087999; cv=none; d=google.com; s=arc-20160816; b=KRds839Wq14bYGYivTm1Bz0yGcZVKAYSbW0CDdgiNmlAXhr5++Vl6xFYZAb4/lgsIO 9CXM2iFEr6xmpJF6uTirAfQM3PD/f/U7udaoOtCmFOxh3ghZSsV/MRwQhYR5IAQibkpi C3rE8k7/leRadHHMz4hQ2lZ4o9wLueDtxbzs/eba0SmdeYzDJtAlQVw4rfMCtZlsxHS0 si+Tiy8ex4nIW1XiSDhfn/7C4q7J942yTb7d+BhoPM3Ew30QSCY5EKdYyknnPW1iqjEj z8Q5SEB6MSS8sr/OiACVXk6Q59qzD475qkXQTZ5M+Gd1E1U26jJcONHXJSJMZ9rMdb7T Hveg== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id 38si1709949pgn.121.2019.03.20.06.19.59; Wed, 20 Mar 2019 06:19:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="jY9OC/Z6"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728387AbfCTNT6 (ORCPT + 31 others); Wed, 20 Mar 2019 09:19:58 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:43454 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728367AbfCTNT4 (ORCPT ); Wed, 20 Mar 2019 09:19:56 -0400 Received: by mail-pf1-f193.google.com with SMTP id c8so1915148pfd.10 for ; Wed, 20 Mar 2019 06:19:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=qKXF150NnoD6hcYF3ZEcLMoM6yEN8jPT+N985toWhiQ=; b=jY9OC/Z6mfCscuQwlqSkewP82zJgv7CWpnTSmleHgo2FrKtoV3ptvqL97VpzbiTwEI ZNtbTifHoKSXeXij9/9HwZGFezGjtWGbq2cJgvaTGy4ZpiLfigLW/70WimfaARhyo/Tv DoLuBoAtMHC7QhoxFwIa2LbT9vu3KKfgWxwyEqEUwtU8YpIz0xoOhquRmFMCUDyRl3gD 49xzbj/gIgkrfZGuLZkJsrWJ/i5Cls0T5e5rTzc4GSsxpmTSQhhnby4J06X9vHyg7XCF osz+lzlU3BQG7zX0twU7PFkPIOdcgTbksCs3zCE7Qoz5D25kt2Xd8af64qsViQzh4ZAX AaHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=qKXF150NnoD6hcYF3ZEcLMoM6yEN8jPT+N985toWhiQ=; b=hHKp4n/W0Rw1JBd8Edh9Sar2hIdcBJ/0zbDdzkDhX7kd2wDgPtiZyti170hb7mVeNb cg0syfp18lxV6W9VJSxpsbtvJhOhHoRKssRmEX9LdpBDWBg3jJdJLgjpe5/hc6mxAooG NjlOZ2tgdqRhQPh58H2Ui+c0O7wh51Zt3OQK7tg8iLUi1ul1XVBpI+2G6eBkSrBmIW6r icKrzGCtFswAN4aY0R5F/LgTUNiRELN/DDNx3thccUbqn4xQTCB4SaHV8U+oEsjIutTa WIxfjDkCQy92NpPthnRqC7I/GJmXUEW+yBAfdxvrnvv1qNNqnE+1e/ySjkDbVYm55tsq 5GWw== X-Gm-Message-State: APjAAAVaDOmwYSETYu7M+Y67JEAbfFNU9PSUFXWnL8qDbrdGxExKQA39 MIatwJ9aAkv3Wej+ILmcaw3F2KduG20= X-Received: by 2002:aa7:9088:: with SMTP id i8mr6087166pfa.118.1553087995113; Wed, 20 Mar 2019 06:19:55 -0700 (PDT) Received: from localhost ([114.143.122.221]) by smtp.gmail.com with ESMTPSA id l28sm6945655pfi.186.2019.03.20.06.19.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Mar 2019 06:19:54 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, Daniel Lezcano , David Brown , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCHv3 21/23] arm64: dts: qcom: qcs404: Add tsens controller Date: Wed, 20 Mar 2019 18:48:01 +0530 Message-Id: <9108372823aba9288b98b1c8a003c21b578d1e13.1553086065.git.amit.kucheria@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org qcs404 has a single TSENS IP block with 10 sensors. The calibration data is stored in an eeprom (qfprom) that is accessed through the nvmem framework. We add the qfprom node to allow the tsens sensors to be calibrated correctly. Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index e8fd26633d57..7881792980b8 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -259,6 +259,16 @@ reg = <0x00060000 0x6000>; }; + qfprom: qfprom@a4000 { + compatible = "qcom,qfprom"; + reg = <0x000a4000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + tsens_caldata: caldata@d0 { + reg = <0x1f8 0x14>; + }; + }; + rng: rng@e3000 { compatible = "qcom,prng-ee"; reg = <0x000e3000 0x1000>; @@ -266,6 +276,16 @@ clock-names = "core"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; + reg = <0x004a9000 0x1000>, /* TM */ + <0x004a8000 0x1000>; /* SROT */ + nvmem-cells = <&tsens_caldata>; + nvmem-cell-names = "calib"; + #qcom,sensors = <10>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,qcs404-pinctrl"; reg = <0x01000000 0x200000>, From patchwork Wed Mar 20 13:18:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 160689 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp283489jan; Wed, 20 Mar 2019 06:20:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqwPysLTHrxQJ2e79FskKgwdkg7AXC/qTxj0J5R9ZXY0HWFxRyBPcJmS/wR++/0ZOntHlnZB X-Received: by 2002:a17:902:9a43:: with SMTP id x3mr8418952plv.173.1553088003417; Wed, 20 Mar 2019 06:20:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1553088003; cv=none; d=google.com; s=arc-20160816; b=M4A8xeSPj9wL2hxZDs6T7dU/rAPxPc3fVcPYHRlPT1iC5X2LkgWxTYVDV7x7MbnsqI rpK8PlZvvVLL1JEbwBz7amADQrcP3u3ZKa/AtcFFAgRi/1UskdaOEupLN1u52qxFMhTd GQcQtbWtA4uUUooWZfUsOJMwrcrycaayKmscfS7O4fTnj3mR0JiI8eLjEBJevS1FBZFu cCabyvjqepvsQC7fzVCWdDSzKV9k9MJ/GkCXI+jqghw7N+Bajoqyi0J9WeHt37F4MkEE S3fExQDuAUVAxlrGcXJB8tnt060XOEvZnXjkMgF7RpZLIGeXoH6KwPk1ononur8Lcfip WVtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=dPQlQtT/j9T5YpFHSehlrM49UmBNUmuq32Pii701NPg=; b=yKLI3mEhHCbBGAiNcnzSXS2g6FX6vWHpPRWukIe34EnmxOTfpNZLCouqDvX+sHnPup YiNTmvSmnn1igEr7U7892bnzWtl2FRwMo8OrLtI71INOJMoENJ4Qg6mcQgjiMG3fBeAw LPXj67kn4ImpKOOISI8XIbqJrs8z9MO8cDTetqtDEwAfzy8vcCWKm7nwSaDTXUjEsyTx jZcBtFpHuQ3gGJxZr6mzA03xW2a1mCJ8AMRNWIjjINA/7BCkYcsHca10sisM+AJYJ5bo G6OaQI6fzigaPuNBiyKhtF1vriDom8fnSJyE7i9CwfyvlaEUi047b9Dubna75WBBXlaT OoiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QLZYDg58; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 38si1709949pgn.121.2019.03.20.06.20.03; Wed, 20 Mar 2019 06:20:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QLZYDg58; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728401AbfCTNUC (ORCPT + 31 others); Wed, 20 Mar 2019 09:20:02 -0400 Received: from mail-pg1-f193.google.com ([209.85.215.193]:46877 "EHLO mail-pg1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728389AbfCTNUA (ORCPT ); Wed, 20 Mar 2019 09:20:00 -0400 Received: by mail-pg1-f193.google.com with SMTP id a22so1768596pgg.13 for ; Wed, 20 Mar 2019 06:19:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=dPQlQtT/j9T5YpFHSehlrM49UmBNUmuq32Pii701NPg=; b=QLZYDg58UjHZ0TEs7Ha3AABd3N5NZGf9nxLdbW+xX7DM/B31QBg2gLWmhJX7JImtCg NGKsnoGoRWj6pk2Li4qxQzy4K8jeg+OsMXQ2On3oBHnf89lWk0iHauEWWMZAavukXJKq 5aJUd1DSm2x4MKvo8VSWiWaCelcnMOGN4BAWi5t16PlJs0iTE4kFetNBmrXBax5BF9l2 Uw0i56inAvVi/Xs4Shj54ej2DR02OjXiS6DsDUm/R8Ln3+qQmyehwaRg0EzF2zlRXWw5 bwKeL9U7xNtZMxzd13TwYhTXWf1aIG1dflZayIndJxcmfoNpQQKCo4WJ37jIqEWbxlhR zBtw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=dPQlQtT/j9T5YpFHSehlrM49UmBNUmuq32Pii701NPg=; b=bV5Z7aikv6j7HDSVUtOfkgQwbnhwnFxQT6D9P4X7eSvGyNc5KhsCs2VV1HwSUakbs+ R8nvuASVXxCbgKAye0um4Isd62NiNZDXIWqXLGDx8peDISgxBireWmsJS2istz4M535z 7BMQ7AAhLY82sFv4fg2PzE5Wh81waC7cMq0isxDq85lQsqYtZW1S08KB5rJi0pNDGM3R Q0EbWLgfCN3L6d2tUvgiz7r7A1/lcCyQL971dnNlp+J950CB14UC6ZudsnBH8pbA1Qi7 LZglnAjxgO2PFZlli+SeCNxV6f/TPLnqBoB03lF+Noa4mgowjDrw9OaMO8Aoj/QBfidR ia1Q== X-Gm-Message-State: APjAAAXy4njZ03SDJxLDeXi34JYSV5bz8crwbrQCaWSgnAR+ZuU7xuWP ufbsCJ9uj1sDwMFoXyqt73hIIYiWILU= X-Received: by 2002:a17:902:266:: with SMTP id 93mr8087338plc.161.1553087999258; Wed, 20 Mar 2019 06:19:59 -0700 (PDT) Received: from localhost ([114.143.122.221]) by smtp.gmail.com with ESMTPSA id k72sm6012896pfb.122.2019.03.20.06.19.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 20 Mar 2019 06:19:58 -0700 (PDT) From: Amit Kucheria To: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org, edubezval@gmail.com, andy.gross@linaro.org, Daniel Lezcano , David Brown , Zhang Rui Cc: devicetree@vger.kernel.org Subject: [PATCHv3 22/23] arm64: dts: qcom: qcs404: Add thermal zones for each sensor Date: Wed, 20 Mar 2019 18:48:02 +0530 Message-Id: X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org qcs404 has 10 sensors connected to the single TSENS IP. Define a thermal zone for each of those sensors to expose the temperature of each zone. Signed-off-by: Amit Kucheria --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 252 +++++++++++++++++++++++++++ 1 file changed, 252 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 7881792980b8..2423c816b98d 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -31,6 +32,7 @@ reg = <0x100>; enable-method = "psci"; next-level-cache = <&L2_0>; + #cooling-cells= <2>; }; CPU1: cpu@101 { @@ -39,6 +41,7 @@ reg = <0x101>; enable-method = "psci"; next-level-cache = <&L2_0>; + #cooling-cells= <2>; }; CPU2: cpu@102 { @@ -47,6 +50,7 @@ reg = <0x102>; enable-method = "psci"; next-level-cache = <&L2_0>; + #cooling-cells= <2>; }; CPU3: cpu@103 { @@ -55,6 +59,7 @@ reg = <0x103>; enable-method = "psci"; next-level-cache = <&L2_0>; + #cooling-cells= <2>; }; L2_0: l2-cache { @@ -866,4 +871,251 @@ #interrupt-cells = <2>; }; }; + + thermal-zones { + aoss-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 0>; + + trips { + aoss_alert0: trip-point@0 { + temperature = <105000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + q6-hvx-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 1>; + + trips { + q6_hvx_alert0: trip-point@0 { + temperature = <105000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + lpass-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 2>; + + trips { + lpass_alert0: trip-point@0 { + temperature = <105000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + wlan-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 3>; + + trips { + wlan_alert0: trip-point@0 { + temperature = <105000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + + cluster-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 4>; + + trips { + cluster_alert0: trip-point@0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + cluster_alert1: trip-point@1 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + cluster_crit: cluster_crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cluster_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu0_alert0: trip-point@0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu0_alert1: trip-point@1 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu0_crit: cpu_crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu0_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + + trips { + cpu1_alert0: trip-point@0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu1_alert1: trip-point@1 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu1_crit: cpu_crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu1_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + cpu2_alert0: trip-point@0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu2_alert1: trip-point@1 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu2_crit: cpu_crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu2_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + cpu3_alert0: trip-point@0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + cpu3_alert1: trip-point@1 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu3_crit: cpu_crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&cpu3_alert1>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + + gpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 9>; + + trips { + gpu_alert0: trip-point@0 { + temperature = <95000>; + hysteresis = <2000>; + type = "hot"; + }; + }; + }; + }; }; From patchwork Wed Mar 20 13:18:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kucheria X-Patchwork-Id: 160690 Delivered-To: patch@linaro.org Received: by 2002:a02:c6d8:0:0:0:0:0 with SMTP id r24csp283592jan; Wed, 20 Mar 2019 06:20:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqzGSXkfNmvAcUrafoVkCHswOv0kfw0bOO8XKYk1XwOjBxoy63cYaPKnwBxwS0xBBxRg3UUG X-Received: by 2002:a17:902:56a:: with SMTP id 97mr8110805plf.320.1553088008418; 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Signed-off-by: Amit Kucheria --- drivers/thermal/qcom/tsens-common.c | 5 ----- drivers/thermal/qcom/tsens.h | 5 +++++ 2 files changed, 5 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/thermal/qcom/tsens-common.c b/drivers/thermal/qcom/tsens-common.c index 92747ccb2850..928e8e81ba69 100644 --- a/drivers/thermal/qcom/tsens-common.c +++ b/drivers/thermal/qcom/tsens-common.c @@ -12,11 +12,6 @@ #include #include "tsens.h" -#define CAL_DEGC_PT1 30 -#define CAL_DEGC_PT2 120 -#define SLOPE_FACTOR 1000 -#define SLOPE_DEFAULT 3200 - char *qfprom_read(struct device *dev, const char *cname) { struct nvmem_cell *cell; diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index d648fba235cf..eefe3844fb4e 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -9,6 +9,11 @@ #define ONE_PT_CALIB 0x1 #define ONE_PT_CALIB2 0x2 #define TWO_PT_CALIB 0x3 +#define CAL_DEGC_PT1 30 +#define CAL_DEGC_PT2 120 +#define SLOPE_FACTOR 1000 +#define SLOPE_DEFAULT 3200 + #include #include