From patchwork Wed Nov 23 18:31:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 628101 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9591EC433FE for ; Wed, 23 Nov 2022 18:33:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239670AbiKWSds (ORCPT ); Wed, 23 Nov 2022 13:33:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34468 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239673AbiKWSdI (ORCPT ); Wed, 23 Nov 2022 13:33:08 -0500 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CDC07627E for ; Wed, 23 Nov 2022 10:32:52 -0800 (PST) Received: by mail-pl1-x636.google.com with SMTP id w23so17374524ply.12 for ; Wed, 23 Nov 2022 10:32:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QH40xdstEqWGzwJenNT3rCqkfJ9ajN5rIUi4+/Qwboo=; b=JrFdo9zzSZq4vcjaRKG7bUw2d1ykyBu3DmR5uM6AoS+kqrWKKR0uFmlc4c7lXispzd kFkiPLTW3txvogFwPDRXz8P6DOUXh5m0ICVY8h9AN1Iy1OcessiYG1rL+sLgIZOekjTB 7D6rtGJ8fVUdxvzJqhK+uAj9Muon9ZZEMU1aNjcspSZAstB4EgbeI5QQy4n9x+oMpinL jwVJBHIlwK2bpelndwekvu8+SplY++A5Ug8+Fl397z12i7M1A7yDdIVzLARJsnL4DOGc rXbv1tYpQnJJddseV4Jxn2l029mg0S1ZnkqEiPk593Z9AUqNtvHXQdTu24TVK3fK747f Yxaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QH40xdstEqWGzwJenNT3rCqkfJ9ajN5rIUi4+/Qwboo=; b=JWhcBnu/4AJ3GmCxHzemFvIWGJ/TMf3u0Lww67Kw059cMvR1SSdQp+LVfauhehmsiu QHZv3+HUgd7O80UaD0ixv/WC7YsITJRHSffIDLCaD3mNjxMI0tKyPXqwvLt63Th1IhoJ GlhUMSVrRkDuRa4J4jhYfFr3xS30gNZ9rQNpYE7+k9W6pDbjtbUsgBuB2rAN5MlZl+uB hWpI1Pmv0Na3RWlA5DIQ3xElACoqa4gBrpBwWMdnSI15CUTbNOyXtD/4N6a7zJpO6FtM yx6Csh9VmPwUmjsB/eC9udTRFhUPO9lqm1u73EZs1YakUDT1B9PFdb9DK6dBk0phRf/5 wlTw== X-Gm-Message-State: ANoB5pklovIYHdSkumDohhUF0EKTgyZY7YYesIji1It6cGtBHWJ0QeeD YmAhRigfkD4z1WJY91KLlzMt7A== X-Google-Smtp-Source: AA0mqf4pLxcJq9p7xF2+hlaeWUITQBV/rTFCR2so3rNYWpE+TbroSTO+lGHvi5XnoOSkv/PMshemTg== X-Received: by 2002:a17:90a:1bc2:b0:218:8bdb:de3f with SMTP id r2-20020a17090a1bc200b002188bdbde3fmr24941981pjr.225.1669228372327; Wed, 23 Nov 2022 10:32:52 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a809:a055:fcc4:4677:827]) by smtp.gmail.com with ESMTPSA id x3-20020aa79403000000b0056d2317455bsm13006732pfo.7.2022.11.23.10.32.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 10:32:51 -0800 (PST) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski Cc: Daniel Lezcano , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Johan Jonker , Jagan Teki Subject: [PATCH v8 2/8] dt-bindings: timer: rk-timer: Add rktimer for rv1126 Date: Thu, 24 Nov 2022 00:01:18 +0530 Message-Id: <20221123183124.6911-3-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123183124.6911-1-jagan@edgeble.ai> References: <20221123183124.6911-1-jagan@edgeble.ai> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add rockchip timer compatible string for rockchip rv1126. Signed-off-by: Jagan Teki --- Changes for v8: - drop cc list Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml index dc3bc1e62fe9..a6221222e948 100644 --- a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml +++ b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml @@ -17,6 +17,7 @@ properties: - items: - enum: - rockchip,rv1108-timer + - rockchip,rv1126-timer - rockchip,rk3036-timer - rockchip,rk3188-timer - rockchip,rk3228-timer From patchwork Wed Nov 23 18:31:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 628100 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B43CC433FE for ; Wed, 23 Nov 2022 18:33:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239839AbiKWSd4 (ORCPT ); Wed, 23 Nov 2022 13:33:56 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239757AbiKWSdT (ORCPT ); Wed, 23 Nov 2022 13:33:19 -0500 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B64A6069F for ; Wed, 23 Nov 2022 10:33:01 -0800 (PST) Received: by mail-pf1-x435.google.com with SMTP id 140so18105666pfz.6 for ; Wed, 23 Nov 2022 10:33:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lMcMz4lhTbYSnL4IrpNum4EJaPaF6oOxPzEpaG2dE7U=; b=RzP+DEdeYgyxuILcflyFxdmNMvmVIgEU79rd5mwcIKRxVW5CUeQeiyq901tnYuF3On 8PmbtrDXxJb9ebyi/4orWUMVdOHg7NLcwUO1j2pHeystdORlMTRzTFzICC46wEdKfNJZ AxhyoXoy4FVm/iujljX/ZEaIZifSbPtku/0j3LkMijFaKDEHpVAY3WEUE0zzrG4f9s2E vtDnJp+c4G2O3lnGLIYMsAH6NXUqoQvtsojdT+Uf3q1vO1ma43wfw4IIVaFJK1OJaDcO LtEzah4wQmooxBtDYypC3K+VllCgempBiWDqITAGPfuXSTSGDsZHj/y3OxOs0eH8I2K2 S8TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lMcMz4lhTbYSnL4IrpNum4EJaPaF6oOxPzEpaG2dE7U=; b=WY+SKmaBU2uE81fqJb32vLOiCTTGw06lwDKmtw8fxcDJpZ4ghXPmvqulrDQhYO0q5C bS3Uw5ctOeVAWFIbxIWAZ+kO+oVQTOooymw46QwJyv7DGCqjDTak6X/Qp2ISZS4j9YUF TlppqCA6lvBs75NsavxZeazMbfKvOj9PydbLS1rc0iur4Fx89GpXvkBzoQihcpR8e9+O 4kbS8OV5cT0fcIHrJ4xLfxdqJSdI0w1T5VVcWxshhJRfowYnHkJQH3S30XSdFCAB+51F Xn0UF8mX7LPyTelQQ+MqTSH2yoS/OtasW9lvNjSaKF74cYmSaTLsr9W9l24WcHmZfqjv 8+ag== X-Gm-Message-State: ANoB5plJBBRscBueriKtPf/wIaLEwxGoHhgBubUGA5pThYyMM+MGiMw4 RlISDU/GPoszvxXPkXkule+nRQ== X-Google-Smtp-Source: AA0mqf6RW7pNSIF/I27WQsO7L6AhhmE2S12uhpHpMvcPF/qQrUcrclF2MKb4/KRclsp7HbVyJGj+aQ== X-Received: by 2002:a62:1e03:0:b0:56b:d68e:41f6 with SMTP id e3-20020a621e03000000b0056bd68e41f6mr31284050pfe.36.1669228380767; Wed, 23 Nov 2022 10:33:00 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a809:a055:fcc4:4677:827]) by smtp.gmail.com with ESMTPSA id x3-20020aa79403000000b0056d2317455bsm13006732pfo.7.2022.11.23.10.32.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 10:33:00 -0800 (PST) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski Cc: Daniel Lezcano , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Johan Jonker , Jagan Teki , Jon Lin , Sugar Zhang Subject: [PATCH v8 4/8] ARM: dts: rockchip: Add Rockchip RV1126 SoC Date: Thu, 24 Nov 2022 00:01:20 +0530 Message-Id: <20221123183124.6911-5-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123183124.6911-1-jagan@edgeble.ai> References: <20221123183124.6911-1-jagan@edgeble.ai> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org RV1126 is a high-performance vision processor SoC for IPC/CVR, especially for AI related application. It is based on quad-core ARM Cortex-A7 32-bit core which integrates NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16 hybrid operation and computing power is up to 2.0TOPs. This patch add basic core dtsi support. Signed-off-by: Jon Lin Signed-off-by: Sugar Zhang Signed-off-by: Jagan Teki --- Changes for v8: - fix rv1126 dtsi - remove uart aliases - add adc node name - add uart dma-names - add timer0 node name Changes for v7: - fix dtbs_check - rearrange nodes - remove Edegble in license text Changes for v6: - add psci node Changes for v5: - none Changes for v4: - update i2c0 - rebase on -next Changes for v3: - update cru and power file names Changes for v2: - split pinctrl in separate patch arch/arm/boot/dts/rv1126.dtsi | 438 ++++++++++++++++++++++++++++++++++ 1 file changed, 438 insertions(+) create mode 100644 arch/arm/boot/dts/rv1126.dtsi diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi new file mode 100644 index 000000000000..1cb43147e90b --- /dev/null +++ b/arch/arm/boot/dts/rv1126.dtsi @@ -0,0 +1,438 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rv1126"; + + interrupt-parent = <&gic>; + + aliases { + i2c0 = &i2c0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu2: cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu3: cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + grf: syscon@fe000000 { + compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; + reg = <0xfe000000 0x20000>; + }; + + pmugrf: syscon@fe020000 { + compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; + reg = <0xfe020000 0x1000>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rv1126-pmu-io-voltage-domain"; + status = "disabled"; + }; + }; + + qos_emmc: qos@fe860000 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860000 0x20>; + }; + + qos_nandc: qos@fe860080 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860080 0x20>; + }; + + qos_sfc: qos@fe860200 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860200 0x20>; + }; + + qos_sdio: qos@fe86c000 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe86c000 0x20>; + }; + + gic: interrupt-controller@feff0000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0xfeff1000 0x1000>, + <0xfeff2000 0x2000>, + <0xfeff4000 0x2000>, + <0xfeff6000 0x2000>; + interrupts = ; + }; + + pmu: power-management@ff3e0000 { + compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; + reg = <0xff3e0000 0x1000>; + + power: power-controller { + compatible = "rockchip,rv1126-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RV1126_PD_NVM { + reg = ; + clocks = <&cru HCLK_EMMC>, + <&cru CLK_EMMC>, + <&cru HCLK_NANDC>, + <&cru CLK_NANDC>, + <&cru HCLK_SFC>, + <&cru HCLK_SFCXIP>, + <&cru SCLK_SFC>; + pm_qos = <&qos_emmc>, + <&qos_nandc>, + <&qos_sfc>; + #power-domain-cells = <0>; + }; + + power-domain@RV1126_PD_SDIO { + reg = ; + clocks = <&cru HCLK_SDIO>, + <&cru CLK_SDIO>; + pm_qos = <&qos_sdio>; + #power-domain-cells = <0>; + }; + }; + }; + + i2c0: i2c@ff3f0000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff3f0000 0x1000>; + interrupts = ; + rockchip,grf = <&pmugrf>; + clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart1: serial@ff410000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff410000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 7>, <&dmac 6>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + pmucru: clock-controller@ff480000 { + compatible = "rockchip,rv1126-pmucru"; + reg = <0xff480000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@ff490000 { + compatible = "rockchip,rv1126-cru"; + reg = <0xff490000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dmac: dma-controller@ff4e0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xff4e0000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + + uart0: serial@ff560000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff560000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 5>, <&dmac 4>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@ff570000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff570000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 9>, <&dmac 8>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@ff580000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff580000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 11>, <&dmac 10>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@ff590000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff590000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 13>, <&dmac 12>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart5: serial@ff5a0000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff5a0000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 15>, <&dmac 14>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + saradc: adc@ff5e0000 { + compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc"; + reg = <0xff5e0000 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC_P>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + timer0: timer@ff660000 { + compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer"; + reg = <0xff660000 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; + clock-names = "pclk", "timer"; + }; + + emmc: mmc@ffc50000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc50000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + power-domains = <&power RV1126_PD_NVM>; + status = "disabled"; + }; + + sdmmc: mmc@ffc60000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc60000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + status = "disabled"; + }; + + sdio: mmc@ffc70000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc70000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + power-domains = <&power RV1126_PD_SDIO>; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rv1126-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@ff460000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff460000 0x100>; + interrupts = ; + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ff620000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff620000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ff630000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff630000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ff640000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff640000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ff650000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff650000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rv1126-pinctrl.dtsi" From patchwork Wed Nov 23 18:31:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 628099 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B4C9C4332F for ; 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Wed, 23 Nov 2022 10:33:09 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a809:a055:fcc4:4677:827]) by smtp.gmail.com with ESMTPSA id x3-20020aa79403000000b0056d2317455bsm13006732pfo.7.2022.11.23.10.33.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 10:33:09 -0800 (PST) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski Cc: Daniel Lezcano , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Johan Jonker , Jagan Teki , Rob Herring Subject: [PATCH v8 6/8] dt-bindings: arm: rockchip: Add Edgeble Neural Compute Module 2 Date: Thu, 24 Nov 2022 00:01:22 +0530 Message-Id: <20221123183124.6911-7-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123183124.6911-1-jagan@edgeble.ai> References: <20221123183124.6911-1-jagan@edgeble.ai> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module based on Rockchip RV1126 from Edgeble AI. Edgeble Neural Compute Module 2(Neu2) IO board is an industrial form factor evaluation board from Edgeble AI. Neu2 needs to mount on top of this IO board in order to create complete Edgeble Neural Compute Module 2(Neu2) IO platform. Add dt-bindings for it. Acked-by: Rob Herring Signed-off-by: Jagan Teki --- Changes for v8: - none Changes for v7: - collect Rob Ack Changes for v6: - updated SOM and Carrier name Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 244c42eaae8c..26fdd205a899 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -85,6 +85,12 @@ properties: - const: chipspark,rayeager-px2 - const: rockchip,rk3066a + - description: Edgeble Neural Compute Module 2(Neu2) SoM based boards + items: + - const: edgeble,neural-compute-module-2-io # Edgeble Neural Compute Module 2 IO Board + - const: edgeble,neural-compute-module-2 # Edgeble Neural Compute Module 2 SoM + - const: rockchip,rv1126 + - description: Elgin RV1108 R1 items: - const: elgin,rv1108-r1 From patchwork Wed Nov 23 18:31:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 628098 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 428AFC433FE for ; Wed, 23 Nov 2022 18:34:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239349AbiKWSeM (ORCPT ); Wed, 23 Nov 2022 13:34:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239793AbiKWSdp (ORCPT ); Wed, 23 Nov 2022 13:33:45 -0500 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47C3C21A1 for ; Wed, 23 Nov 2022 10:33:23 -0800 (PST) Received: by mail-pj1-x1033.google.com with SMTP id x13-20020a17090a46cd00b00218f611b6e9so972840pjg.1 for ; Wed, 23 Nov 2022 10:33:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=edgeble-ai.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jPbVvPps35d9qSmRicMnyfKxv7RaFTM2lFdzVKFiQc0=; b=GjVa3I9DLIVr/b1xkrqj+nLz/A1pDKu716OKgzMMClvA5VnFJY4vE4V6EAU9AzjiY5 +VqLd2uI5L8J7kqsWIZRIE8lTVzjA3y8pK8gv8UI+0/0WfXemVoMI9KF4LnBQVOoZ1p9 nqM4dbBOyPUoKsx0MtqdUjgG3wXAUoKuFgjyEiPltQKBAtMaQW6tuCCZfNNUoRLbe5Gv YpjjsT4TJh9JAYd6bnCrOehRRJBZQw5fPxwk3/VzDAYajhR6rsQTHs2ZfVFMmvkR/Jkn 2BxFeAOg9P5f9lKtmbfkmwdixVzj+hXcJu9Hh+X2vlAR6gbAs7bGvl1AfJ9oHoIsfOJ6 4g4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jPbVvPps35d9qSmRicMnyfKxv7RaFTM2lFdzVKFiQc0=; b=BmB1dimWfEIaA5x3fGypGJLuDm2GrasXTbTkG88foeDdHQRVJ1vqbWlk/Rk+kE0M3+ o/toyTbThc+I3J0CxH9wWWFFrpZ2TL6DPoCA5IQib6VN2v12p9Mn7se+Rgo14N0fmwcn E84DqLdIPhrmqc2JMgGOfM82KimcaNmOd2nmJohqaaj+bKGpeQDgKBS2LBSEwb6PU/lv tOuOR+naT9SxY2fYGfl5WOSthF/xx7dJ0yrf87ISkyxPM0AsDQkIxhF07MOdKUm6sMMT Ij4CVW7SLX3F9Z9O+RlwOVvYZ3wsumseR7w8OWgqSA9oV+t1XsG6vfiNYabWLxcJZ3JT T4kg== X-Gm-Message-State: ANoB5pm31J056jOnkMxgVftXzYwB5JWa9qFyIL+nKl8bkCUVlqT41bEj y+kJ5AKxSV0YMukVN/Y4Jq2F4g== X-Google-Smtp-Source: AA0mqf7dAPWZzf40dx3d0O3bkXKMBgurnduSmGOZHlNfm/ahurULbBuk5/AdotG3WbK7zhruBkWH6Q== X-Received: by 2002:a17:90a:5918:b0:213:ff:1cda with SMTP id k24-20020a17090a591800b0021300ff1cdamr30955608pji.86.1669228402771; Wed, 23 Nov 2022 10:33:22 -0800 (PST) Received: from localhost.localdomain ([2405:201:c00a:a809:a055:fcc4:4677:827]) by smtp.gmail.com with ESMTPSA id x3-20020aa79403000000b0056d2317455bsm13006732pfo.7.2022.11.23.10.33.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 10:33:21 -0800 (PST) From: Jagan Teki To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski Cc: Daniel Lezcano , linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, Johan Jonker , Jagan Teki Subject: [PATCH v8 8/8] ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) IO Date: Thu, 24 Nov 2022 00:01:24 +0530 Message-Id: <20221123183124.6911-9-jagan@edgeble.ai> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221123183124.6911-1-jagan@edgeble.ai> References: <20221123183124.6911-1-jagan@edgeble.ai> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Neural Compute Module 2(Neu2) IO board is an industrial form factor evaluation board from Edgeble AI. General features: - microSD slot - MIPI DSI connector - 2x USB Host - 1x USB OTG - Ethernet - mini PCIe - Onboard PoE - RS485, RS232, CAN - Micro Phone array - Speaker - RTC battery slot - 40-pin expansion Neu2 needs to mount on top of this IO board in order to create complete Edgeble Neural Compute Module 2(Neu2) IO platform. Add support for it. Signed-off-by: Jagan Teki --- Changes for v8, v7: - none Changes for v6: - update the carrier name. arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts | 38 ++++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e48cfbc4e8e4..40cc34bd4945 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1122,6 +1122,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1108-elgin-r1.dtb \ rv1108-evb.dtb \ + rv1126-edgeble-neu2-io.dtb \ rk3036-evb.dtb \ rk3036-kylin.dtb \ rk3066a-bqcurie2.dtb \ diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts new file mode 100644 index 000000000000..ae1cf344239b --- /dev/null +++ b/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +/dts-v1/; +#include "rv1126.dtsi" +#include "rv1126-edgeble-neu2.dtsi" + +/ { + model = "Edgeble Neu2 IO Board"; + compatible = "edgeble,neural-compute-module-2-io", + "edgeble,neural-compute-module-2", "rockchip,rv1126"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +};