From patchwork Wed Nov 23 21:03:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 628095 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95DDDC47088 for ; Wed, 23 Nov 2022 21:04:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236761AbiKWVEJ (ORCPT ); Wed, 23 Nov 2022 16:04:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237068AbiKWVEI (ORCPT ); Wed, 23 Nov 2022 16:04:08 -0500 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D3EC2936F for ; Wed, 23 Nov 2022 13:04:06 -0800 (PST) Received: by mail-lf1-x133.google.com with SMTP id bp15so29897012lfb.13 for ; Wed, 23 Nov 2022 13:04:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lCL3T9bEBAWFKFNPkwgPngR7HtM0awS/KY1SN8cp/IM=; b=CcfVE3CIpdAWl1OIoYlRZr5tYRkW7hRYRidaps7uH5itebTaEbFJrVM/WIhEU4Wo33 DLIHRYikT2WIfr/M39P7x3n3LjmvPzPHWFd0o+xA+8X+7a64TEA/bOx0uwFT8ZtFyUsC 4wC13/frNdbuvZHflqW4u859QMvZUUURvuU3p8iv3GCBZEQE0ruvIGVniZu8EF0Wut1X k8DefauYVTqPV8vSjbwD/2q9xcZ2qf/aZpOzdaNUpBII3ZlGZRV+BopemUh7OdyvD7sv QzHee5hRHRJzw1xhWnSwyehX9k2myuTInMr5iTMaxg1Su5pbWryhW+IBPm7t+sGyo5QO 53bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lCL3T9bEBAWFKFNPkwgPngR7HtM0awS/KY1SN8cp/IM=; b=Q0IPMzazxL+TzXoCrhfXF3uxfP1lh3ItFbrkJ7ds2EnYRWLtkMGoNYcc3FwHPwuWDw oRK2J3yI7wQetC8ZKVe8Xu4g3XgKJ2DcuMh1K1D3YBV7N+9sGmXBYTKNKRjY3mX66P8L /ERmDAAHlYlQn4FOuJSrVKG/XqS+2pUIdb0snEsFy+HYTd1IWjd80jx1l5YK3w6lE8d4 +MX+q9Q3lONXs3op8r5/AJ4rqpfgbCuM/ZJ1UXobnuKbzTtvBlDp6MdqVo8GexFB5yGA WW26NNf7lbmNe1Xuk43vmiRAfZI9FSu/j9LTUOPwREzCRijDDGODxDRBkGpzZEfp8D6Z VaMg== X-Gm-Message-State: ANoB5pnpwWKPCQZk0SOg+hJu2bwquTllSd2JHlrRW000pImEe214jO/R hOuP2OqyWg0uMqsAUADZb4dLew== X-Google-Smtp-Source: AA0mqf6Mv9u0bqEHtoER2ms/qAfzGkxZGhZjC3FjxRCF6ns0Of+1EoEc4mCYC/42cBfhn5mbMmE9pg== X-Received: by 2002:a05:6512:750:b0:4b0:a1e7:9160 with SMTP id c16-20020a056512075000b004b0a1e79160mr9404127lfs.566.1669237444954; Wed, 23 Nov 2022 13:04:04 -0800 (PST) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id c3-20020ac25f63000000b004b177293a8dsm3009913lfc.210.2022.11.23.13.04.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 13:04:04 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski Subject: [PATCH v5 01/10] dt-bindings: display/msm: *dpu.yaml: split required properties clauses Date: Wed, 23 Nov 2022 23:03:54 +0200 Message-Id: <20221123210403.3593366-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221123210403.3593366-1-dmitry.baryshkov@linaro.org> References: <20221123210403.3593366-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Require only properties declared in given schema, which makes the code a bit more readable and easy to follow. Suggested-by: Krzysztof Kozlowski Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/display/msm/dpu-common.yaml | 4 ---- .../devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml | 7 +++++++ .../devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml | 7 +++++++ .../devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml | 7 +++++++ .../devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml | 7 +++++++ .../devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml | 7 +++++++ .../devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml | 7 +++++++ 7 files changed, 42 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dpu-common.yaml b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml index 8ffbc30c6b7f..870158bb2aa0 100644 --- a/Documentation/devicetree/bindings/display/msm/dpu-common.yaml +++ b/Documentation/devicetree/bindings/display/msm/dpu-common.yaml @@ -40,10 +40,6 @@ properties: - port@0 required: - - compatible - - reg - - reg-names - - clocks - interrupts - power-domains - operating-points-v2 diff --git a/Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml index b02adba36e9e..479ce75bd451 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,msm8998-dpu.yaml @@ -46,6 +46,13 @@ properties: - const: core - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml index a7b382f01b56..e794f0dd8ef4 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml @@ -42,6 +42,13 @@ properties: - const: lut - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml index bd590a6b5b96..0dfdf8f3c5b4 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7180-dpu.yaml @@ -44,6 +44,13 @@ properties: - const: core - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml index 924059b387b6..512d23f8d629 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-dpu.yaml @@ -43,6 +43,13 @@ properties: - const: core - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml index 5719b45f2860..d5a55e898b11 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sdm845-dpu.yaml @@ -42,6 +42,13 @@ properties: - const: core - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml index 9ff8a265c85f..687c8c170cd4 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml @@ -39,6 +39,13 @@ properties: - const: core - const: vsync +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + unevaluatedProperties: false examples: From patchwork Wed Nov 23 21:03:56 2022 Content-Type: text/plain; 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Wed, 23 Nov 2022 13:04:06 -0800 (PST) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id c3-20020ac25f63000000b004b177293a8dsm3009913lfc.210.2022.11.23.13.04.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 13:04:06 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Krzysztof Kozlowski Subject: [PATCH v5 03/10] dt-bindings: display/msm: add sm8350 and sm8450 DSI PHYs Date: Wed, 23 Nov 2022 23:03:56 +0200 Message-Id: <20221123210403.3593366-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221123210403.3593366-1-dmitry.baryshkov@linaro.org> References: <20221123210403.3593366-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SM8350 and SM8450 platforms use the same driver and same bindings as the existing 7nm DSI PHYs. Add corresponding compatibility strings. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index c851770bbdf2..bffd161fedfd 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -15,6 +15,8 @@ allOf: properties: compatible: enum: + - qcom,dsi-phy-5nm-8350 + - qcom,dsi-phy-5nm-8450 - qcom,dsi-phy-7nm - qcom,dsi-phy-7nm-8150 - qcom,sc7280-dsi-phy-7nm From patchwork Wed Nov 23 21:03:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 628093 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0A2AC3A59F for ; Wed, 23 Nov 2022 21:04:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237370AbiKWVE1 (ORCPT ); Wed, 23 Nov 2022 16:04:27 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56842 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237443AbiKWVEQ (ORCPT ); Wed, 23 Nov 2022 16:04:16 -0500 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69D4797A99 for ; Wed, 23 Nov 2022 13:04:10 -0800 (PST) Received: by mail-lf1-x12b.google.com with SMTP id g7so29972824lfv.5 for ; Wed, 23 Nov 2022 13:04:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JzVHcmxorROJCIoZd11bHlIHsRKO6twZzQN8g754tbQ=; b=nFaNPBxwoQUeOP54oU2tx6S9FR7YelHx27WEFXWu2cHhEid2Uc+Dxs1Im0f0A6qLhl sKMtqk5GecHvGjBexFvK7oDz0oJlu9pORO9xa2unYAwyIWmz4jx867vEtVRRrHXIKqp4 UFwdlz7HyN1R8H2RXlgA/SyW51ZAEtWcwqY6sewz9ldQiCIEFhfYAJZhhneaWCuffTAZ v4p5zJyGML4Khdam1NG0nQ04lI2x2jyb5Ctj6MiGtlJ2vDiNPhHWQQMZy/c++No860es aVMUM+QSyII+z7hIvIToiHE19Xz+4wAhxYdtBCMlu/2pEeqAjljFICejlxajxaMU6CRI mZRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JzVHcmxorROJCIoZd11bHlIHsRKO6twZzQN8g754tbQ=; b=nuSfYfX6S73s0FacKKBoUojKZkxb6o0ipxXztF5Y9etY7VhyVnxFqylmiC+naSEosa 6tTQtNiZN4HkHt7r6+BuZ3PFC7uCVst8600qPfhFiRWwKaDexTTewm/joQnlpFX6zw4z DUr1W64/H/S9Wu17IBelYU6xnLGv+eFZukUMFZYRjl7BBI8Z4M5P3d+LQkQMLvlnE1Ew R7zK4GRKI9QyYp6kyI0qWynER5PO5hxafscXYVOMveq1SUIM1Pw4F2iNZht+wO/Ahg+o gbrlpJavQY6LQbS8q373RizdqCKcEAHV1+9bSRMjQeAUQ+jXYPGsYExCMPpIAT1akpdz hOlg== X-Gm-Message-State: ANoB5pnSw/oG9ykX2TxAZszhCnP8IDvO3A7m7+iHYXiItMrdRVYhQ4nj 1Auc0yxmrDuUSZWlXdQY+3Iung== X-Google-Smtp-Source: AA0mqf5fNdtYcM2Pbvb4S8ZwzG7JXBqqwswezEyq8ghCbfoDfxeZv/69Kd5jc2D14MVJ5Qc0yrfZIw== X-Received: by 2002:a19:6b0b:0:b0:4a2:44dc:b70c with SMTP id d11-20020a196b0b000000b004a244dcb70cmr9183696lfa.360.1669237448428; Wed, 23 Nov 2022 13:04:08 -0800 (PST) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id c3-20020ac25f63000000b004b177293a8dsm3009913lfc.210.2022.11.23.13.04.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 13:04:08 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Konrad Dybcio Subject: [PATCH v5 05/10] drm/msm/dsi/phy: rework register setting for 7nm PHY Date: Wed, 23 Nov 2022 23:03:58 +0200 Message-Id: <20221123210403.3593366-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221123210403.3593366-1-dmitry.baryshkov@linaro.org> References: <20221123210403.3593366-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In preparation to adding the sm8350 and sm8450 PHYs support, rearrange register values calculations in dsi_7nm_phy_enable(). This change bears no functional changes itself, it is merely a preparation for the next patch. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 26 +++++++++++------------ 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c index 9e7fa7d88ead..0b780f9d3d0a 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -858,23 +858,34 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, /* Alter PHY configurations if data rate less than 1.5GHZ*/ less_than_1500_mhz = (clk_req->bitclk_rate <= 1500000000); + if (phy->cphy_mode) { + vreg_ctrl_0 = 0x51; + vreg_ctrl_1 = 0x55; + glbl_pemph_ctrl_0 = 0x11; + lane_ctrl0 = 0x17; + } else { + vreg_ctrl_1 = 0x5c; + glbl_pemph_ctrl_0 = 0x00; + lane_ctrl0 = 0x1f; + } + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_1) { - vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; if (phy->cphy_mode) { glbl_rescode_top_ctrl = 0x00; glbl_rescode_bot_ctrl = 0x3c; } else { + vreg_ctrl_0 = less_than_1500_mhz ? 0x53 : 0x52; glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d : 0x00; glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x39 : 0x3c; } glbl_str_swi_cal_sel_ctrl = 0x00; glbl_hstx_str_ctrl_0 = 0x88; } else { - vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; if (phy->cphy_mode) { glbl_str_swi_cal_sel_ctrl = 0x03; glbl_hstx_str_ctrl_0 = 0x66; } else { + vreg_ctrl_0 = less_than_1500_mhz ? 0x5B : 0x59; glbl_str_swi_cal_sel_ctrl = less_than_1500_mhz ? 0x03 : 0x00; glbl_hstx_str_ctrl_0 = less_than_1500_mhz ? 0x66 : 0x88; } @@ -882,17 +893,6 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, glbl_rescode_bot_ctrl = 0x3c; } - if (phy->cphy_mode) { - vreg_ctrl_0 = 0x51; - vreg_ctrl_1 = 0x55; - glbl_pemph_ctrl_0 = 0x11; - lane_ctrl0 = 0x17; - } else { - vreg_ctrl_1 = 0x5c; - glbl_pemph_ctrl_0 = 0x00; - lane_ctrl0 = 0x1f; - } - /* de-assert digital and pll power down */ data = BIT(6) | BIT(5); dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_0, data); From patchwork Wed Nov 23 21:04:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 628092 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A905C4708C for ; Wed, 23 Nov 2022 21:04:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237562AbiKWVEa (ORCPT ); Wed, 23 Nov 2022 16:04:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56836 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237473AbiKWVES (ORCPT ); Wed, 23 Nov 2022 16:04:18 -0500 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F16379825E for ; Wed, 23 Nov 2022 13:04:11 -0800 (PST) Received: by mail-lf1-x12c.google.com with SMTP id f13so8410535lfa.6 for ; Wed, 23 Nov 2022 13:04:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i5Gb3UnijTffvUZ5061n1gC+IjflOu8fq8L5Sow654E=; b=qIxen24U8K5h1/Axh9/h7awJyD7b5j5GQd0C+SmQxJr37O/RwifoaXm5HjdRDKOpYi e3JI54ejKYU/+vrMyTjcGxeeapVHQlGWBUZP4diFzXIXsGeDGv+5DJ8W8PSGMXlOwpvH NCA92vBFQof17kWPch2d/Ji6EhRuGEtP3ja31j/9iY6w73K3o2lYWWX+0pHJ585Y13cv H3FUuV1yllXOu2NNVh5vqNf4BKTGFLqed5d+A3ErX+9kZdrd/pTxqahk4lLz4sIpBiYf gcO6pSObNBmolNfeAbGA2IZJh9GbesbxRoWf8uaeIuWHCkpUhCFRg513kHEBoQCI1rw9 mYeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i5Gb3UnijTffvUZ5061n1gC+IjflOu8fq8L5Sow654E=; b=dVEvZUbhZ4TBYgS3KctMRonhgmsUPgh4Ns+dP+Vq2IgFff679o2FXUgpnX1VsC3lUz HlBtwoxHlFSddEXzItDHPmAZwmz5N4fXidPeo+qhNDt9bG135m1IlgkhrjuDED+lz7aP k+HHdU/Z6FAzarpRM17l5BTZusY/mnuzOfpmElN0rdBjOxOAXu/H2FMjx60e6jOS0lSK bpxHwTvdRnbLG/A38ZA8lmlEBI7F87aLRtWDFeL0rZcu8jfJXUZpQGZKag4aTsW43PKt eRa8UUOC3ttmz3NYnkO2uRGN8/D8TStFaNd8e0HrKvNxTieucC9F4oLT1clMzkW+gW64 B5Vg== X-Gm-Message-State: ANoB5pkLeeQKqRxPQbGqJvILsj9ZjXGruGphD966BhJJe2d4GyMi9UFD 4TN1RkgBxLw7KacQWjaDntxvow== X-Google-Smtp-Source: AA0mqf5jBg7VOIi+svpan2pzqx22MI42d9wHkZtnb2p51nuo9gB9boIGfF5ybyd7oJIRdB6jwawJlw== X-Received: by 2002:a19:4f14:0:b0:4b4:b20c:4b7 with SMTP id d20-20020a194f14000000b004b4b20c04b7mr4503069lfb.201.1669237450335; Wed, 23 Nov 2022 13:04:10 -0800 (PST) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id c3-20020ac25f63000000b004b177293a8dsm3009913lfc.210.2022.11.23.13.04.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 13:04:09 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Vinod Koul , Konrad Dybcio Subject: [PATCH v5 07/10] drm/msm/dsi: add support for DSI 2.6.0 Date: Wed, 23 Nov 2022 23:04:00 +0200 Message-Id: <20221123210403.3593366-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221123210403.3593366-1-dmitry.baryshkov@linaro.org> References: <20221123210403.3593366-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for DSI 2.6.0 (block used on sm8450). Tested-by: Vinod Koul Reviewed-by: Vinod Koul Reviewed-by: Konrad Dybcio Reviewed-by: Abhinav Kumar Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c index 7e97c239ed48..59a4cc95a251 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -300,6 +300,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { &sc7180_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0, &sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0, + &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, }; const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h index 8f04e685a74e..95957fab499d 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -25,6 +25,7 @@ #define MSM_DSI_6G_VER_MINOR_V2_4_0 0x20040000 #define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001 #define MSM_DSI_6G_VER_MINOR_V2_5_0 0x20050000 +#define MSM_DSI_6G_VER_MINOR_V2_6_0 0x20060000 #define MSM_DSI_V2_VER_MINOR_8064 0x0 From patchwork Wed Nov 23 21:04:01 2022 Content-Type: text/plain; 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Wed, 23 Nov 2022 13:04:11 -0800 (PST) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id c3-20020ac25f63000000b004b177293a8dsm3009913lfc.210.2022.11.23.13.04.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 13:04:10 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Vinod Koul , Konrad Dybcio Subject: [PATCH v5 08/10] drm/msm/dpu: add support for MDP_TOP blackhole Date: Wed, 23 Nov 2022 23:04:01 +0200 Message-Id: <20221123210403.3593366-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221123210403.3593366-1-dmitry.baryshkov@linaro.org> References: <20221123210403.3593366-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On sm8450 a register block was removed from MDP TOP. Accessing it during snapshotting results in NoC errors / immediate reboot. Skip accessing these registers during snapshot. Tested-by: Vinod Koul Reviewed-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 11 +++++++++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 38aa38ab1568..8da4c5ba6dc3 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -82,6 +82,8 @@ enum { * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth * compression initial revision * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 + * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results + * in a failure * @DPU_MDP_MAX Maximum value */ @@ -92,6 +94,7 @@ enum { DPU_MDP_UBWC_1_0, DPU_MDP_UBWC_1_5, DPU_MDP_AUDIO_SELECT, + DPU_MDP_PERIPH_0_REMOVED, DPU_MDP_MAX }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index f3660cd14f4f..4ac14de55139 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -927,8 +927,15 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, - dpu_kms->mmio + cat->mdp[0].base, "top"); + if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { + msm_disp_snapshot_add_block(disp_state, 0x380, + dpu_kms->mmio + cat->mdp[0].base, "top"); + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - 0x3a8, + dpu_kms->mmio + cat->mdp[0].base + 0x3a8, "top_2"); + } else { + msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, + dpu_kms->mmio + cat->mdp[0].base, "top"); + } pm_runtime_put_sync(&dpu_kms->pdev->dev); }