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[2001:14ba:a302:5f12::1]) by smtp.gmail.com with ESMTPSA id be34-20020a056512252200b0049e9122bd1bsm2869082lfb.164.2022.11.23.02.44.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 02:44:45 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: Johan Hovold , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v9 1/4] dt-bindings: phy: qcom, *-qmp-ufs-phy: add clock-cells property Date: Wed, 23 Nov 2022 12:44:40 +0200 Message-Id: <20221123104443.3415267-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221123104443.3415267-1-dmitry.baryshkov@linaro.org> References: <20221123104443.3415267-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add #clock-cells property to the QMP UFS PHYs to describe them as clock providers. The QMP PHY provides rx and tx symbol clocks for the GCC. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml | 3 +++ .../devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 3 +++ 2 files changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml index be41acbd3b6c..80a5348dbfde 100644 --- a/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,msm8996-qmp-ufs-phy.yaml @@ -75,6 +75,9 @@ patternProperties: minItems: 3 maxItems: 6 + "#clock-cells": + const: 1 + "#phy-cells": const: 0 diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml index dde86a19f792..32ed1886fbae 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -43,6 +43,9 @@ properties: vdda-pll-supply: true + "#clock-cells": + const: 1 + "#phy-cells": const: 0 From patchwork Wed Nov 23 10:44:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 627972 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B65CC47088 for ; Wed, 23 Nov 2022 10:56:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236347AbiKWK4F (ORCPT ); Wed, 23 Nov 2022 05:56:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54616 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236232AbiKWKzW (ORCPT ); Wed, 23 Nov 2022 05:55:22 -0500 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E02E25F6 for ; Wed, 23 Nov 2022 02:44:48 -0800 (PST) Received: by mail-lj1-x22c.google.com with SMTP id t10so20973845ljj.0 for ; Wed, 23 Nov 2022 02:44:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hasDy1+t/B8Y/xArguog4wPmJmnVb9H5spMq9+2JDcg=; b=FD+6cjsM0AH2+2CDIxDnDJN4K8NqaRyiqqcM/QhJzUsxY5ItxzaThxQ5aaMxBEF20c LHAc5z1zBDjMTrBZCwKkjJxE341z4lVPte3ze5HMQETw+lZefvPWohfFpZlcxy4zB+Jb ynCs0BYVZZEKVT9NJ9Az9UibYeg/pQe5xq6nj2r4ExwQeFCbj1SY/bttqOwt4wBu9h1s I3VDMt9AfATc5/y7exOFBbzRtFvCM3zmh5kiC3rp6CzmEs6Wukoc0+/w3Kj6VlOjXBJa CFKTy+/VaAyhgdtXmXfGU0OJabrkRfxe8kEuSxUy1r119KIH+xyc1A9+qW3jtzzewR6X nvkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hasDy1+t/B8Y/xArguog4wPmJmnVb9H5spMq9+2JDcg=; b=zqLjoI/4w7lNeUmpDmZAlFxOBkODPUrFiSpwU8w9Qe9m9qtbzpcUbmSxv+pd31jxSg OMyN7ieWqgxBZ5mbXdeELfkOpQP125f3g+Tuc7KlHM2J4eDXYYQBjbxBDvg1VnVbfz8r giqyvj+dVLAh/0YueteUdLiMnyJyxywMfhNVeXm9wgYSMTEgXdKm5loRHC6uBcKaS1wI L0TcfE6Eo6/hPGpaisOqLiA6ZwdC0IEVKhjl65ofhDU9+I19iqfDoDokvftLkO2j9JyK QLm+d/pyMlaMFSJryhewirFHeK7i34L+0syT67GXJJ3DHB1r/RWn7fDgmbeNcWvL3WGb o7TA== X-Gm-Message-State: ANoB5pmGuFMiPzx/LYjptyFmqgjjQl7WZeeQFMbSHxs7gTSl3vHL6TUF 8l5AIxpMTOmqe7JN7sOW15b+mw== X-Google-Smtp-Source: AA0mqf5scskv1XCelKbs7W3K6Z/9+gBIeesXfpBhpCcFHbuhgiPG+poOqIjARIJoBZTQeGFnnRF/iA== X-Received: by 2002:a2e:9998:0:b0:279:7405:85d5 with SMTP id w24-20020a2e9998000000b00279740585d5mr1703820lji.31.1669200286436; Wed, 23 Nov 2022 02:44:46 -0800 (PST) Received: from eriador.lumag.spb.ru (dzpbg0ftyyyyyyyyyyyyt-3.rev.dnainternet.fi. [2001:14ba:a302:5f12::1]) by smtp.gmail.com with ESMTPSA id be34-20020a056512252200b0049e9122bd1bsm2869082lfb.164.2022.11.23.02.44.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 02:44:45 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: Johan Hovold , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH v9 2/4] phy: qcom-qmp-ufs: provide symbol clocks Date: Wed, 23 Nov 2022 12:44:41 +0200 Message-Id: <20221123104443.3415267-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221123104443.3415267-1-dmitry.baryshkov@linaro.org> References: <20221123104443.3415267-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Register three UFS symbol clocks (ufs_rx_symbol_0_clk_src, ufs_rx_symbol_1_clk_src ufs_tx_symbol_0_clk_src). Register OF clock provider to let other devices link these clocks through the DT. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 57 +++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 189103d1bd18..ce50eabccb9d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -1023,6 +1023,59 @@ static int qmp_ufs_clk_init(struct qmp_ufs *qmp) return devm_clk_bulk_get(dev, num, qmp->clks); } +static void qmp_ufs_clk_release_provider(void *res) +{ + of_clk_del_provider(res); +} + +#define UFS_SYMBOL_CLOCKS 3 + +static int qmp_ufs_register_clocks(struct qmp_ufs *qmp, struct device_node *np) +{ + struct clk_hw_onecell_data *clk_data; + struct clk_hw *hw; + char name[64]; + int ret; + + clk_data = devm_kzalloc(qmp->dev, + struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS), + GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->num = UFS_SYMBOL_CLOCKS; + + snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev)); + hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + clk_data->hws[0] = hw; + + snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev)); + hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + clk_data->hws[1] = hw; + + snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev)); + hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + clk_data->hws[2] = hw; + + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); + if (ret) + return ret; + + /* + * Roll a devm action because the clock provider can be a child node. + */ + return devm_add_action_or_reset(qmp->dev, qmp_ufs_clk_release_provider, np); +} + static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np) { struct platform_device *pdev = to_platform_device(qmp->dev); @@ -1135,6 +1188,10 @@ static int qmp_ufs_probe(struct platform_device *pdev) if (ret) goto err_node_put; + ret = qmp_ufs_register_clocks(qmp, np); + if (ret) + goto err_node_put; + qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops); if (IS_ERR(qmp->phy)) { ret = PTR_ERR(qmp->phy); From patchwork Wed Nov 23 10:44:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 628412 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23B63C47089 for ; Wed, 23 Nov 2022 10:56:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236328AbiKWK4G (ORCPT ); Wed, 23 Nov 2022 05:56:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236308AbiKWKzX (ORCPT ); Wed, 23 Nov 2022 05:55:23 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1918271C for ; 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[2001:14ba:a302:5f12::1]) by smtp.gmail.com with ESMTPSA id be34-20020a056512252200b0049e9122bd1bsm2869082lfb.164.2022.11.23.02.44.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 02:44:46 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: Johan Hovold , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Konrad Dybcio Subject: [PATCH v9 3/4] arm64: dts: qcom: sm8450: fix gcc clocks order to follow the schema Date: Wed, 23 Nov 2022 12:44:42 +0200 Message-Id: <20221123104443.3415267-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221123104443.3415267-1-dmitry.baryshkov@linaro.org> References: <20221123104443.3415267-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move the sleep_clk to make sure the gcc device node follows the schema. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d32f08df743d..efb01fefe9c7 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -720,13 +720,13 @@ gcc: clock-controller@100000 { #reset-cells = <1>; #power-domain-cells = <1>; clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, <&pcie0_lane>, - <&pcie1_lane>, - <&sleep_clk>; + <&pcie1_lane>; clock-names = "bi_tcxo", + "sleep_clk", "pcie_0_pipe_clk", - "pcie_1_pipe_clk", - "sleep_clk"; + "pcie_1_pipe_clk"; }; gpi_dma2: dma-controller@800000 { From patchwork Wed Nov 23 10:44:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 627971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C667BC4332F for ; Wed, 23 Nov 2022 10:56:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236032AbiKWK4G (ORCPT ); Wed, 23 Nov 2022 05:56:06 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236371AbiKWKzX (ORCPT ); Wed, 23 Nov 2022 05:55:23 -0500 Received: from mail-lj1-x232.google.com (mail-lj1-x232.google.com [IPv6:2a00:1450:4864:20::232]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 091092ADA for ; Wed, 23 Nov 2022 02:44:50 -0800 (PST) Received: by mail-lj1-x232.google.com with SMTP id d3so20955365ljl.1 for ; Wed, 23 Nov 2022 02:44:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DJbYsescDesnIDrlLOgPi9Av/Ac3g0HEYOKjpTBbqyU=; b=sIT2OAglWOl0uyGg1ad5APBZx/YJPRG1zIYq8YM1yF20bJX5wF5FCyVb/F0J7N9MRH Qkn6W+6TUSzF8vZUx4YqQH9NCOVlHiRArA1ViHwbdHOO9vS8TH4PhPRFgxMHrG/gEBqo zQEsTwdRSt1qk/8XWWNi+keyUZ2Q30JIHTg8CCLaV9zxt7Nv+rpqlCN/BXxqrJBO7NW2 t6XV0lmo0skKZukNdTYuUs7wlmcFngeoWwjEOpxMCqdfSAVyzKdMdbL76fZIxV6uAt63 p0imPpN01r8I6bxZgKV9ciXcZwTdEearyeB/ntOlslTMlBQBZNcAwKEnC97kxPWWSzVv TRAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DJbYsescDesnIDrlLOgPi9Av/Ac3g0HEYOKjpTBbqyU=; b=Y+ACM1ZhPklpcd4SJ29e9YwhCsw2CrMZS0b3VzvecCV01TfIzlao0gv2Ly85Xz0y5j tMEN3z0If8HOH6h4MdfM4VxJRdwJ4ICgxgpOvqGLt5y0Sh+MJ6q4JWqYDD+yj4kj34l2 KTiKwUG2SafTJB5MPrjFbWo8Lc5E3ypQuCx471umVEUl+Y29oGpTh5t5DxjEIUUlvzR9 J5iA5gIFAIPubzbY+82aklFO05YfedMfmsE3wmEzssxMe3/XpbGywcCJvSUeQV7b3y5O KSBoKVc3ekepQ3Mo65/OwUIKY6SDh8j4v20X9RLCZwsQylRIdCjavlZBiHhkSCxQwOpd 4FEQ== X-Gm-Message-State: ANoB5pkxb19yaoPI1FMFFnJfMrAveuyZ+k12/YJvyGCiYOVftXt602QG VZXMsmOCZO+gPa8b7mJllFIkRA== X-Google-Smtp-Source: AA0mqf5Uv9bg05fy4lh0j2BT1KaTrOkd4O06GGwwxWKcKV52qLAuNZsIxTln3NUweGZhGkOl36Vvpw== X-Received: by 2002:a2e:875a:0:b0:26e:1d9:c2a5 with SMTP id q26-20020a2e875a000000b0026e01d9c2a5mr8930832ljj.353.1669200288396; Wed, 23 Nov 2022 02:44:48 -0800 (PST) Received: from eriador.lumag.spb.ru (dzpbg0ftyyyyyyyyyyyyt-3.rev.dnainternet.fi. [2001:14ba:a302:5f12::1]) by smtp.gmail.com with ESMTPSA id be34-20020a056512252200b0049e9122bd1bsm2869082lfb.164.2022.11.23.02.44.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Nov 2022 02:44:47 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski Cc: Johan Hovold , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Konrad Dybcio Subject: [PATCH v9 4/4] arm64: dts: qcom: use UFS symbol clocks provided by PHY Date: Wed, 23 Nov 2022 12:44:43 +0200 Message-Id: <20221123104443.3415267-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221123104443.3415267-1-dmitry.baryshkov@linaro.org> References: <20221123104443.3415267-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove manually created symbol clocks and replace them with clocks provided by PHY. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 5 ++++- arch/arm64/boot/dts/qcom/sm8350.dtsi | 25 ++++--------------------- arch/arm64/boot/dts/qcom/sm8450.dtsi | 15 +++++++++++++-- 3 files changed, 21 insertions(+), 24 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index c0a2baffa49d..935ba6e6bc15 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -699,7 +699,9 @@ gcc: clock-controller@300000 { <&pciephy_1>, <&pciephy_2>, <&ssusb_phy_0>, - <0>, <0>, <0>; + <&ufsphy_lane 0>, + <&ufsphy_lane 1>, + <&ufsphy_lane 2>; clock-names = "cxo", "cxo2", "sleep_clk", @@ -2019,6 +2021,7 @@ ufsphy_lane: phy@627400 { reg = <0x627400 0x12c>, <0x627600 0x200>, <0x627c00 0x1b4>; + #clock-cells = <1>; #phy-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index a86d9ea93b9d..553cf451f283 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -37,24 +37,6 @@ sleep_clk: sleep-clk { clock-frequency = <32000>; #clock-cells = <0>; }; - - ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; - - ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; - - ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0 { - compatible = "fixed-clock"; - clock-frequency = <1000>; - #clock-cells = <0>; - }; }; cpus { @@ -661,9 +643,9 @@ gcc: clock-controller@100000 { <0>, <0>, <0>, - <&ufs_phy_rx_symbol_0_clk>, - <&ufs_phy_rx_symbol_1_clk>, - <&ufs_phy_tx_symbol_0_clk>, + <&ufs_mem_phy_lanes 0>, + <&ufs_mem_phy_lanes 1>, + <&ufs_mem_phy_lanes 2>, <0>, <0>; }; @@ -2147,6 +2129,7 @@ ufs_mem_phy_lanes: phy@1d87400 { <0 0x01d87c00 0 0x1dc>, <0 0x01d87800 0 0x108>, <0 0x01d87a00 0 0x1e0>; + #clock-cells = <1>; #phy-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index efb01fefe9c7..95c01391972a 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -722,11 +722,21 @@ gcc: clock-controller@100000 { clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, <&pcie0_lane>, - <&pcie1_lane>; + <&pcie1_lane>, + <0>, + <&ufs_mem_phy_lanes 0>, + <&ufs_mem_phy_lanes 1>, + <&ufs_mem_phy_lanes 2>, + <0>; clock-names = "bi_tcxo", "sleep_clk", "pcie_0_pipe_clk", - "pcie_1_pipe_clk"; + "pcie_1_pipe_clk", + "pcie_1_phy_aux_clk", + "ufs_phy_rx_symbol_0_clk", + "ufs_phy_rx_symbol_1_clk", + "ufs_phy_tx_symbol_0_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; }; gpi_dma2: dma-controller@800000 { @@ -3166,6 +3176,7 @@ ufs_mem_phy_lanes: phy@1d87400 { <0 0x01d87c00 0 0x1dc>, <0 0x01d87800 0 0x108>, <0 0x01d87a00 0 0x1e0>; + #clock-cells = <1>; #phy-cells = <0>; }; };