From patchwork Tue Nov 22 23:36:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 627568 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24611C4167D for ; Tue, 22 Nov 2022 23:37:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234911AbiKVXhM (ORCPT ); Tue, 22 Nov 2022 18:37:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235017AbiKVXhD (ORCPT ); Tue, 22 Nov 2022 18:37:03 -0500 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EA02C605E for ; Tue, 22 Nov 2022 15:37:02 -0800 (PST) Received: by mail-lj1-x235.google.com with SMTP id a15so19624687ljb.7 for ; Tue, 22 Nov 2022 15:37:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AZRg2hYUZ55Yzoq4hDxZaql963EtJYTAOZ+zJGgmhWA=; b=EDlgWkp3OlyaDWrNvJsNIWgLIYVuQZIYzKiJIOC1ZLqFg/lgJQ0T1TxJE2J51RzJfR geYDbHJUMW0VhJfaDjuFsghMtTK14+bGSGWu2ncdiUXNP2BzirW7lHmIv8haxnjveQYF x/TVfz4Kb12T8w0sjBB5YnzBZgUjw87roqtF6pTwHE+TSL7cy3szvmtlnFnD0usB5J5b qOLm5hoeO/FkV63rEu1iyk1v6UXfjwJp9met0fRRyepSnpltnTyEm5oQ2eo2uHREZSBy idobRjUHn+WIItkKaQz3YqLZWPoQY5HYGCrdLYJPV54YEoJGOAyjbB1eK1CmQDc83Zu9 T9Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AZRg2hYUZ55Yzoq4hDxZaql963EtJYTAOZ+zJGgmhWA=; b=2fD/fKyaWoEBod5LlAT1143uue+i7+XDW2Gakss8GlIt63cCYmmZgqdSPIaNa94TU8 Zjr3saI+SziJIkefVSReXKJNNWXyiiy+RwsxQuAwe8A+1FAXWPBsBtu2deqNjjv8aACt SP75SpavcN6OR1bC/8s7T7Hl62ICf55cCb322PkoB1wB5yBYw+8xAYUE56TUinmm0Xwq 2GQTvnZqbGVpgGEpYHgJ6xh6tysZh9JgKVoeHBQQ3r/IXT6cCzYA/6h0KecEOzExAkvt QgBdyYc7GtTMduQ8T57kM08lRa93rZMovo7NmsQ5ZZvrszOyna0Qe58OJFXId9Nnro6o KWTw== X-Gm-Message-State: ANoB5pnw9Y+/g4+dpKEeQUJUIozyPwDS62eSnL2s4/TLDnBmRuM0B4iz /ee0iq5C29elo6xHbYSpF1oMbg== X-Google-Smtp-Source: AA0mqf5zwUBczXkxLKMF+E+AAp+kHqmVWugsTI1eD54EFn4ZfqP56jOYdGU8gSo8Mhz/sWcMrXpI/g== X-Received: by 2002:a05:651c:2123:b0:277:328:affb with SMTP id a35-20020a05651c212300b002770328affbmr3487255ljq.376.1669160220986; Tue, 22 Nov 2022 15:37:00 -0800 (PST) Received: from eriador.lumag.spb.ru (dzpbkzhtyyyyyyyyyyyyt-3.rev.dnainternet.fi. [2001:14ba:a302:8a1a::1]) by smtp.gmail.com with ESMTPSA id h3-20020ac250c3000000b00492c463526dsm2666454lfm.186.2022.11.22.15.37.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 15:37:00 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 1/5] arm64: dts: qcom: sm8450: add RPMH_REGULATOR_LEVEL_LOW_SVS_D1 Date: Wed, 23 Nov 2022 01:36:55 +0200 Message-Id: <20221122233659.3308175-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221122233659.3308175-1-dmitry.baryshkov@linaro.org> References: <20221122233659.3308175-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add another power saving state used on SM8450. Unfortunately adding it in proper place causes renumbering of all the opp states in sm8450.dtsi Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 20 ++++++++++++-------- include/dt-bindings/power/qcom-rpmpd.h | 1 + 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index f20db5456765..8cc9f62f7645 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3211,35 +3211,39 @@ rpmhpd_opp_min_svs: opp2 { opp-level = ; }; - rpmhpd_opp_low_svs: opp3 { + rpmhpd_opp_low_svs_d1: opp3 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp4 { opp-level = ; }; - rpmhpd_opp_svs: opp4 { + rpmhpd_opp_svs: opp5 { opp-level = ; }; - rpmhpd_opp_svs_l1: opp5 { + rpmhpd_opp_svs_l1: opp6 { opp-level = ; }; - rpmhpd_opp_nom: opp6 { + rpmhpd_opp_nom: opp7 { opp-level = ; }; - rpmhpd_opp_nom_l1: opp7 { + rpmhpd_opp_nom_l1: opp8 { opp-level = ; }; - rpmhpd_opp_nom_l2: opp8 { + rpmhpd_opp_nom_l2: opp9 { opp-level = ; }; - rpmhpd_opp_turbo: opp9 { + rpmhpd_opp_turbo: opp10 { opp-level = ; }; - rpmhpd_opp_turbo_l1: opp10 { + rpmhpd_opp_turbo_l1: opp11 { opp-level = ; }; }; diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index 7b2e4b66419a..701401c8b945 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -174,6 +174,7 @@ /* SDM845 Power Domain performance levels */ #define RPMH_REGULATOR_LEVEL_RETENTION 16 #define RPMH_REGULATOR_LEVEL_MIN_SVS 48 +#define RPMH_REGULATOR_LEVEL_LOW_SVS_D1 56 #define RPMH_REGULATOR_LEVEL_LOW_SVS 64 #define RPMH_REGULATOR_LEVEL_SVS 128 #define RPMH_REGULATOR_LEVEL_SVS_L0 144 From patchwork Tue Nov 22 23:36:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 627569 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81DD4C46467 for ; Tue, 22 Nov 2022 23:37:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234531AbiKVXhL (ORCPT ); Tue, 22 Nov 2022 18:37:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235058AbiKVXhE (ORCPT ); Tue, 22 Nov 2022 18:37:04 -0500 Received: from mail-lj1-x234.google.com (mail-lj1-x234.google.com [IPv6:2a00:1450:4864:20::234]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63C94C6228 for ; Tue, 22 Nov 2022 15:37:03 -0800 (PST) Received: by mail-lj1-x234.google.com with SMTP id b9so19645448ljr.5 for ; Tue, 22 Nov 2022 15:37:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3Tj4Q5QZjc2k2el66bp1+eHo8gv1sTvtgrH+UGFLgDo=; b=rdHqa9cDNzYTpxm1jnDHl7Kok4DMVbYP2Y4BUdv3+aJfNaHlFL/ovLeAvINcDLe3Uy RrLyroxwrbnCBvANa7dKI9XyVoGEKt2PvqjT2W61cTeRx9PHP4TptdSj/REcVqGTAhSe dYsECvEG5hZEFychop/xRTq/ubWJqt1wsW1t2N+9ci88pI8X1GK8c4h/Pggz/OuLpLKr S241yF0SKhHTNrg1VdCRCQ5MuwLG+gYwo98dFzvsljuD99f2mV5ICNy/AY5eE2ecdo72 BcKe96YTKH8CwnZH/S4pUlai2RuOhYvG5bkQ9c9SdyX4kYdaLXQgdT51PZiUa1YKUdr5 XbTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3Tj4Q5QZjc2k2el66bp1+eHo8gv1sTvtgrH+UGFLgDo=; b=d5nrqoN00mMSviFH++dojqyhPzr58zsaUgcf29+1Ht5Ae2Q34rQQcvJObbLFRjzVFI yBgVbCYdXE758BhLkYYio+/0xtgxysEjH9pQqgXg5sMfwwTZ+/PzhAFS6BJJTeE26vWx Otj23FrJx4KYuz4KUJeZnZaZGDWGGuddhbHJgyMCYEmvvzjiDCIP4wQhGgetPWIivMZ6 jrMhHyyrAvV4RRU3iaeUOQFYMKy3Z3quo7SeKpvH2DXQBK+XaSCburttcKjPq55mpsfP /pqj6c9R0ZMcr5CYT0dRF5lcoxq+lSJ3AlMKar7kOjpcq0LmtpmeP2hW+mQYbp13nUTm UBGg== X-Gm-Message-State: ANoB5pm3oz5JoZnlLS9PbafqIYuUOv3Anl8zAz39lq/gMTSELSrQdI+o lHCLDTByt0ojxw1Q4bBjcnwgDw== X-Google-Smtp-Source: AA0mqf6MOVpxArZTIFBSwfm+p3KfTu3V10RNVsAl3x4G+yQzZ/FXYUyEPT60XFay2V1nrE8EFQXu7w== X-Received: by 2002:a05:651c:b10:b0:26f:c081:9aee with SMTP id b16-20020a05651c0b1000b0026fc0819aeemr1885457ljr.219.1669160221747; Tue, 22 Nov 2022 15:37:01 -0800 (PST) Received: from eriador.lumag.spb.ru (dzpbkzhtyyyyyyyyyyyyt-3.rev.dnainternet.fi. [2001:14ba:a302:8a1a::1]) by smtp.gmail.com with ESMTPSA id h3-20020ac250c3000000b00492c463526dsm2666454lfm.186.2022.11.22.15.37.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 15:37:01 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 2/5] arm64: dts: qcom: sm8450: add display hardware devices Date: Wed, 23 Nov 2022 01:36:56 +0200 Message-Id: <20221122233659.3308175-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221122233659.3308175-1-dmitry.baryshkov@linaro.org> References: <20221122233659.3308175-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add devices tree nodes describing display hardware on SM8450: - Display Clock Controller - MDSS - MDP - two DSI controllers and DSI PHYs This does not provide support for DP controllers present on SM8450. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 284 ++++++++++++++++++++++++++- 1 file changed, 280 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 8cc9f62f7645..0c3a3a5578b0 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -2394,6 +2394,282 @@ camcc: clock-controller@ade0000 { status = "disabled"; }; + mdss: mdss@ae00000 { + compatible = "qcom,sm8450-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + /* same path used twice */ + interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, + <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x2800 0x402>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8450-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-172000000 { + opp-hz = /bits/ 64 <172000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-5nm-8450"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + power-domains = <&rpmhpd SM8450_MMCX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-5nm-8450"; + reg = <0 0x0ae96400 0 0x200>, + <0 0x0ae96600 0 0x280>, + <0 0x0ae96900 0 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + dispcc: clock-controller@af00000 { compatible = "qcom,sm8450-dispcc"; reg = <0 0x0af00000 0 0x20000>; @@ -2401,10 +2677,10 @@ dispcc: clock-controller@af00000 { <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GCC_DISP_AHB_CLK>, <&sleep_clk>, - <0>, /* dsi0 */ - <0>, - <0>, /* dsi1 */ - <0>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, <0>, /* dp0 */ <0>, <0>, /* dp1 */ From patchwork Tue Nov 22 23:36:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 628006 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5202FC43217 for ; Tue, 22 Nov 2022 23:37:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230009AbiKVXhN (ORCPT ); Tue, 22 Nov 2022 18:37:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235136AbiKVXhF (ORCPT ); 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[2001:14ba:a302:8a1a::1]) by smtp.gmail.com with ESMTPSA id h3-20020ac250c3000000b00492c463526dsm2666454lfm.186.2022.11.22.15.37.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 15:37:02 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH v2 3/5] arm64: dts: qcom: sm8450-hdk: enable display hardware Date: Wed, 23 Nov 2022 01:36:57 +0200 Message-Id: <20221122233659.3308175-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221122233659.3308175-1-dmitry.baryshkov@linaro.org> References: <20221122233659.3308175-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable MDSS/DPU/DSI0 on SM8450-HDK device. Note, there is no panel configuration (yet). Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 2dd4f8c8f931..75b7aecb7d8e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -349,6 +349,28 @@ vreg_l7e_2p8: ldo7 { }; }; +&dispcc { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l6b_1p2>; + status = "okay"; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l5b_0p88>; + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &pcie0 { status = "okay"; max-link-speed = <2>; From patchwork Tue Nov 22 23:36:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 628005 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E6B4DC47089 for ; Tue, 22 Nov 2022 23:37:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234913AbiKVXhO (ORCPT ); Tue, 22 Nov 2022 18:37:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235183AbiKVXhG (ORCPT ); Tue, 22 Nov 2022 18:37:06 -0500 Received: from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com [IPv6:2a00:1450:4864:20::22a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 639ACBEB6D for ; Tue, 22 Nov 2022 15:37:05 -0800 (PST) Received: by mail-lj1-x22a.google.com with SMTP id x21so19596768ljg.10 for ; Tue, 22 Nov 2022 15:37:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FM4K/pkHjLHkAOvfw4d2cino7N9sUMcIq1wxV3ai/bY=; b=KOsB3D1ho5/J9eaOkqkoyZqIaHUjyVggsLvtTrZLamLCBMyz4E88xUqGZ2H+bpAswX IlRtdpWMlod+j3hCE2lNqqbs1FXOKze37Yerp8Wis/uSMcQ8CuVRKIxYxPlSpOchQOuL isc/9GPdtC+dQaG7sOwDslT+51chZzcLUyRilb4yadGv2IJftqTXphuIYgtaVHJ10DW0 GjgbYDubU+k2xnWtJyTZCdBjZd2I8QRl21jn8MJOX3TM85gCor1QSVl2WHg6TNhdK9dV efOdBWkihJP5oju4p1IVqPoGW/xSh5u8RpJ1U8hbG9XJkzYM5ds1x/hwifd9xslXWTc1 mmUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FM4K/pkHjLHkAOvfw4d2cino7N9sUMcIq1wxV3ai/bY=; b=iVNwZuqNGdsZFi18ggyICXhWMg7MiXNFhH7AgV3NDaqvNVbbivuTTA7k4xip8AA8JH 7Lz7htqXma1pJxEapNebfxSsPx4y3jY50uKyDZJ+Q8he43wf9azjOTR1tk1LzUui66AO yuYrUc+R3OXeTGOcPMWIuRqlwYt0kdw/QWG6KbHqnjb+0vIDpbg0Pj/fNRI8N+EqVaSr DF4A4r5HUn6C+El8+yDlkh+JBaJ4XB1Oz8FIY1Ju0W77bEx2orkhVHWEBESmW+Tpkh8z nnjwBvkTO1EZdXUCAVitxCzUu4VGkPdcmcO9YkcLDj5mfFh9IEzJqJ+boenLV++nb2lU YadQ== X-Gm-Message-State: ANoB5plwjmb6QSPoGXB4vXzTgNLPAL5VPRgIn5NR/6gBAgwhqnbTFMZ9 lvOLX9x7AvWtHaJDCtKZsgPXOQ== X-Google-Smtp-Source: AA0mqf5bZVQDunR4a0/2DQ93hnQZnrAIyyh6AoqyqeMzmVooT0FTtKSReZ5efjgw/D1ntdL5r9UMaQ== X-Received: by 2002:a2e:b55b:0:b0:26c:554f:87a5 with SMTP id a27-20020a2eb55b000000b0026c554f87a5mr5067918ljn.452.1669160223739; Tue, 22 Nov 2022 15:37:03 -0800 (PST) Received: from eriador.lumag.spb.ru (dzpbkzhtyyyyyyyyyyyyt-3.rev.dnainternet.fi. [2001:14ba:a302:8a1a::1]) by smtp.gmail.com with ESMTPSA id h3-20020ac250c3000000b00492c463526dsm2666454lfm.186.2022.11.22.15.37.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 15:37:02 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Vinod Koul Subject: [PATCH v2 4/5] arm64: dts: qcom: sm8450-hdk: Add LT9611uxc HDMI bridge Date: Wed, 23 Nov 2022 01:36:58 +0200 Message-Id: <20221122233659.3308175-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221122233659.3308175-1-dmitry.baryshkov@linaro.org> References: <20221122233659.3308175-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Vinod Koul Add the LT9611uxc DSI-HDMI bridge and supplies Signed-off-by: Vinod Koul Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 61 +++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 75b7aecb7d8e..6b6dcd0e0052 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -20,6 +20,28 @@ chosen { stdout-path = "serial0:115200n8"; }; + lt9611_1v2: lt9611-vdd12-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_1V2"; + + vin-supply = <&vph_pwr>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + gpio = <&tlmm 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + lt9611_3v3: lt9611-3v3-regulator { + compatible = "regulator-fixed"; + regulator-name = "LT9611_3V3"; + + vin-supply = <&vreg_bob>; + gpio = <&tlmm 109 GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -353,6 +375,27 @@ &dispcc { status = "okay"; }; +&i2c9 { + clock-frequency = <400000>; + status = "okay"; + + lt9611_codec: hdmi-bridge@2b { + compatible = "lontium,lt9611uxc"; + reg = <0x2b>; + + interrupts-extended = <&tlmm 44 IRQ_TYPE_EDGE_FALLING>; + + reset-gpios = <&tlmm 107 GPIO_ACTIVE_HIGH>; + + vdd-supply = <<9611_1v2>; + vcc-supply = <<9611_3v3>; + + pinctrl-names = "default"; + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + + }; +}; + &mdss { status = "okay"; }; @@ -416,6 +459,10 @@ &qupv3_id_0 { status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &sdhc_2 { cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; pinctrl-names = "default", "sleep"; @@ -431,6 +478,20 @@ &sdhc_2 { &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; + lt9611_irq_pin: lt9611-irq { + pins = "gpio44"; + function = "gpio"; + bias-disable; + }; + + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio107"; + function = "normal"; + + output-high; + input-disable; + }; + sdc2_card_det_n: sd-card-det-n-state { pins = "gpio92"; function = "gpio"; From patchwork Tue Nov 22 23:36:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 627567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 552F0C433FE for ; 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[2001:14ba:a302:8a1a::1]) by smtp.gmail.com with ESMTPSA id h3-20020ac250c3000000b00492c463526dsm2666454lfm.186.2022.11.22.15.37.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Nov 2022 15:37:04 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Cc: Stephen Boyd , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Vinod Koul , Krzysztof Kozlowski Subject: [PATCH v2 5/5] arm64: dts: qcom: sm8450-hdk: Enable HDMI Display Date: Wed, 23 Nov 2022 01:36:59 +0200 Message-Id: <20221122233659.3308175-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221122233659.3308175-1-dmitry.baryshkov@linaro.org> References: <20221122233659.3308175-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Vinod Koul Add the HDMI display nodes and link it to DSI. Signed-off-by: Vinod Koul Reviewed-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 36 +++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 6b6dcd0e0052..709cddaac781 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -20,6 +20,17 @@ chosen { stdout-path = "serial0:115200n8"; }; + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + lt9611_1v2: lt9611-vdd12-regulator { compatible = "regulator-fixed"; regulator-name = "LT9611_1V2"; @@ -393,6 +404,26 @@ lt9611_codec: hdmi-bridge@2b { pinctrl-names = "default"; pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; }; }; @@ -405,6 +436,11 @@ &mdss_dsi0 { status = "okay"; }; +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + &mdss_dsi0_phy { vdds-supply = <&vreg_l5b_0p88>; status = "okay";