From patchwork Tue Nov 15 15:27:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 625655 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C5DFEC433FE for ; Tue, 15 Nov 2022 15:27:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237818AbiKOP1n (ORCPT ); Tue, 15 Nov 2022 10:27:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237700AbiKOP1m (ORCPT ); Tue, 15 Nov 2022 10:27:42 -0500 Received: from mail-ej1-x631.google.com (mail-ej1-x631.google.com [IPv6:2a00:1450:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D29B2D769 for ; Tue, 15 Nov 2022 07:27:40 -0800 (PST) Received: by mail-ej1-x631.google.com with SMTP id n20so16314897ejh.0 for ; Tue, 15 Nov 2022 07:27:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/OnIF5KJq38ydF7gLxLfsf0iN2iW7kEJTrwDz5/qCW8=; b=XeD7h1D85c6PELOSUkCRH42zXo6QrloEq7je/ihrbaWxuZGUSugvC6ZYCtZPrpYQ4C m0/ZoyjftHwJDvZSWFeHc7V1cB19WR8ouls1xE8wSHQj9ZSBG/zZdQbUr//U4Hz78NOh 70ld40peqz55/qWelsXnefWszp8OMz/rpqmTbA6IjQrxu45BbDpIS0QzOQ2DFbGI6PtQ RNqBkZX2Prkbb3LIHpdKtx0PT/Q6nocYrCQXe9fVAYLrKU6ViBsbbJUZSQKlvvaQsi7f 49WgjnxLy320wM2CPMu7og+jlX6VaL9gxSlfXHPthueLNUy/SEDBgRDH8QLQkHu54Wqp dG4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/OnIF5KJq38ydF7gLxLfsf0iN2iW7kEJTrwDz5/qCW8=; b=LL1ZCgGPu8CYftvWfUMtHR/FJd/yqwvqNnkvKp1bc+lnEEhSzDl9wIEcThtjqNjk1Q NdI5thHeHwP7XFOAg1MJP/HD0I3gcRjoM/smSnwZRVXvJKCsPQbrTYKTnIHWaSiSZHY2 0k6NgAo5CnoGdfcl1hE3XFU7ffB80gI77OFVWlRxkVBu9VgiLN1pS797HdfrkBRaaK8O Zudk1Z5PDltR+WC36z65Qsd1PVYslBa+1fz1LAB/lwhnHbWGJVaull3j37RSRw2FX8tp 27/MCyp6TcuurrEDTGQ5zmvoLQp3f+0yYxNiLVCribpJB/3ZXqynlM8Go/+An55LuRlt KkJA== X-Gm-Message-State: ANoB5pm0DFTh/5qCXeTpi20Mu92pQXd6i4pJzrourvLgZeZdiBoHe0Lj J2+R98iaeBAqBDpDwgFFfDXqJjRmH6AkQP0S X-Google-Smtp-Source: AA0mqf6t90H5G/NxFj6kZZ89Op+6k4zWLusxmbs0qlF4AQ2K0srx4P2Envtn5p5Sx3vJB9JOY4JsQw== X-Received: by 2002:a17:906:d82:b0:7ad:8a7a:2343 with SMTP id m2-20020a1709060d8200b007ad8a7a2343mr13999054eji.225.1668526058653; Tue, 15 Nov 2022 07:27:38 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id ku21-20020a170907789500b007ae1ab8f887sm5750679ejc.14.2022.11.15.07.27.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Nov 2022 07:27:38 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/9] dt-bindings: arm-smmu: Allow 3 power domains on SM6375 MMU500 Date: Tue, 15 Nov 2022 16:27:19 +0100 Message-Id: <20221115152727.9736-2-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221115152727.9736-1-konrad.dybcio@linaro.org> References: <20221115152727.9736-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SMMU on SM6375 requires 3 power domains to be active. Add an appropriate description of that. Signed-off-by: Konrad Dybcio --- .../devicetree/bindings/iommu/arm,smmu.yaml | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 28f5720824cd..348a73f3e5f0 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -200,7 +200,8 @@ properties: maxItems: 7 power-domains: - maxItems: 1 + minItems: 1 + maxItems: 3 nvidia,memory-controller: description: | @@ -364,6 +365,26 @@ allOf: - description: interface clock required to access smmu's registers through the TCU's programming interface. + - if: + properties: + compatible: + contains: + const: qcom,sm6375-smmu-500 + then: + properties: + power-domains: + items: + - description: SNoC MMU TBU RT GDSC + - description: SNoC MMU TBU NRT GDSC + - description: SNoC TURING MMU TBU0 GDSC + + required: + - power-domains + else: + properties: + power-domains: + maxItems: 1 + examples: - |+ /* SMMU with stream matching or stream indexing */ From patchwork Tue Nov 15 15:27:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 624886 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B8981C43219 for ; Tue, 15 Nov 2022 15:27:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237837AbiKOP1o (ORCPT ); Tue, 15 Nov 2022 10:27:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57802 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237288AbiKOP1n (ORCPT ); Tue, 15 Nov 2022 10:27:43 -0500 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 011642D76B for ; Tue, 15 Nov 2022 07:27:42 -0800 (PST) Received: by mail-ej1-x62a.google.com with SMTP id i10so28239989ejg.6 for ; Tue, 15 Nov 2022 07:27:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IypuJ/Pof2USoK7b4/Atk2DRjHrF23U2plR6w47C7ao=; b=ito5/jloRWFJ99jHqzlUSB4dBZpMQRiX+Vmb2DRhO1mWYaBAQEtz+7NntJX+Jan9PH Atnwdz311XrxObo9JVDE+jxVAMcBgJcl1wmVk2ob3hGKKWOIEU17e4FaVriDc3CLmREn ta/KKE/wRx5PuWIqFfrU1IFuFxHwcnBj5QOmRZXuqmNb9ag6pu23wkvs3zGqVf2/8I2d SEyqFklKn0qZDPmmVta7XKisPbu4bcOJK7VKRDBZTxso1Krtk//SocgRlFAjH+ISWxKM t9XH5TB0bvWdQqzSXMBBql44J1oUnVZjuVilEsk2ce0GmK7wYFQtYT/ire9Oq97kOk2m +rcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IypuJ/Pof2USoK7b4/Atk2DRjHrF23U2plR6w47C7ao=; b=PqULuevXFCQq5qdATea2AgnFBqKeeAOgkdy7qQg1/H/MenveGrgKJtpa9UrYG/D67w bgQIBSmHVc56C2e8QfjrWTsrE+G885wnGVpJL9peAASravK19v0bC6tzrgVHl5TCvlYH FblpgMK+wGx5oSQkzBGCC4NFgD49lv9Bpv9cGwjjEGHNFZblv8vCW6DX240D2xfkhNFG JrPhGOH0IUQr+zEKMd/o87NTcB8AbbDNjDdClA33hPx24ggTeLXKL8zEX5C4BzYeIymJ ytflnP88IxGxaTeKEUuRn9+kISd4RGKX1upl5AOIcTEYXiFfjbWNPGSvBJwslQCEZUa2 YC+A== X-Gm-Message-State: ANoB5pmXMZY7abyP9uydd8UitZe1Jzlp6SlRq2Lzn40j1vaWBEivzPL2 lXIdSYqzo77Kj12GKMrRYCR79f9pQyyB6LOR X-Google-Smtp-Source: AA0mqf50V2PfNgzViLP2mKi1jL47BCBMB63T0Ng5UlgIw+DgCsgLNzx1P9I0TusUJoS3nHavcUpnFg== X-Received: by 2002:a17:906:1441:b0:7ad:b97e:283a with SMTP id q1-20020a170906144100b007adb97e283amr13913029ejc.567.1668526060270; Tue, 15 Nov 2022 07:27:40 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id ku21-20020a170907789500b007ae1ab8f887sm5750679ejc.14.2022.11.15.07.27.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Nov 2022 07:27:39 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Dmitry Baryshkov , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/9] arm64: dts: qcom: pmk8350: Allow specifying arbitrary SID Date: Tue, 15 Nov 2022 16:27:20 +0100 Message-Id: <20221115152727.9736-3-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221115152727.9736-1-konrad.dybcio@linaro.org> References: <20221115152727.9736-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PMK8350 is shipped on SID6 with some SoCs, for example with SM6375. Add some preprocessor logic to allow changing the SID in cases like this. While I am not in favour of adding #if's into the device tree, this is the least messy way to handle this. If one isn't specified, it will default to 0 (as it has been previously). Suggested-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pmk8350.dtsi | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi index a7ec9d11946d..2730d97ab213 100644 --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi @@ -8,10 +8,15 @@ #include #include +/* (Sadly) this PMIC can be configured to be at different SIDs */ +#ifndef PMK8350_SID + #define PMK8350_SID 0 +#endif + &spmi_bus { - pmk8350: pmic@0 { + pmk8350: pmic@PMK8350_SID { compatible = "qcom,pmk8350", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; + reg = ; #address-cells = <1>; #size-cells = <0>; @@ -21,14 +26,14 @@ pmk8350_pon: pon@1300 { pon_pwrkey: pwrkey { compatible = "qcom,pmk8350-pwrkey"; - interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + interrupts = ; linux,code = ; status = "disabled"; }; pon_resin: resin { compatible = "qcom,pmk8350-resin"; - interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupts = ; status = "disabled"; }; }; @@ -38,14 +43,14 @@ pmk8350_vadc: adc@3100 { reg = <0x3100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupts = ; #io-channel-cells = <1>; }; pmk8350_adc_tm: adc-tm@3400 { compatible = "qcom,adc-tm7"; reg = <0x3400>; - interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; @@ -56,7 +61,7 @@ pmk8350_rtc: rtc@6100 { compatible = "qcom,pmk8350-rtc"; reg = <0x6100>, <0x6200>; reg-names = "rtc", "alarm"; - interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + interrupts = ; status = "disabled"; }; From patchwork Tue Nov 15 15:27:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 625654 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCAD0C4167D for ; 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Tue, 15 Nov 2022 07:27:41 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/9] arm64: dts: qcom: sm6375: Add GPI DMA nodes Date: Tue, 15 Nov 2022 16:27:21 +0100 Message-Id: <20221115152727.9736-4-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221115152727.9736-1-konrad.dybcio@linaro.org> References: <20221115152727.9736-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add nodes for GPI DMA hosts on SM6375. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 9b1a497e5ca7..62a64dd731a0 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -567,6 +567,46 @@ rpm_msg_ram: sram@45f0000 { reg = <0 0x045f0000 0 0x7000>; }; + gpi_dma0: dma-controller@4a00000 { + compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x04a00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0x16 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + + gpi_dma1: dma-controller@4c00000 { + compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x04c00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0xd6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + usb_1: usb@4ef8800 { compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; reg = <0 0x04ef8800 0 0x400>; From patchwork Tue Nov 15 15:27:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 624885 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53AE4C433FE for ; Tue, 15 Nov 2022 15:27:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238008AbiKOP1r (ORCPT ); Tue, 15 Nov 2022 10:27:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237906AbiKOP1p (ORCPT ); Tue, 15 Nov 2022 10:27:45 -0500 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B5422D769 for ; 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Tue, 15 Nov 2022 07:27:42 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/9] arm64: dts: qcom: sm6375: Add pin configs for some QUP configurations Date: Tue, 15 Nov 2022 16:27:22 +0100 Message-Id: <20221115152727.9736-5-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221115152727.9736-1-konrad.dybcio@linaro.org> References: <20221115152727.9736-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the pin setup for SPI/I2C configurations that are supported downstream. I can guesstimate the correct settings for other buses, but: - I have no hardware to test it on - Some QUPs are straight up missing pin funcs in TLMM - Vendors probably didn't really care and used whatever was there in the reference design and BSP - should any other be used, they can be configured at a later time Acked-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 62a64dd731a0..952156891476 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -519,6 +519,49 @@ tlmm: pinctrl@500000 { gpio-controller; #interrupt-cells = <2>; #gpio-cells = <2>; + + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup00"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio61", "gpio62"; + function = "qup01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio45", "gpio46"; + function = "qup02"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio19", "gpio20"; + /* TLMM, GCC and vendor DT all have different indices.. */ + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio4", "gpio5"; + function = "qup10"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qup00"; + drive-strength = <6>; + bias-disable; + }; }; gcc: clock-controller@1400000 { From patchwork Tue Nov 15 15:27:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 625653 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B81C3C4332F for ; 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Tue, 15 Nov 2022 07:27:44 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 5/9] arm64: dts: qcom: sm6375: Add QUPs and corresponding SPI/I2C hosts Date: Tue, 15 Nov 2022 16:27:23 +0100 Message-Id: <20221115152727.9736-6-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221115152727.9736-1-konrad.dybcio@linaro.org> References: <20221115152727.9736-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add necessary nodes to support various QUP configurations. Note that: - QUP3/4/5 and 11 are straight up missing - There may be more QUPs physically on the SoC that work perfectly fine, but Qualcomm decided not to expose them on the downstream kernel - Many are missing pinctrls, as there are both missing pin funcs in the TLMM driver and missing configuration settings (though they are possible to guesstimate quite easily) Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 306 +++++++++++++++++++++++++++ 1 file changed, 306 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 952156891476..6adffd927a8e 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -317,6 +318,25 @@ CLUSTER_PD: cpu-cluster0 { }; }; + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -630,6 +650,125 @@ gpi_dma0: dma-controller@4a00000 { status = "disabled"; }; + qupv3_id_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04ac0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_default>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@4a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* + * As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream. + * There is a comment in the included DTSI of another SoC saying that they + * are not "bolled out" (probably meaning not routed to solder balls) + * TLMM driver however, suggests there are as many as 15 QUPs in total! + * Most of which don't even have pin configurations for.. Sad stuff! + */ + }; + gpi_dma1: dma-controller@4c00000 { compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x04c00000 0 0x60000>; @@ -650,6 +789,173 @@ gpi_dma1: dma-controller@4c00000 { status = "disabled"; }; + qupv3_id_1: geniqup@4cc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04cc0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xc3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c6: i2c@4c80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@4c80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@4c84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi7: spi@4c84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@4c88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_default>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi8: spi@4c88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@4c8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@4c8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c10: i2c@4c90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_default>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi10: spi@4c90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + usb_1: usb@4ef8800 { compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; reg = <0 0x04ef8800 0 0x400>; From patchwork Tue Nov 15 15:27:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 624884 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17DAAC433FE for ; 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Tue, 15 Nov 2022 07:27:46 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 6/9] arm64: dts: qcom: sm6375-pdx225: Enable QUPs & GPI DMA Date: Tue, 15 Nov 2022 16:27:24 +0100 Message-Id: <20221115152727.9736-7-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221115152727.9736-1-konrad.dybcio@linaro.org> References: <20221115152727.9736-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable QUPs & GPI DMA on the Xperia 10 IV. Signed-off-by: Konrad Dybcio --- .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 450d4a557df1..6a0f4c0bf7ad 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -65,6 +65,22 @@ vph_pwr: vph-pwr-regulator { }; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <13 4>; }; From patchwork Tue Nov 15 15:27:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 625652 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AE18C4321E for ; Tue, 15 Nov 2022 15:29:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231347AbiKOP3C (ORCPT ); Tue, 15 Nov 2022 10:29:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231437AbiKOP2J (ORCPT ); Tue, 15 Nov 2022 10:28:09 -0500 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C37812DAAA for ; Tue, 15 Nov 2022 07:27:50 -0800 (PST) Received: by mail-ed1-x52a.google.com with SMTP id x102so7142001ede.0 for ; Tue, 15 Nov 2022 07:27:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tczgVkko34uNNjGCJDRlpeQPz9HaugPUNs3BO6M1w28=; b=m2gDNZOwfzRyfwFpjIL+h89qb5vBHcJTyTpxhG1o9BXJPeLfFGmAWM4BDldrEAr8wQ F4CZoXDWgXGS6SSMfuIokf4K8owq4CNlzFo5EeqhhtnaKfDK+/YDjN+XtR8drMP3ZJkB O22DrH1G35Fa39PJXQHXEbxxG4VFnG9A77/xFvO5JfEAI+S2btlm+Hx5uiPuZkCb7Ysv OCHpqlC8MZUYn4IHfusF//Bq7t9iThUSF2hG/FuyO60R2eYIvDR5c8Pn8voVg+jEBrFs jA/wLHbWk7oNKVEQbQ8sydC+HFkKjfnzGarP//Gjt8QwdyRIHz+xM1R8SvIHdMaVtlKb 95nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tczgVkko34uNNjGCJDRlpeQPz9HaugPUNs3BO6M1w28=; b=U01ESamVxfF99+U3Bw6XAryM8/Ejr4rXZXFhJuhycbeYYXbZcG59/843WGXsLLkTQN mOF3zUVyPiNmCzZjku0yY/tr9KMdmf1tO0at3WlyZZk8PaDnRtsDuSTMF+tSJjCMAw8f P8vxDXkG6vhR0UHOW+FPPSUrXgoPvV4iRagVM4qSQJOqevB0dzVwwAp9/6x0VIPxMo3L iDbMEXeYg0u7rye2HE1HrFdQFFeTAabcpDl1FDTcVd1StsMXzPIc/Lr2+U3b0r/2K498 6JKFTNPr8+rkvoprnbTtvVbxPYE79bXab7QVxkwQdBcxQOO1MfStdjMpxV0wXO4ZWVkk chAw== X-Gm-Message-State: ANoB5pnVopEEfqTApXwhNAjj6Jrlyi2Lme+AjB4gpt0PvHjzfcAAZSjd SZIqr7JhbyM1AvHTbHScz8DQ3s2gc9joYB5V X-Google-Smtp-Source: AA0mqf4erJrOY2wpFpDSx+j8j7JX2M+fk5u4BVtsN38AgY3Cgkb21lGhz+IjdjY8cW7aTSvQcplirQ== X-Received: by 2002:aa7:cf11:0:b0:468:4cd4:f133 with SMTP id a17-20020aa7cf11000000b004684cd4f133mr2247707edy.18.1668526069015; Tue, 15 Nov 2022 07:27:49 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id ku21-20020a170907789500b007ae1ab8f887sm5750679ejc.14.2022.11.15.07.27.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Nov 2022 07:27:48 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 7/9] arm64: dts: qcom: sm6375-pdx225: Add PMIC peripherals Date: Tue, 15 Nov 2022 16:27:25 +0100 Message-Id: <20221115152727.9736-8-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221115152727.9736-1-konrad.dybcio@linaro.org> References: <20221115152727.9736-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add and enable PMIC peripherals for PM6125, PMR735a and PMK8350 on the Xperia 10 IV. Signed-off-by: Konrad Dybcio --- .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 6a0f4c0bf7ad..c830124cb483 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -5,10 +5,18 @@ /dts-v1/; +/* PMK8350 is configured to use SID6 instead of 0 */ +#define PMK8350_SID 6 + #include #include "sm6375.dtsi" +#include "pm6125.dtsi" +#include "pmk8350.dtsi" #include "pmr735a.dtsi" +/* PM6125 PON is used and we can't have duplicate labels */ +/delete-node/ &pmk8350_pon; + / { model = "Sony Xperia 10 IV"; compatible = "sony,pdx225", "qcom,sm6375"; @@ -73,6 +81,23 @@ &gpi_dma1 { status = "okay"; }; +&pmk8350_adc_tm { + status = "okay"; +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; From patchwork Tue Nov 15 15:27:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 625651 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FBB4C43217 for ; Tue, 15 Nov 2022 15:29:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231563AbiKOP3E (ORCPT ); Tue, 15 Nov 2022 10:29:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58448 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238226AbiKOP2K (ORCPT ); Tue, 15 Nov 2022 10:28:10 -0500 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 516812DAB6 for ; Tue, 15 Nov 2022 07:27:51 -0800 (PST) Received: by mail-ej1-x629.google.com with SMTP id t25so36859509ejb.8 for ; Tue, 15 Nov 2022 07:27:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vg8NC6M8db0CO7+c1/ONSYumm0SUtSfLgSyiNkD+2X8=; b=KMv9NkjCZaMovl0v85MLOAMCKNnmtqMrpiIeNHOoLfEf0HeCc223B+vmdN+0r29d5u SpKG5X4hvF5LjCbd1ck6S6glJPJzaAJ5qijH2WO2ZC/4zXuJml9SSc3V1FJD8Y2NkDHv /z0YUvakxTNipvi6Vn0i39mRGLuGVgeH1CcQmLS8UjB8A9x4rFANdjiSXp9lGHaReUPh 02u67QxhlJfDvzi83MJ87beJ9fIGFskSCq5R3dekH3IdmqKslqupxlUZ1NKl4k1kIjQ0 0HZdHUlu/4n2PnbjFxtnWjE3HymsAsr96xCBiwFwG+MbjAzoQ0CKaglGR1azocJky/Q0 9X8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vg8NC6M8db0CO7+c1/ONSYumm0SUtSfLgSyiNkD+2X8=; b=hbBWm2qgZ+L0WMwExPxPRO0UGp77vuvA7c12fgzqFeyo8Xdl8tiT5spwthku2BICK7 /eQK8c/kyz7Nc9lCtRQmfRBYO1qr0RZ/mnEUYCA83FDlXgx2X+EZuPsjPuwFUn82tX9C ov2TmGp2CsVrWbWQ1pzjpcRuiLYswc9k9/0/nyyyZteXkhaxp/qmtuf3h4fgbg71T1ja fhzMJ2B/jTEXYw/53ifyWAnLLVB/uPF3w8FcYR7si3/PtnXf4VW5gmrDVy8nXYRKwsvm Xrgqinc+Z/Cw36kI0HSt+kt+X9t5yorLtqVZBwy9iStjPzcwOrMupmcai3WX5MyG/tsN Oj9Q== X-Gm-Message-State: ANoB5pmE/TLC9oPgN/qSVX+5WdoYR8RFFS/4x8Uu0WUtSdh/BRyM7H3j JhNz8wRj3ovynwZYiA0WydOh9xZ8Jiqx9QYd X-Google-Smtp-Source: AA0mqf4NvmLzHSD1ba0I4817Mame5s4HpOlUb7W2psN02aQ6LkrQW0I0YeOlY4yRLNH+W+BUPIjnAw== X-Received: by 2002:a17:906:c1cc:b0:781:f54c:1947 with SMTP id bw12-20020a170906c1cc00b00781f54c1947mr14712594ejb.69.1668526070647; Tue, 15 Nov 2022 07:27:50 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id ku21-20020a170907789500b007ae1ab8f887sm5750679ejc.14.2022.11.15.07.27.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Nov 2022 07:27:50 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 8/9] arm64: dts: qcom: sm6375-pdx225: Configure SMD RPM regulators Date: Tue, 15 Nov 2022 16:27:26 +0100 Message-Id: <20221115152727.9736-9-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221115152727.9736-1-konrad.dybcio@linaro.org> References: <20221115152727.9736-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Configure regulators present on the Xperia 10 IV that are reachable via SMD RPM. Signed-off-by: Konrad Dybcio --- .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 182 ++++++++++++++++++ 1 file changed, 182 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index c830124cb483..0f1ddfa28c89 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -106,6 +106,188 @@ &qupv3_id_1 { status = "okay"; }; +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + pm6125_s5: s5 { + regulator-min-microvolt = <382000>; + regulator-max-microvolt = <1120000>; + }; + + pm6125_s6: s6 { + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <1374000>; + }; + + pm6125_s7: s7 { + regulator-min-microvolt = <1574000>; + regulator-max-microvolt = <2040000>; + }; + + /* + * S8 is VDD_GFX + * L1 is VDD_LPI_CX + */ + + pm6125_l2: l2 { + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l3: l3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + pm6125_l4: l4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + pm6125_l5: l5 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3050000>; + }; + + pm6125_l6: l6 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l7: l7 { + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + }; + + pm6125_l8: l8 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l9: l9 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + pm6125_l10: l10 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l11: l11 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l12: l12 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + pm6125_l13: l13 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l14: l14 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + pm6125_l15: l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + }; + + pm6125_l16: l16 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + /* L17 is VDD_LPI_MX */ + + pm6125_l18: l18 { + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + }; + + pm6125_l19: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l20: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l21: l21 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l22: l22 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + + pm6125_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l24: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pmr735a-regulators"; + + /* + * S1 is VDD_MX + * S2 is VDD_CX + */ + + pmr735a_l1: l1 { + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + }; + + pmr735a_l2: l2 { + regulator-min-microvolt = <352000>; + regulator-max-microvolt = <796000>; + }; + + pmr735a_l3: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + pmr735a_l4: l4 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + pmr735a_l5: l5 { + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + }; + + pmr735a_l6: l6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <868000>; + }; + + pmr735a_l7: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + }; +}; + &tlmm { gpio-reserved-ranges = <13 4>; }; From patchwork Tue Nov 15 15:27:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 624883 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12985C433FE for ; Tue, 15 Nov 2022 15:29:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231395AbiKOP3D (ORCPT ); Tue, 15 Nov 2022 10:29:03 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58462 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238280AbiKOP2M (ORCPT ); Tue, 15 Nov 2022 10:28:12 -0500 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5F4B2E69E for ; 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Tue, 15 Nov 2022 07:27:51 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 9/9] arm64: dts: qcom: sm6375-pdx225: Configure Samsung touchscreen Date: Tue, 15 Nov 2022 16:27:27 +0100 Message-Id: <20221115152727.9736-10-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221115152727.9736-1-konrad.dybcio@linaro.org> References: <20221115152727.9736-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a pretty bog-standard-for-Xperias-for-the-past-3-years touchscreen setup. The OEM that built the Xperia 10 IV for SONY decided to use some kind of a GPIO regulator that needs to be enabled at all times for both the touch panel and the display panel to function. Signed-off-by: Konrad Dybcio --- .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 0f1ddfa28c89..d18167bcb41f 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -81,6 +81,23 @@ &gpi_dma1 { status = "okay"; }; +&i2c8 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen@48 { + compatible = "samsung,s6sy761"; + reg = <0x48>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + + vdd-supply = <&pm6125_l13>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_default &ts_avdd_default>; + }; +}; + &pmk8350_adc_tm { status = "okay"; }; @@ -290,6 +307,20 @@ pmr735a_l7: l7 { &tlmm { gpio-reserved-ranges = <13 4>; + + ts_int_default: ts-int-default-state { + pins = "gpio22"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_avdd_default: ts-avdd-default-state { + pins = "gpio59"; + function = "gpio"; + drive-strength = <8>; + output-high; + }; }; &usb_1 {