From patchwork Tue Nov 15 17:28:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 624874 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EEAEC433FE for ; Tue, 15 Nov 2022 17:28:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231669AbiKOR2j (ORCPT ); Tue, 15 Nov 2022 12:28:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59522 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231644AbiKOR2i (ORCPT ); Tue, 15 Nov 2022 12:28:38 -0500 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CECB22B10 for ; Tue, 15 Nov 2022 09:28:37 -0800 (PST) Received: by mail-lj1-x229.google.com with SMTP id s24so18444283ljs.11 for ; Tue, 15 Nov 2022 09:28:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=liGvN8jbPDWPFBcKz2XKooL1E4NpfbDZme1QvgIlf+k=; b=aBh56Fch88bdtMiVczgOaevciiG2Ou1kl90Wi+0Ms9XJS+qjcYTMjQ0pLCoWeKCKdA d6qCTj28DcHhHhKJQxPswcE3OCQp55Mhbqy3YMnmc/NmX3lKydBG51H4fBNeFofo/WSR bBahM6bblHtU4cEhYFdIMAOyvA8Eg1saD68BoortJwnGcl1Eul8MAaaYW0f8xcogEKYu 0yn6w07XfD3N0vGMLMlALT+KoX0sskCAMx3o65l7SwaAngi9UIwpfwNgeWbmSbbo7pUb 41TU9sdiFPTB3TtP5MXVsj4kdWNko/+s6gSMQ0qW8bB7UUMc9l/2o7AiycGlm/OyUSFe Doig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=liGvN8jbPDWPFBcKz2XKooL1E4NpfbDZme1QvgIlf+k=; b=KOuAFhCfpPnutATTu9a5i5TGi6Jt7prQF1XEOsRdWVc5/jgJ24y/NowK8hWKKEuRGx EKj+Co/iFT0aHy+C5h7GoS+gxJOp3QAx5aopVX1wOeXEljcgss/7vERQOdGhepYBXuR4 wqY3MRX3pqb0Xr7Y9o9nD2Aoa6g/PyIahQaB8SncY1SRpS5qO6xeRwgTOR2QFBO5MQ37 kz19WzEc/MOzcxFeQAqt58fEstTsXLpmp/rxcTAUVnXuQ4dmgkw9yTBU7mEhgmpP5BJ8 q0CGo1Xj9fBvW+S/XpstQ0Vvk+dwViCUPFWDm41x56pl9fhiQvKmHZM4wQNQyFnQowMB nMeA== X-Gm-Message-State: ANoB5plghmq0cdbtbqXzlOskPSKW57u+GNIoZMtSg2g0OYNzyGYqUYYs AOaYH/VpDfKT+d914pchnK+myuKiaKWaxI/e X-Google-Smtp-Source: AA0mqf7kFYtoShG3Ec+K7wsHA+5VGZ4wbmkF5LBpCHRy/fXgPLFgn6vfYqCmvLICUQhXL/933z6vUA== X-Received: by 2002:a2e:300f:0:b0:277:7eef:1d97 with SMTP id w15-20020a2e300f000000b002777eef1d97mr6815192ljw.516.1668533315312; Tue, 15 Nov 2022 09:28:35 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id b42-20020a0565120baa00b00496d3e6b131sm2261511lfv.234.2022.11.15.09.28.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Nov 2022 09:28:34 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] dt-bindings: mmc: sdhci-msm: Document SM8350 SDHCI Date: Tue, 15 Nov 2022 18:28:25 +0100 Message-Id: <20221115172828.14372-1-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Document the SDHCI on SM8350. Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index 12def0f57e3e..31dfaff0048d 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -49,6 +49,7 @@ properties: - qcom,sm6375-sdhci - qcom,sm8150-sdhci - qcom,sm8250-sdhci + - qcom,sm8350-sdhci - qcom,sm8450-sdhci - const: qcom,sdhci-msm-v5 # for sdcc version 5.0 From patchwork Tue Nov 15 17:28:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 625645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF8B8C43217 for ; Tue, 15 Nov 2022 17:28:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231477AbiKOR2o (ORCPT ); Tue, 15 Nov 2022 12:28:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231723AbiKOR2k (ORCPT ); Tue, 15 Nov 2022 12:28:40 -0500 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA0A01D32D for ; Tue, 15 Nov 2022 09:28:38 -0800 (PST) Received: by mail-lf1-x136.google.com with SMTP id l12so25514592lfp.6 for ; Tue, 15 Nov 2022 09:28:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j5Zsxhl1TYkSTxNL/AaKGZ9xhkYvd+wyYJFAyYon0sM=; b=BMTj5Dak6W+WJH+TKdUOI2FV0SSmcOlhtNa8pLoMKG7SvhOIUFobG47saheBFT4egX abIUbjO5j64XvRfZbNDNZPJ5inwwZYFFrryFf5rC/ExXxi6+SdSuvfONWR3edjZFZSML JhS4nbHm0NAGBq71Qy909MdqoaLMuA8m+uql90no3Un+RIZBUPoU/6FL/EFI26sX17fW WZklZFyEiqKM69Ra9hE75X5+EHP55jo3WebwSjkVCDUkpixxcW2UBuTq1OCQb02ITFle sY5BBizcxCb2OlhHDatRvm/hEDPg3y2ZNS6MIsOJkJcjk/LtYJuqABIWKkfj+rygshhC pxdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j5Zsxhl1TYkSTxNL/AaKGZ9xhkYvd+wyYJFAyYon0sM=; b=Cj+Cno1rWTDsGMcKwU/N1xZidkfYtmwpTP0JyKCe7eI4r3zepglUMdjB/3f4xpcN5m PKJ6JUV9BiFrL0hFAhdnk+GzQxIo5I5yDGQ7KrLQ6rVioGAucE8MrXCzul5GJI6lA8vn 8FJ/lBpPKxtAr4DJRVG8BDAF2us6yS33A1MP8v9cTjFzSDQc9Y/6Ikmnh85tQf/1+Dcm d5h6n/VyWJZf85HUljCFGlqTvLJKLMim9rnembqQqhNXjy/WjGMKGzrd8lsu7QlHqL3F n96+d5hFfmjUcLKSdH3LvecQmMcvGOj241ocvg/44sf0xmm479uQzagyOcqGQixVZGeu cd6A== X-Gm-Message-State: ANoB5pmqlu+hq/hE9ezksuDsllgdXbuufCRsCL2h6O9XgRusP/7xnjUf ZmlVrMDrcJnXo2hgtB4Frk20EvFxHPt/rNiX X-Google-Smtp-Source: AA0mqf4HHR+TSuVMQPzoZGW2Uia1qZKNs1X6DTvzzrqBJa7wf2ZAxEgAOg8M2Hp7Xiecxvd2tj0YDw== X-Received: by 2002:a05:6512:312c:b0:4a2:1d18:45d8 with SMTP id p12-20020a056512312c00b004a21d1845d8mr5855145lfd.330.1668533316803; Tue, 15 Nov 2022 09:28:36 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id b42-20020a0565120baa00b00496d3e6b131sm2261511lfv.234.2022.11.15.09.28.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Nov 2022 09:28:36 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio Subject: [PATCH 2/4] arm64: dts: qcom: sm8350: Add SDHCI2 Date: Tue, 15 Nov 2022 18:28:26 +0100 Message-Id: <20221115172828.14372-2-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221115172828.14372-1-konrad.dybcio@linaro.org> References: <20221115172828.14372-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add and configure the SDHCI host responsible for (mostly) SD Card and its corresponding pins' sleep states. The setup is *literally* 1:1 with 8450 (bar SDR50/104 may not be broken). Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 79 ++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 552c0da3c479..9a118112facb 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1761,6 +1761,46 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 204>; wakeup-parent = <&pdc>; + sdc2_default_state: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <16>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <16>; + bias-pull-up; + }; + }; + + sdc2_sleep_state: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup_uart3_default_state: qup-uart3-default-state { rx-pins { pins = "gpio18"; @@ -2329,6 +2369,45 @@ compute-cb@8 { }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + resets = <&gcc GCC_SDCC2_BCR>; + interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; + iommus = <&apps_smmu 0x4a0 0x0>; + power-domains = <&rpmhpd SM8350_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + bus-width = <4>; + dma-coherent; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm8350-usb-hs-phy", "qcom,usb-snps-hs-7nm-phy"; From patchwork Tue Nov 15 17:28:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 624873 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33071C433FE for ; Tue, 15 Nov 2022 17:28:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231960AbiKOR2u (ORCPT ); Tue, 15 Nov 2022 12:28:50 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231792AbiKOR2m (ORCPT ); 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Tue, 15 Nov 2022 09:28:37 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio Subject: [PATCH 3/4] arm64: dts: qcom: sm8350-sagami: Add GPIO line names for TLMM Date: Tue, 15 Nov 2022 18:28:27 +0100 Message-Id: <20221115172828.14372-3-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221115172828.14372-1-konrad.dybcio@linaro.org> References: <20221115172828.14372-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Sony ever so graciously provides GPIO line names in their downstream kernel (though sometimes they are not 100% accurate and you can judge that by simply looking at them and with what drivers they are used). Add these to the Sagami-common / PDX215 DTSIs to better document the hardware. Diff between 215 and common: < "NC", < "NC", > "WLC_I2C_SDA", > "WLC_I2C_SCL", < "NC", > "WLC_INT_N", > "CAM_MCLK4", < "NC", < "NC", > "TOF_RST_N", < "NC", < "NC", < "NC", > "QLINK1_REQ", > "QLINK1_EN", > "QLINK1_WMSS_RESET_N", It's pretty logical as 1 III has WLC (WireLess Charging), and an additional 3D iToF sensor. As for QLINK, no idea. Signed-off-by: Konrad Dybcio --- .../qcom/sm8350-sony-xperia-sagami-pdx215.dts | 206 ++++++++++++++++++ .../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 203 +++++++++++++++++ 2 files changed, 409 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts index d21bbeb603a6..c74c973a69d2 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami-pdx215.dts @@ -11,3 +11,209 @@ / { model = "Sony Xperia 1 III"; compatible = "sony,pdx215-generic", "qcom,sm8350"; }; + +&tlmm { + gpio-line-names = "APPS_I2C_0_SDA", /* GPIO_0 */ + "APPS_I2C_0_SCL", + "UWIDEC_PWR_EN", + "HAP_RST_N", + "WLC_I2C_SDA", + "WLC_I2C_SCL", + "PM8008_1_RESET_N", + "WLC_INT_N", + "OIS_TELE_I2C_SDA", + "OIS_TELE_I2C_SCL", + "PM8350_OPTION", /* GPIO_10 */ + "NC", + "APPS_I2C_1_SDA", + "APPS_I2C_1_SCL", + "NC", + "NC", + "CAM1_RESET_N", + "LEO_CAM0_RESET_N", + "DEBUG_UART_TX", + "DEBUG_UART_RX", + "TS_I2C_SDA", /* GPIO_20 */ + "TS_I2C_SCL", + "TS_RESET_N", + "TS_INT_N", + "DISP_RESET_N", + "SW_SERVICE", + "DISP_ERR_FG", + "TX_GTR_THRES_IN", + "NC", + "NC", + "NC", /* GPIO_30 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "SPK_AMP_INT_N", + "SPK_AMP_RESET_N", + "FP_INT_N", + "FP_RESET_N", + "NC", /* GPIO_40 */ + "NC", + "DEBUG_GPIO0", + "FORCE_USB_BOOT", + "FP_SPI_MISO", + "FP_SPI_MOSI", + "FP_SPI_CLK", + "FP_SPI_CS_N", + "SPK_AMP_I2C_SDA", + "SPK_AMP_I2C_SCL", + "NC", /* GPIO_50 */ + "HAP_INT_N", + "CAMSENSOR_I2C_SDA", + "CAMSENSOR_I2C_SCL", + "SBU_SW_OE", + "SBU_SW_SEL", + "NFC_ESE_SPI_MISO", + "NFC_ESE_SPI_MOSI", + "NFC_ESE_SPI_CLK", + "NFC_ESE_SPI_CS", + "NFC_I2C_SDA", /* GPIO_60 */ + "NFC_I2C_SCL", + "NFC_EN", + "NFC_CLK_REQ", + "HST_WLAN_EN", + "HST_BT_EN", + "HW_ID_0", + "HW_ID_1", + "HST_BT_UART_CTS", + "HST_BT_UART_RFR", + "HST_BT_UART_TX", /* GPIO_70 */ + "HST_BT_UART_RX", + "HAP_I2C_SDA", + "HAP_I2C_SCL", + "RF_LCD_ID_EN", + "RF_ID_EXTENSION", + "NC", + "NC", + "NC", + "NC", + "HALL_INT_N", /* GPIO_80 */ + "USB_CC_DIR", + "DISP_VSYNC", + "NC", + "NC", + "CAM_SOF_TELE", + "NFC_DWL_REQ", + "NFC_IRQ", + "WCD_RST_N", + "ALS_PROX_INT_N", + "NC", /* GPIO_90 */ + "NC", + "TRAY_DET", + "UDON_SWITCH_SEL", + "PCIE0_RESET_N", + "PCIE0_CLK_REQ_N", + "PCIE0_WAKE_N", + "CAM_SOF", + "RF_ID_EXTENSION_2", + "RGBC_IR_INT", + "CAM_MCLK0", /* GPIO_100 */ + "CAM_MCLK1", + "CAM_MCLK2", + "CAM_MCLK3", + "CAM_MCLK4", + "NC", + "CAM2_RESET_N", + "CCI_I2C0_SDA", + "CCI_I2C0_SCL", + "CCI_I2C1_SDA", + "CCI_I2C1_SCL", /* GPIO_110 */ + "CCI_I2C2_SDA", + "CCI_I2C2_SCL", + "CCI_I2C3_SDA", + "CCI_I2C3_SCL", + "NC", + "PM8008_1_IRQ", + "CAM3_RESET_N", + "IMU1_INT", + "EXT_VD0_XVS", + "NC", /* GPIO_120 */ + "NC", + "NC", + "NC", + "NC", + "HAP_I2S_CLK", + "HAP_I2S_DOUT", + "HAP_TRG1", + "HAP_I2S_SYNC", + "HST_BT_WLAN_SLIMBUS_CLK", + "HST_BT_WLAN_SLIMBUS_DAT0", /* GPIO_130 */ + "NC", + "UIM2_DETECT_EN", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RESET", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RESET", + "TRAY_DET", /* GPIO_140 */ + "SM_RFFE0_CLK", + "SM_RFFE0_DATA", + "SM_RFFE1_CLK", + "SM_RFFE1_DATA", + "SM_MSS_GRFC4", + "SM_MSS_GRFC5", + "SM_MSS_GRFC6", + "SM_MSS_GRFC7", + "SM_RFFE4_CLK", + "SM_RFFE4_DATA", /* GPIO_150 */ + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "HST_SW_CTRL", + "DISP_VDDR_EN", + "NC", + "NC", + "PA_INDICATOR_OR", + "TOF_RST_N", + "QLINK0_REQ", + "QLINK0_EN", /* GPIO_160 */ + "QLINK0_WMSS_RESET_N", + "QLINK1_REQ", + "QLINK1_EN", + "QLINK1_WMSS_RESET_N", + "PM8008_2_IRQ", + "TELEC_PWR_EN", + "PM8008_2_RESET_N", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", /* GPIO_170 */ + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + "SM_DMIC1_CLK", + "SM_DMIC1_DATA", + "SM_DMIC2_CLK", + "SM_DMIC2_DATA", + "SPK_AMP_I2S_CLK", + "SPK_AMP_I2S_WS", + "SPK_AMP_I2S_ASP_DIN", /* GPIO_180 */ + "SPK_AMP_I2S_ASP_DOUT", + "WCD_SWR_TX_DATA2", + "NC", + "NC", + "NC", + "NC", + "IMU_SPI_MISO", + "IMU_SPI_MOSI", + "IMU_SPI_CLK", + "IMU_SPI_CS_N", /* GPIO_190 */ + "MAG_I2C_SDA", + "MAG_I2C_SCL", + "SENSOR_I2C_SDA", + "SENSOR_I2C_SCL", + "NC", + "NC", + "NC", + "NC", + "HST_BLE_UART_TX", + "HST_BLE_UART_RX", /* GPIO_200 */ + "HST_WLAN_UART_TX", + "HST_WLAN_UART_RX"; +}; diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index dab5145358e7..a428ce31ab4e 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -571,6 +571,209 @@ &spi14 { &tlmm { gpio-reserved-ranges = <44 4>; + gpio-line-names = "APPS_I2C_0_SDA", /* GPIO_0 */ + "APPS_I2C_0_SCL", + "UWIDEC_PWR_EN", + "HAP_RST_N", + "NC", + "NC", + "PM8008_1_RESET_N", + "NC", + "OIS_TELE_I2C_SDA", + "OIS_TELE_I2C_SCL", + "PM8350_OPTION", /* GPIO_10 */ + "NC", + "APPS_I2C_1_SDA", + "APPS_I2C_1_SCL", + "NC", + "NC", + "CAM1_RESET_N", + "LEO_CAM0_RESET_N", + "DEBUG_UART_TX", + "DEBUG_UART_RX", + "TS_I2C_SDA", /* GPIO_20 */ + "TS_I2C_SCL", + "TS_RESET_N", + "TS_INT_N", + "DISP_RESET_N", + "SW_SERVICE", + "DISP_ERR_FG", + "TX_GTR_THRES_IN", + "NC", + "NC", + "NC", /* GPIO_30 */ + "NC", + "NC", + "NC", + "NC", + "NC", + "SPK_AMP_INT_N", + "SPK_AMP_RESET_N", + "FP_INT_N", + "FP_RESET_N", + "NC", /* GPIO_40 */ + "NC", + "DEBUG_GPIO0", + "FORCE_USB_BOOT", + "FP_SPI_MISO", + "FP_SPI_MOSI", + "FP_SPI_CLK", + "FP_SPI_CS_N", + "SPK_AMP_I2C_SDA", + "SPK_AMP_I2C_SCL", + "NC", /* GPIO_50 */ + "HAP_INT_N", + "CAMSENSOR_I2C_SDA", + "CAMSENSOR_I2C_SCL", + "SBU_SW_OE", + "SBU_SW_SEL", + "NFC_ESE_SPI_MISO", + "NFC_ESE_SPI_MOSI", + "NFC_ESE_SPI_CLK", + "NFC_ESE_SPI_CS", + "NFC_I2C_SDA", /* GPIO_60 */ + "NFC_I2C_SCL", + "NFC_EN", + "NFC_CLK_REQ", + "HST_WLAN_EN", + "HST_BT_EN", + "HW_ID_0", + "HW_ID_1", + "HST_BT_UART_CTS", + "HST_BT_UART_RFR", + "HST_BT_UART_TX", /* GPIO_70 */ + "HST_BT_UART_RX", + "HAP_I2C_SDA", + "HAP_I2C_SCL", + "RF_LCD_ID_EN", + "RF_ID_EXTENSION", + "NC", + "NC", + "NC", + "NC", + "HALL_INT_N", /* GPIO_80 */ + "USB_CC_DIR", + "DISP_VSYNC", + "NC", + "NC", + "CAM_SOF_TELE", + "NFC_DWL_REQ", + "NFC_IRQ", + "WCD_RST_N", + "ALS_PROX_INT_N", + "NC", /* GPIO_90 */ + "NC", + "TRAY_DET", + "UDON_SWITCH_SEL", + "PCIE0_RESET_N", + "PCIE0_CLK_REQ_N", + "PCIE0_WAKE_N", + "CAM_SOF", + "RF_ID_EXTENSION_2", + "RGBC_IR_INT", + "CAM_MCLK0", /* GPIO_100 */ + "CAM_MCLK1", + "CAM_MCLK2", + "CAM_MCLK3", + "NC", + "NC", + "CAM2_RESET_N", + "CCI_I2C0_SDA", + "CCI_I2C0_SCL", + "CCI_I2C1_SDA", + "CCI_I2C1_SCL", /* GPIO_110 */ + "CCI_I2C2_SDA", + "CCI_I2C2_SCL", + "CCI_I2C3_SDA", + "CCI_I2C3_SCL", + "NC", + "PM8008_1_IRQ", + "CAM3_RESET_N", + "IMU1_INT", + "EXT_VD0_XVS", + "NC", /* GPIO_120 */ + "NC", + "NC", + "NC", + "NC", + "HAP_I2S_CLK", + "HAP_I2S_DOUT", + "HAP_TRG1", + "HAP_I2S_SYNC", + "HST_BT_WLAN_SLIMBUS_CLK", + "HST_BT_WLAN_SLIMBUS_DAT0", /* GPIO_130 */ + "NC", + "UIM2_DETECT_EN", + "UIM2_DATA", + "UIM2_CLK", + "UIM2_RESET", + "UIM2_PRESENT", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RESET", + "TRAY_DET", /* GPIO_140 */ + "SM_RFFE0_CLK", + "SM_RFFE0_DATA", + "SM_RFFE1_CLK", + "SM_RFFE1_DATA", + "SM_MSS_GRFC4", + "SM_MSS_GRFC5", + "SM_MSS_GRFC6", + "SM_MSS_GRFC7", + "SM_RFFE4_CLK", + "SM_RFFE4_DATA", /* GPIO_150 */ + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "HST_SW_CTRL", + "DISP_VDDR_EN", + "NC", + "NC", + "PA_INDICATOR_OR", + "NC", + "QLINK0_REQ", + "QLINK0_EN", /* GPIO_160 */ + "QLINK0_WMSS_RESET_N", + "NC", + "NC", + "NC", + "PM8008_2_IRQ", + "TELEC_PWR_EN", + "PM8008_2_RESET_N", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", /* GPIO_170 */ + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + "SM_DMIC1_CLK", + "SM_DMIC1_DATA", + "SM_DMIC2_CLK", + "SM_DMIC2_DATA", + "SPK_AMP_I2S_CLK", + "SPK_AMP_I2S_WS", + "SPK_AMP_I2S_ASP_DIN", /* GPIO_180 */ + "SPK_AMP_I2S_ASP_DOUT", + "WCD_SWR_TX_DATA2", + "NC", + "NC", + "NC", + "NC", + "IMU_SPI_MISO", + "IMU_SPI_MOSI", + "IMU_SPI_CLK", + "IMU_SPI_CS_N", /* GPIO_190 */ + "MAG_I2C_SDA", + "MAG_I2C_SCL", + "SENSOR_I2C_SDA", + "SENSOR_I2C_SCL", + "NC", + "NC", + "NC", + "NC", + "HST_BLE_UART_TX", + "HST_BLE_UART_RX", /* GPIO_200 */ + "HST_WLAN_UART_TX", + "HST_WLAN_UART_RX"; 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Tue, 15 Nov 2022 09:28:39 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Bhupesh Sharma , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio Subject: [PATCH 4/4] arm64: dts: qcom: sm8350-sagami: Wire up SDHCI2 Date: Tue, 15 Nov 2022 18:28:28 +0100 Message-Id: <20221115172828.14372-4-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221115172828.14372-1-konrad.dybcio@linaro.org> References: <20221115172828.14372-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Adjust regulators, add required pin setup and finally enable SDHCI2 to get the SD Card slot going on Sagami Xperias. Signed-off-by: Konrad Dybcio --- .../dts/qcom/sm8350-sony-xperia-sagami.dtsi | 30 ++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi index a428ce31ab4e..fdf95b763cf4 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350-sony-xperia-sagami.dtsi @@ -312,7 +312,8 @@ pm8350c_l8: ldo8 { pm8350c_l9: ldo9 { regulator-name = "pm8350c_l9"; regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <3008000>; + /* Originally max = 3008000 but SDHCI expects 2960000 */ + regulator-max-microvolt = <2960000>; regulator-initial-mode = ; }; @@ -558,6 +559,19 @@ &qupv3_id_2 { status = "okay"; }; +&sdhc_2 { + cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_default_state &sdc2_card_det_active>; + pinctrl-1 = <&sdc2_sleep_state &sdc2_card_det_sleep>; + vmmc-supply = <&pm8350c_l9>; + vqmmc-supply = <&pm8350c_l6>; + no-sdio; + no-mmc; + status = "okay"; +}; + + &slpi { status = "okay"; firmware-name = "qcom/sm8350/Sony/sagami/slpi.mbn"; @@ -782,6 +796,20 @@ ts_int_default: ts-int-default-state { bias-disable; input-enable; }; + + sdc2_card_det_active: sd-card-det-active-state { + pins = "gpio92"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + sdc2_card_det_sleep: sd-card-det-sleep-state { + pins = "gpio92"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; }; /* BIG WARNING! DO NOT TOUCH UFS, YOUR DEVICE WILL DIE! */