From patchwork Mon Nov 14 10:42:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 624609 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26D9DC433FE for ; Mon, 14 Nov 2022 10:42:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236100AbiKNKmi (ORCPT ); Mon, 14 Nov 2022 05:42:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236081AbiKNKmh (ORCPT ); Mon, 14 Nov 2022 05:42:37 -0500 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 821E21DDDC for ; Mon, 14 Nov 2022 02:42:36 -0800 (PST) Received: by mail-lj1-x235.google.com with SMTP id u11so12550167ljk.6 for ; Mon, 14 Nov 2022 02:42:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zDzwDb0dnKoTPgCy4RBfiMpDFetmXY9OEGk9SR/WSLY=; b=FhlApcqDxCtCoupJ/TIS0Ykf65afLK30ejNB8v2zhMO/08W/KJGjo+jBHJsNqt10pm 1GEqKtYy830ohGlIM91yJZR6N3HiLjwX/ldBqlIKM5vXM3kFSN+2IIvvYOj+qJ87LRfI dzDH0BAB4MOhdYEyvZ3udJabwEej8WLG14Mgf1O8L/LxHKjVqaxAvZpwi12vdDcBIVpu SuIQrLXvLUodif/creo1nAh7wOM3vGtIU/3ALCYbvqgi8SSmbsONxt+v709lJdR5zYEw fxJFr0c9PqfemGYKmEEvkXXlRTEeFlBCxfFC6xv+x98BZlO64aBbZ6833hVafWVYTAYD 0eZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zDzwDb0dnKoTPgCy4RBfiMpDFetmXY9OEGk9SR/WSLY=; b=lnA8m7uvftxaBIaVZdLtBfvPMcypQI9dv0QHgnZy6FqXzf8W6WvUXM9Pb9hDO6l/EI 3vGmoGB0+wQ6iVHljQlK3oVmvw9iYtkmqKot3Y0nlr6fwsZPdhQelZr23ZlhyBI8Hro3 TbQmULOsJWtkd5GD3Cad2anE5EFsw8Ttv6ITpfo++8fFj/zftbM3M55FACxRJg6bqavr y/1mOZeoqDD47dgCDJVhxgW7oOEw3vUB61uScjEV+04if9it/QiCeo6ciwy9k2L4pgQT qU4YIRumbQntHdpkDCjauxbgfkaAcpgkUVDXdhsmcZrFOteT1iCOuishSKygjawuWiye NBow== X-Gm-Message-State: ANoB5plVsCtdwklsyjb44JRIuDWld38y1PZ6WKxcyhqOJLoVbHyLlh2Y WPp9Q0d9jLcSpVWvKodOu6AvuYKFoCs+R3Yu X-Google-Smtp-Source: AA0mqf4qlxiMY3JDejy6a3SVEFC3TJHChXsZGfocnkqWhpRLRNPJLTzvyucW4mkNtj7j0c1yswAz8g== X-Received: by 2002:a2e:960d:0:b0:277:4f:bd2a with SMTP id v13-20020a2e960d000000b00277004fbd2amr3622765ljh.341.1668422554455; Mon, 14 Nov 2022 02:42:34 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id bs21-20020a05651c195500b0026c4e922fb2sm1946486ljb.48.2022.11.14.02.42.33 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 14 Nov 2022 02:42:34 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/9] dt-bindings: arm-smmu: Allow up to 3 power-domains Date: Mon, 14 Nov 2022 11:42:14 +0100 Message-Id: <20221114104222.36329-2-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221114104222.36329-1-konrad.dybcio@linaro.org> References: <20221114104222.36329-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some SMMUs require that a vote is held on as much as 3 separate PDs (hello Qualcomm). Allow it in bindings. Signed-off-by: Konrad Dybcio --- Changes since v1: - Add minItems Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 9066e6df1ba1..82bc696de662 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -159,7 +159,8 @@ properties: through the TCU's programming interface. power-domains: - maxItems: 1 + minItems: 0 + maxItems: 3 nvidia,memory-controller: description: | From patchwork Mon Nov 14 10:42:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 624608 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7AA5C4321E for ; Mon, 14 Nov 2022 10:42:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236155AbiKNKmk (ORCPT ); Mon, 14 Nov 2022 05:42:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235997AbiKNKmi (ORCPT ); Mon, 14 Nov 2022 05:42:38 -0500 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFB561EAF8 for ; Mon, 14 Nov 2022 02:42:37 -0800 (PST) Received: by mail-lj1-x236.google.com with SMTP id a15so12574798ljb.7 for ; Mon, 14 Nov 2022 02:42:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pefehE5o4ZbEpfgRDd+vWut5SWgW8/RYnVz1s2zWHXE=; b=uZuLqwtgmf+J1MWVvHIF9VmWJb6tLA0c/U0YPCM+7e/Uzfzb5lPasX+IC3yfp2iNKh uVtkvGdNj2j7jTGo+dI+dxfd8wpCOJXuSxYnZ8TGMs/oObT6unEB2szR5Zt9iuaXvcKO Y0y6cWkeUbTl/hSMoDgVU+QC+0OLIDR5o0J4I7jHRNgYSDo31yYydomF4DjwHxLmMw7G 5aF0w6g8YhcbliXFeZ/CVEBdt57OAkXRW1tFbBjptCwMr5BQVzKuRjjazaZDFx5zvP/4 74rLHZc6hiVV32ghjXANyOpaqURNX5Mba7WlDr+Zj+ArfBcX5phE+xtssV35aT/JTtnn UUjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pefehE5o4ZbEpfgRDd+vWut5SWgW8/RYnVz1s2zWHXE=; b=NYjB5lECwb3gecLSJMGvFAeHm0Q/AZlVSpcTeY4OhB9Rs5Y74OoKrIdkrQ8z8AzAvo DnjMhWZtPaTttwVBhTQHBVg+UsV8kvHfyFtn1NtG5nWa4SPcvvmDiKxlJ9Lh5EYTu+P4 duMwwO+pT/6YaxPMtVokIhq0pXN9eBM+U7nQdq+fDx3rsSev8WV9/AoduwOjIEtsX0wv MwADcfgbPo8UfvhsNNrY7Zg9P2EczDl+w4dszBagePWQSYhz9VZw9q3xkWe8hWY7qSeB EjqtgPGyTkKZT5IyZvCKBpMZK720UVTXu5sqqpSFAzOZP5mYJlIL+T5eTqWJ8hMMDDJo oWAA== X-Gm-Message-State: ANoB5pnsCMjIvkcNLzRL6+nf97Jo67rgARwj3yRaRhSIFcLjLWDoO+6S KVwOEV1lV17pniw1Ruyp9iCQS44QEdZGpSTs X-Google-Smtp-Source: AA0mqf7/mUQ/mfjgdPLxhttxA/2in9O16AdY2CR6UlT6O2LaPLs3Ls2ZD6tUWXwDycZWnL+CFHmV2A== X-Received: by 2002:a05:651c:104e:b0:26f:bf09:2f57 with SMTP id x14-20020a05651c104e00b0026fbf092f57mr3642094ljm.180.1668422555818; Mon, 14 Nov 2022 02:42:35 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id bs21-20020a05651c195500b0026c4e922fb2sm1946486ljb.48.2022.11.14.02.42.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 14 Nov 2022 02:42:35 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Dmitry Baryshkov , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/9] arm64: dts: qcom: pmk8350: Allow specifying arbitrary SID Date: Mon, 14 Nov 2022 11:42:15 +0100 Message-Id: <20221114104222.36329-3-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221114104222.36329-1-konrad.dybcio@linaro.org> References: <20221114104222.36329-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org PMK8350 is shipped on SID6 with some SoCs, for example with SM6375. Add some preprocessor logic to allow changing the SID in cases like this. While I am not in favour of adding #if's into the device tree, this is the least messy way to handle this. If one isn't specified, it will default to 0 (as it has been previously). Suggested-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- Changes since v1: - take a different approach; patch substituted arch/arm64/boot/dts/qcom/pmk8350.dtsi | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi index a7ec9d11946d..2730d97ab213 100644 --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi @@ -8,10 +8,15 @@ #include #include +/* (Sadly) this PMIC can be configured to be at different SIDs */ +#ifndef PMK8350_SID + #define PMK8350_SID 0 +#endif + &spmi_bus { - pmk8350: pmic@0 { + pmk8350: pmic@PMK8350_SID { compatible = "qcom,pmk8350", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; + reg = ; #address-cells = <1>; #size-cells = <0>; @@ -21,14 +26,14 @@ pmk8350_pon: pon@1300 { pon_pwrkey: pwrkey { compatible = "qcom,pmk8350-pwrkey"; - interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + interrupts = ; linux,code = ; status = "disabled"; }; pon_resin: resin { compatible = "qcom,pmk8350-resin"; - interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupts = ; status = "disabled"; }; }; @@ -38,14 +43,14 @@ pmk8350_vadc: adc@3100 { reg = <0x3100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupts = ; #io-channel-cells = <1>; }; pmk8350_adc_tm: adc-tm@3400 { compatible = "qcom,adc-tm7"; reg = <0x3400>; - interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; @@ -56,7 +61,7 @@ pmk8350_rtc: rtc@6100 { compatible = "qcom,pmk8350-rtc"; reg = <0x6100>, <0x6200>; reg-names = "rtc", "alarm"; - interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + interrupts = ; status = "disabled"; }; From patchwork Mon Nov 14 10:42:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 625736 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B671C43217 for ; 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Mon, 14 Nov 2022 02:42:36 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/9] arm64: dts: qcom: sm6375: Add GPI DMA nodes Date: Mon, 14 Nov 2022 11:42:16 +0100 Message-Id: <20221114104222.36329-4-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221114104222.36329-1-konrad.dybcio@linaro.org> References: <20221114104222.36329-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add nodes for GPI DMA hosts on SM6375. Signed-off-by: Konrad Dybcio --- No changes since v1. arch/arm64/boot/dts/qcom/sm6375.dtsi | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 9b1a497e5ca7..62a64dd731a0 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -567,6 +567,46 @@ rpm_msg_ram: sram@45f0000 { reg = <0 0x045f0000 0 0x7000>; }; + gpi_dma0: dma-controller@4a00000 { + compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x04a00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0x16 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + + gpi_dma1: dma-controller@4c00000 { + compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x04c00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0xd6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + usb_1: usb@4ef8800 { compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; reg = <0 0x04ef8800 0 0x400>; From patchwork Mon Nov 14 10:42:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 625735 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85650C43217 for ; Mon, 14 Nov 2022 10:42:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236201AbiKNKmn (ORCPT ); Mon, 14 Nov 2022 05:42:43 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236190AbiKNKml (ORCPT ); Mon, 14 Nov 2022 05:42:41 -0500 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 945601A22E for ; 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Mon, 14 Nov 2022 02:42:38 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/9] arm64: dts: qcom: sm6375: Add pin configs for some QUP configurations Date: Mon, 14 Nov 2022 11:42:17 +0100 Message-Id: <20221114104222.36329-5-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221114104222.36329-1-konrad.dybcio@linaro.org> References: <20221114104222.36329-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the pin setup for SPI/I2C configurations that are supported downstream. I can guesstimate the correct settings for other buses, but: - I have no hardware to test it on - Some QUPs are straight up missing pin funcs in TLMM - Vendors probably didn't really care and used whatever was there in the reference design and BSP - should any other be used, they can be configured at a later time Acked-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- Changes since v1: - pick up a-b arch/arm64/boot/dts/qcom/sm6375.dtsi | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 62a64dd731a0..952156891476 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -519,6 +519,49 @@ tlmm: pinctrl@500000 { gpio-controller; #interrupt-cells = <2>; #gpio-cells = <2>; + + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup00"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio61", "gpio62"; + function = "qup01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio45", "gpio46"; + function = "qup02"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio19", "gpio20"; + /* TLMM, GCC and vendor DT all have different indices.. */ + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio4", "gpio5"; + function = "qup10"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qup00"; + drive-strength = <6>; + bias-disable; + }; }; gcc: clock-controller@1400000 { From patchwork Mon Nov 14 10:42:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 624606 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B6140C4332F for ; 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Mon, 14 Nov 2022 02:42:39 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/9] arm64: dts: qcom: sm6375: Add QUPs and corresponding SPI/I2C hosts Date: Mon, 14 Nov 2022 11:42:18 +0100 Message-Id: <20221114104222.36329-6-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221114104222.36329-1-konrad.dybcio@linaro.org> References: <20221114104222.36329-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add necessary nodes to support various QUP configurations. Note that: - QUP3/4/5 and 11 are straight up missing - There may be more QUPs physically on the SoC that work perfectly fine, but Qualcomm decided not to expose them on the downstream kernel - Many are missing pinctrls, as there are both missing pin funcs in the TLMM driver and missing configuration settings (though they are possible to guesstimate quite easily) Signed-off-by: Konrad Dybcio --- No changes since v1. arch/arm64/boot/dts/qcom/sm6375.dtsi | 306 +++++++++++++++++++++++++++ 1 file changed, 306 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 952156891476..6adffd927a8e 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -317,6 +318,25 @@ CLUSTER_PD: cpu-cluster0 { }; }; + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -630,6 +650,125 @@ gpi_dma0: dma-controller@4a00000 { status = "disabled"; }; + qupv3_id_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04ac0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_default>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@4a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* + * As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream. + * There is a comment in the included DTSI of another SoC saying that they + * are not "bolled out" (probably meaning not routed to solder balls) + * TLMM driver however, suggests there are as many as 15 QUPs in total! + * Most of which don't even have pin configurations for.. Sad stuff! + */ + }; + gpi_dma1: dma-controller@4c00000 { compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x04c00000 0 0x60000>; @@ -650,6 +789,173 @@ gpi_dma1: dma-controller@4c00000 { status = "disabled"; }; + qupv3_id_1: geniqup@4cc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04cc0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xc3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c6: i2c@4c80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@4c80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@4c84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi7: spi@4c84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@4c88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_default>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi8: spi@4c88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@4c8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@4c8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c10: i2c@4c90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_default>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi10: spi@4c90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + usb_1: usb@4ef8800 { compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; reg = <0 0x04ef8800 0 0x400>; From patchwork Mon Nov 14 10:42:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 624607 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72E73C43217 for ; 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Mon, 14 Nov 2022 02:42:41 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/9] arm64: dts: qcom: sm6375-pdx225: Enable QUPs & GPI DMA Date: Mon, 14 Nov 2022 11:42:19 +0100 Message-Id: <20221114104222.36329-7-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221114104222.36329-1-konrad.dybcio@linaro.org> References: <20221114104222.36329-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable QUPs & GPI DMA on the Xperia 10 IV. Signed-off-by: Konrad Dybcio --- No changes since v1. .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 450d4a557df1..6a0f4c0bf7ad 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -65,6 +65,22 @@ vph_pwr: vph-pwr-regulator { }; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <13 4>; }; From patchwork Mon Nov 14 10:42:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 625734 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36CBAC433FE for ; Mon, 14 Nov 2022 10:42:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236260AbiKNKm5 (ORCPT ); Mon, 14 Nov 2022 05:42:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236248AbiKNKmq (ORCPT ); Mon, 14 Nov 2022 05:42:46 -0500 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E6B61EAF8 for ; Mon, 14 Nov 2022 02:42:45 -0800 (PST) Received: by mail-lf1-x12f.google.com with SMTP id g7so18577839lfv.5 for ; Mon, 14 Nov 2022 02:42:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NIxBbSjNtdNlSWQ1P+SfGBLDhzhPep7hpCHZEsAxTUk=; b=cZew1Zo/v+y0TYowOujeDuQ6IMFAccM4Fk4rgARNNELs8jbhX9zOOlAMT6fP0UV0Qg UBssnbX7FVkEnWgEwY4pAFPOb5NhBcjV96Mznq6b14alBUC7hjbBewJBWBCcjE64T60z VBska7KI4+ixo/F17+RxzTECpjja5fZDgRhp9ZO2OLXy45Q7riSAKcNtBcj10OH7imKd pjZXb98tmeYGiVaylNHiXZSDFiobM5NdSgr9e0Ymyn92g7GdRWjG8sL9XTG/0erzLHPi S3gQ5sxYDM26bBjgUS2P2+Nsg1YOuSpxSGYmvfDEIMImDQaKdaf4EYWWQbZZA2iziDR2 kdEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NIxBbSjNtdNlSWQ1P+SfGBLDhzhPep7hpCHZEsAxTUk=; b=kOtIJqyEJpom/DYIu4nElpiDAZ/xpsF7J0OACMG8qYaqv5oh3uR9cHDbIvQFC0itC/ EdtX9BemhyHKs+B7RlQBx37yhTkwqAyiaMTPkepKJ8lFYZ/H5UfpTiu1mKXTCCoMKTY5 y6x3Iv9GyuTr1pJMtA9PUYzIklY5NQdFBh2qVq7vPSKrNAZ0s01FBbCBAvIzBD7gHJ1c 4sBlRL/GGouslTiA1TexKlvAvAQTE3iC+KLzDoDZawSwEG0N1KHdUUhpqZcihW3UuLGn G2aCJHsz2wyLLQcZJVYM8bCwEynT51+wuoHUtnNI/t6nrwxPeSf9ExTJtxnOD5lmEWM0 wL4Q== X-Gm-Message-State: ANoB5pk56zulGeYZpB/q+LvS+SQ/kh2BOAInN02tBl4/T/VDq8UjV77R ijoe6yF5dXcR4nqpdA+mJeFbDbVxAn6nTvb9 X-Google-Smtp-Source: AA0mqf79KXLBqXhHHaUBl+c9s+DAYlYJocR1z2m9OZukhhoQomWB738w3lzBIlcN3tIBWFZ5EO+tjw== X-Received: by 2002:a19:5e01:0:b0:4ab:4241:80c2 with SMTP id s1-20020a195e01000000b004ab424180c2mr3675107lfb.207.1668422563165; Mon, 14 Nov 2022 02:42:43 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id bs21-20020a05651c195500b0026c4e922fb2sm1946486ljb.48.2022.11.14.02.42.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 14 Nov 2022 02:42:42 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 7/9] arm64: dts: qcom: sm6375-pdx225: Add PMIC peripherals Date: Mon, 14 Nov 2022 11:42:20 +0100 Message-Id: <20221114104222.36329-8-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221114104222.36329-1-konrad.dybcio@linaro.org> References: <20221114104222.36329-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add and enable PMIC peripherals for PM6125, PMR735a and PMK8350 on the Xperia 10 IV. Signed-off-by: Konrad Dybcio --- Changes since v1: - configure PMK8350 SID .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 6a0f4c0bf7ad..c830124cb483 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -5,10 +5,18 @@ /dts-v1/; +/* PMK8350 is configured to use SID6 instead of 0 */ +#define PMK8350_SID 6 + #include #include "sm6375.dtsi" +#include "pm6125.dtsi" +#include "pmk8350.dtsi" #include "pmr735a.dtsi" +/* PM6125 PON is used and we can't have duplicate labels */ +/delete-node/ &pmk8350_pon; + / { model = "Sony Xperia 10 IV"; compatible = "sony,pdx225", "qcom,sm6375"; @@ -73,6 +81,23 @@ &gpi_dma1 { status = "okay"; }; +&pmk8350_adc_tm { + status = "okay"; +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; From patchwork Mon Nov 14 10:42:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 625733 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE6C3C4321E for ; Mon, 14 Nov 2022 10:43:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236318AbiKNKnA (ORCPT ); Mon, 14 Nov 2022 05:43:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236319AbiKNKmr (ORCPT ); Mon, 14 Nov 2022 05:42:47 -0500 Received: from mail-lj1-x22e.google.com (mail-lj1-x22e.google.com [IPv6:2a00:1450:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 945091FCC3 for ; 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Mon, 14 Nov 2022 02:42:44 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 8/9] arm64: dts: qcom: sm6375-pdx225: Configure SMD RPM regulators Date: Mon, 14 Nov 2022 11:42:21 +0100 Message-Id: <20221114104222.36329-9-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221114104222.36329-1-konrad.dybcio@linaro.org> References: <20221114104222.36329-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Configure regulators present on the Xperia 10 IV that are reachable via SMD RPM. Signed-off-by: Konrad Dybcio --- Changes since v1: - sort the node properly (alphabet is hard, I know..) .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 182 ++++++++++++++++++ 1 file changed, 182 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index c830124cb483..0f1ddfa28c89 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -106,6 +106,188 @@ &qupv3_id_1 { status = "okay"; }; +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + pm6125_s5: s5 { + regulator-min-microvolt = <382000>; + regulator-max-microvolt = <1120000>; + }; + + pm6125_s6: s6 { + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <1374000>; + }; + + pm6125_s7: s7 { + regulator-min-microvolt = <1574000>; + regulator-max-microvolt = <2040000>; + }; + + /* + * S8 is VDD_GFX + * L1 is VDD_LPI_CX + */ + + pm6125_l2: l2 { + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l3: l3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + pm6125_l4: l4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + pm6125_l5: l5 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3050000>; + }; + + pm6125_l6: l6 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l7: l7 { + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + }; + + pm6125_l8: l8 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l9: l9 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + pm6125_l10: l10 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l11: l11 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l12: l12 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + pm6125_l13: l13 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l14: l14 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + pm6125_l15: l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + }; + + pm6125_l16: l16 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + /* L17 is VDD_LPI_MX */ + + pm6125_l18: l18 { + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + }; + + pm6125_l19: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l20: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l21: l21 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l22: l22 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + + pm6125_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l24: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pmr735a-regulators"; + + /* + * S1 is VDD_MX + * S2 is VDD_CX + */ + + pmr735a_l1: l1 { + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + }; + + pmr735a_l2: l2 { + regulator-min-microvolt = <352000>; + regulator-max-microvolt = <796000>; + }; + + pmr735a_l3: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + pmr735a_l4: l4 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + pmr735a_l5: l5 { + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + }; + + pmr735a_l6: l6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <868000>; + }; + + pmr735a_l7: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + }; +}; + &tlmm { gpio-reserved-ranges = <13 4>; }; From patchwork Mon Nov 14 10:42:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 624605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32701C433FE for ; Mon, 14 Nov 2022 10:43:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236478AbiKNKnB (ORCPT ); Mon, 14 Nov 2022 05:43:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236324AbiKNKmr (ORCPT ); Mon, 14 Nov 2022 05:42:47 -0500 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A1BF1FCCA for ; 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Mon, 14 Nov 2022 02:42:45 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 9/9] arm64: dts: qcom: sm6375-pdx225: Configure Samsung touchscreen Date: Mon, 14 Nov 2022 11:42:22 +0100 Message-Id: <20221114104222.36329-10-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221114104222.36329-1-konrad.dybcio@linaro.org> References: <20221114104222.36329-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a pretty bog-standard-for-Xperias-for-the-past-3-years touchscreen setup. The OEM that built the Xperia 10 IV for SONY decided to use some kind of a GPIO regulator that needs to be enabled at all times for both the touch panel and the display panel to function. Signed-off-by: Konrad Dybcio --- No changes since v1. .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 0f1ddfa28c89..d18167bcb41f 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -81,6 +81,23 @@ &gpi_dma1 { status = "okay"; }; +&i2c8 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen@48 { + compatible = "samsung,s6sy761"; + reg = <0x48>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + + vdd-supply = <&pm6125_l13>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_default &ts_avdd_default>; + }; +}; + &pmk8350_adc_tm { status = "okay"; }; @@ -290,6 +307,20 @@ pmr735a_l7: l7 { &tlmm { gpio-reserved-ranges = <13 4>; + + ts_int_default: ts-int-default-state { + pins = "gpio22"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_avdd_default: ts-avdd-default-state { + pins = "gpio59"; + function = "gpio"; + drive-strength = <8>; + output-high; + }; }; &usb_1 {