From patchwork Fri Nov 11 10:14:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 624057 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3599CC4321E for ; Fri, 11 Nov 2022 10:16:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233608AbiKKKQF (ORCPT ); Fri, 11 Nov 2022 05:16:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233587AbiKKKQC (ORCPT ); Fri, 11 Nov 2022 05:16:02 -0500 Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2060.outbound.protection.outlook.com [40.107.244.60]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BA3410B8; Fri, 11 Nov 2022 02:15:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=QcAlaSSizgkWe4aVFnwQuWV2pZGSIqNYOgSZBQ2294G6hkpHE9L35wpManXXrYa/x6skG4XchS1HUbNkpMq5i6bhFBhdH5BAv4fXAsotHPTz/7NwGepp0pCAXfytyukEqB0USn6AElxX/El6jyJEzKiegT4cRktAZRhrc3vXqG2MW87TN1IG/VMJaGbES8lWF0RlbHH0XbkFMSOTmPoA2xf/7AIoSX9Y1+qltxrQimymU5qc5zzGrGNpmceO12uK4CsdhvC45XlhdeC/ifz1IYIEJN8kwIVgG2pkzAZEnv19wz8XGDpVzUp9I/AkYiTjZSji1lKootHUjWbMkLGYeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vs/S4cWkFvBdXcr1u/3YfmRTM0i3TVOlY3uRjy0sRLI=; b=MTItGxsqwLk1Mea2XwJSY+mhvyfHlsjGMFS15Jmug6FDzVOFp16ws7LC/eMvX/Ocag33hkaYvsskiamDxumDRDrfOWFKfwxy2eb0tfzWDnxnIXxRyQSa1c+eZoQ0Hhvtg5L+X3xYhbMqj70C3s8b+Z9a+ekR2aDA1BLrNG2nIC8EaM1syudSl5jv6tiD4icr+hq5M5Dol/UTXc0NGx748tG7FBVSbznbM4JEp51ldLMoAOVwVYJcdvxjaItPJXoNiZgpoQ6hgt0wDnN6+MAHM50ua48q570Xe9FsjF+o6fXNRJBZbYc4hENwmxeTG9BIkIr+9hEPQKMnapTE+SmqJQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=linuxfoundation.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vs/S4cWkFvBdXcr1u/3YfmRTM0i3TVOlY3uRjy0sRLI=; b=iQ1Bv2767QOKtfVaHqs0F67xJwIVaxbqQuhr6VlrHAfftiq7pA2fSbfVLhOO26v5qFB3W1MMqMmJGxmiFoY15HLYhwqbx5o7jvX4HqCdDako6WJX3pyUyq38nNvu8nv/2BfzY2O0L3az/3/uO1ah6HooxQRwM3MOiJwrCjyLQw+WobAtMzQVBY8srnQXlocP78fz4+sRDIWjiDUucb2V/0+hiasykf6GTPVkRyig2vQ0Pw8MUpc6w+fhuN7UOIXwSZ5KmBul765hHR+DVPc9376AZPvnajjIQ8HEsEtqtGz5DOnqMR2F50DXHevPpLv97uEifn5FE1otEc/yolAqHQ== Received: from DS7PR03CA0166.namprd03.prod.outlook.com (2603:10b6:5:3b2::21) by IA1PR12MB7541.namprd12.prod.outlook.com (2603:10b6:208:42f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.27; Fri, 11 Nov 2022 10:15:57 +0000 Received: from CY4PEPF0000B8EE.namprd05.prod.outlook.com (2603:10b6:5:3b2:cafe::80) by DS7PR03CA0166.outlook.office365.com (2603:10b6:5:3b2::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.14 via Frontend Transport; Fri, 11 Nov 2022 10:15:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CY4PEPF0000B8EE.mail.protection.outlook.com (10.167.241.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.11 via Frontend Transport; Fri, 11 Nov 2022 10:15:57 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Fri, 11 Nov 2022 02:15:50 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 11 Nov 2022 02:15:49 -0800 Received: from waynec-Precision-5760.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Fri, 11 Nov 2022 02:15:45 -0800 From: Wayne Chang To: , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v2 02/13] dt-bindings: usb: Add NVIDIA Tegra234 XUSB host controller binding Date: Fri, 11 Nov 2022 18:14:58 +0800 Message-ID: <20221111101509.999589-3-waynec@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221111101509.999589-1-waynec@nvidia.com> References: <20221111101509.999589-1-waynec@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000B8EE:EE_|IA1PR12MB7541:EE_ X-MS-Office365-Filtering-Correlation-Id: 0602a273-8069-4a4a-b90e-08dac3cdb993 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: lU4479cudM7SEBGkm09xFzp2rd39TkHFCamJavm8ZWoMNir8o/hvY/cP3AvhYAOexk/S4CF3EJrBDabgf21yxtDw51L4ylBAAFCW/o+DuFdFO5b87063X1pMCpU6B0hVMP5GzZiov8GgXfuvDywmwN0LecpNjokV6G9H0A57p5dnXuhEO6xRxCALaL9jDaLXu8KnQADH4U7YWZ1VNtIQEfCVuYn5fWX5qjYV8pNaHUaZXJvnnXkIRr8ckJqIYVcLzBVvcC7QgXxY68GH9+y/Ma9YozY0bA+3HSpUKAPonOAqxErpOlFCP3pdChve91S6zIU88fx/cCxBm5VF5pFA8Q/oe/JwjZCNnNGNOaeoR5omewEyPt/vEGE2X4R+itzO4e/AkkUTRnwPtNwDxTweGlSPdlsSYgpF/+bfDkWlb1d/K95fc30pdPw2QYyc7U1H/Oc4YLXNydvxOfF4ss3dCxlRdDVurkxLT0lAYg74yWjOhP3MiRhcATkkv9sNdu5lHPw7LszPYYC5mGhPEm5nyb9Z6Wyytm0GSC0K30UJWuSNRSZkV3iKTKLVCfX5oY/cMREcJb9o/kPfu/g8veUObnky3a+uEoQafgk3WMppG4UsIcRjdvYim5UZSaL00eutDl4Gvch8DpU6TvjggYtQ2nd7v14YRHqADOSZG/EpIilCQJwj0mI8/NvlARMgua1SoW5R0QT8eKJB52/xXYJE9S8G673PnNz68Bue3jXspUbZEUWHnn5Eakx2/u4VDNC7YquIcwom5p53f5VlzHWGhY0SWXi5pqTvFQ9vwNghHxWhZrxqz5RBKaSWWImbyyhAZR7byk9URqU0QeicfP7kJyxsGEn7ffGDO0AqEfS/RPIMTBbhtlwUqlxkl8WlHjRajPS2s82Sj7+RYqdpjdbZG3Enq61i+S2PraLNkwkYwd0= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(136003)(346002)(39860400002)(396003)(376002)(451199015)(36840700001)(40470700004)(46966006)(426003)(336012)(1076003)(40480700001)(186003)(6666004)(2616005)(356005)(2906002)(4326008)(47076005)(36860700001)(83380400001)(70586007)(110136005)(966005)(70206006)(41300700001)(921005)(26005)(7636003)(5660300002)(8936002)(54906003)(86362001)(82740400003)(8676002)(6636002)(7416002)(40460700003)(7696005)(316002)(478600001)(36756003)(82310400005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2022 10:15:57.3962 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0602a273-8069-4a4a-b90e-08dac3cdb993 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8EE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7541 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device-tree binding documentation for the XUSB host controller present on Tegra234 SoC. This controller supports the USB 3.1 specification. Signed-off-by: Wayne Chang --- V1 -> V2: new change for adding nvidia,tegra234-xusb.yaml .../bindings/usb/nvidia,tegra234-xusb.yaml | 159 ++++++++++++++++++ 1 file changed, 159 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml new file mode 100644 index 000000000000..d78ee88ed208 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/nvidia,tegra234-xusb.yaml @@ -0,0 +1,159 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/nvidia,tegra234-xusb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra234 xHCI controller + +maintainers: + - Thierry Reding + - Jon Hunter + +description: The Tegra xHCI controller supports both USB2 and USB3 interfaces + exposed by the Tegra XUSB pad controller. + +properties: + compatible: + const: nvidia,tegra234-xusb + + reg: + items: + - description: base and length of the xHCI host registers + - description: base and length of the XUSB FPCI registers + - description: base and length of the XUSB bar2 registers + + reg-names: + items: + - const: hcd + - const: fpci + - const: bar2 + + interrupts: + items: + - description: xHCI host interrupt + - description: mailbox interrupt + + clocks: + items: + - description: XUSB host clock + - description: XUSB Falcon source clock + - description: XUSB SuperSpeed clock + - description: XUSB SuperSpeed source clock + - description: XUSB HighSpeed clock source + - description: XUSB FullSpeed clock source + - description: USB PLL + - description: reference clock + - description: I/O PLL + + clock-names: + items: + - const: xusb_host + - const: xusb_falcon_src + - const: xusb_ss + - const: xusb_ss_src + - const: xusb_hs_src + - const: xusb_fs_src + - const: pll_u_480m + - const: clk_m + - const: pll_e + + interconnects: + items: + - description: read client + - description: write client + + interconnect-names: + items: + - const: dma-mem # read + - const: write + + iommus: + maxItems: 1 + + nvidia,xusb-padctl: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the XUSB pad controller that is used to configure + the USB pads used by the XHCI controller + + phys: + minItems: 1 + maxItems: 8 + + phy-names: + minItems: 1 + maxItems: 8 + items: + enum: + - usb2-0 + - usb2-1 + - usb2-2 + - usb2-3 + - usb3-0 + - usb3-1 + - usb3-2 + - usb3-3 + + power-domains: + items: + - description: XUSBC power domain + - description: XUSBA power domain + + power-domain-names: + items: + - const: xusb_host + - const: xusb_ss + + dma-coherent: + type: boolean + +allOf: + - $ref: usb-xhci.yaml + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + usb@3610000 { + compatible = "nvidia,tegra234-xusb"; + reg = <0x03610000 0x40000>, + <0x03600000 0x10000>, + <0x03650000 0x10000>; + reg-names = "hcd", "fpci", "bar2"; + + interrupts = , + ; + + clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, + <&bpmp TEGRA234_CLK_XUSB_FALCON>, + <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, + <&bpmp TEGRA234_CLK_XUSB_SS>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_XUSB_FS>, + <&bpmp TEGRA234_CLK_UTMIP_PLL>, + <&bpmp TEGRA234_CLK_CLK_M>, + <&bpmp TEGRA234_CLK_PLLE>; + clock-names = "xusb_host", "xusb_falcon_src", + "xusb_ss", "xusb_ss_src", "xusb_hs_src", + "xusb_fs_src", "pll_u_480m", "clk_m", + "pll_e"; + interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, + <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; + interconnect-names = "dma-mem", "write"; + iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; + + power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, + <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; + power-domain-names = "xusb_host", "xusb_ss"; + + nvidia,xusb-padctl = <&xusb_padctl>; + + phys = <&pad_lanes_usb2_0>; + phy-names = "usb2-0"; + + }; From patchwork Fri Nov 11 10:14:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 624056 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93D3AC433FE for ; Fri, 11 Nov 2022 10:16:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233593AbiKKKQZ (ORCPT ); Fri, 11 Nov 2022 05:16:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53006 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233577AbiKKKQN (ORCPT ); Fri, 11 Nov 2022 05:16:13 -0500 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2089.outbound.protection.outlook.com [40.107.94.89]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 61A0367125; Fri, 11 Nov 2022 02:16:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TwKtjGMUdalmHpdx0hq2ijVaTOc3yleJ/ff4Ofgw+j+I82Mpge/vbud7fTpcw0cVbRRBqTmrzGgWfIyD0+dLKNtK0hszMCZ3ZuLsr6s6NLbICbXMYGaU0IxeuOnmlw1Z1XnLwxUpxZsJzlnze0jzKSn9RyvP8lHX7bO9tMF6kf9oQYkGhXJjXVp0OR4lk7OiMBoxFXLLRf7oeEiWpStrUjWE1hXnkSJgXrbjTbwQ72KiqisIcGW/MVdN8ixCSHIZZmX6PGTEv4PAq0ZDV51MGOmXUfh8GRhnQPYziuP1+EvSy27B46W+nrDGe70s0CstShE6VXMamW1ToZEnpI7J1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=UE+pAt+PFeQpx0TGAzlqAkYYvI78kM/x+OtLKXiESHo=; b=N+0WCklmY1ygDwwNMsuYisjPQzSjkTvtAm0tAxm1NlWZOWZQ/ip5rX2CpYf25aLFXlMocDAE6mLHM+OD7gtV0pynL+tlH59IffAT8oU9CY6t99Iyvl59fT+T5Pl9BaTZ0W2nE2judsUEwpT6m9stfeJ1xIWTC/qRLuoKdLLUQQLx/d80AEPXpU5L7sLKtvzgssFuHRMCUhTSCG15uulgS+4yHdyVzoOz0zlKii3wgJefU4Pp61oCziIFgs4+0UrlYjIXo0UCp5vWftXguagqZMKM4CuqXB1Uw9LqKejEEAqx1jx9BHjbCEvFISPfkodAlYDf1mvRQPy1GA3sUXcz2Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=linuxfoundation.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=UE+pAt+PFeQpx0TGAzlqAkYYvI78kM/x+OtLKXiESHo=; b=qzrIrJQ4bPlZwe+wmNZAlgch0jZzloSl2vRcfnnn3pD1vjUHGYzGzCKI/n1UL1JAoSUJ7I4oOpu0jWjiR4WDEB0wWYCJWEArUqKOkWb5rpDkKlXQwE54nuyIh6lyCoa5VHucpaagtxuH7e+agIuPT/iB4MK3XdHznlPzSeaTy4r7UAWashecMu2Sj45z1QTqn/jdX5Dt1+9nUpsZ8QlFJdv+jurSGj7wLfP/Ol6wt1AjRi9eGZ+kFf7oyYJefXygO2mJBzDy9GgrWmBXrWR1R8Da6nGP73OoBjV52XT0pQfHPQzzMWvsLCh4olRIlaJlc5xo7v3xQg9vgiCXgwJcBw== Received: from MN2PR14CA0005.namprd14.prod.outlook.com (2603:10b6:208:23e::10) by MW4PR12MB7141.namprd12.prod.outlook.com (2603:10b6:303:213::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.13; Fri, 11 Nov 2022 10:16:10 +0000 Received: from BL02EPF0000EE3D.namprd05.prod.outlook.com (2603:10b6:208:23e:cafe::74) by MN2PR14CA0005.outlook.office365.com (2603:10b6:208:23e::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.14 via Frontend Transport; Fri, 11 Nov 2022 10:16:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL02EPF0000EE3D.mail.protection.outlook.com (10.167.241.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.11 via Frontend Transport; Fri, 11 Nov 2022 10:16:10 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Fri, 11 Nov 2022 02:15:54 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 11 Nov 2022 02:15:54 -0800 Received: from waynec-Precision-5760.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Fri, 11 Nov 2022 02:15:50 -0800 From: Wayne Chang To: , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v2 03/13] dt-bindings: usb: Add binding for Cypress cypd4226 I2C driver Date: Fri, 11 Nov 2022 18:14:59 +0800 Message-ID: <20221111101509.999589-4-waynec@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221111101509.999589-1-waynec@nvidia.com> References: <20221111101509.999589-1-waynec@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0000EE3D:EE_|MW4PR12MB7141:EE_ X-MS-Office365-Filtering-Correlation-Id: 2b539402-91c1-439a-18e1-08dac3cdc11e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MmnHmnxFFYH5ogxUksV+3w0QvK9PEgdvAhYorvhxCA6skZwHZk+VGeuT1fU6Rbu/B8BiRO5drk44b20QBFOdnH6rQbrPPkCUalpYlzBpJ43pmEMT17Au4Fs5tph9/cBPnAq6bB0jb9q6csuXKI343QCAXgvY6qRwTWgrjPXLXokhQFVTve1q5PZ9eQlq7mnD3WFU9fN1iJkaK3mYB7jHGFCrFWvowmNWfojtCH5ohE8V9It2fPgx+ut0i7JpcrcQA53OeI4kkLno4L6shV7chhueVm8lbrjY22UuxAjqjjNPV0LnCRMQKwt9eCYXxc4JyuypJvSKlMVTMdXsoAHPAiGoZuzi/BLX5A1DeQfEEhpPQ+1JZYHYMUO5rBOTesaV2k2FhFurpvQV1uE6ya/5ocZtFca7kGBZuIkt/0hH+wTRXeQbqDZpeEdQ0WWV5v6fomdnV4FmY8h/FunXiv+lCywMePXLXSinx2P+78JVjfGz31LXXvkCN93gYqj355AXUeaiSRFhGUUWmKU/0B04HFk9V2xWaz43ykyoRcYQzUi2SBJGCtVEr6CN4iWmX9lZx/Olsz18+L4i+WliWRcUkOsCVINQR6mPXQ/tH0JorPknl7VhmyYOzzTprDRD00WNGf+y6hO3D0+uqfzXEKLLczGUGYJYOQzl+PPUfHVY7Z/nYgRNweHuTY2Btofow2rxBiDMxVYEH3tKyrpQC9kHjo0m3HW04G4FMACh8K/dpWlsTtmNt70jcbx+9MX0hVNGtxlrMUui+GoBkDBmH+ZJct/gMrVsHywbTE4vqSc6O1WgMUcKKgwVIzoD2n+fZRmsgNvSUUcKh7147PyW/IB2dn/w7wVQ0kWZYEIuESnrv78TxTFeuBsic6MBkdLdf4XCSBN4sj1iPyqxSzy8HntZ0bOIZAklA2j6MCl3Z61Rjn4= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(396003)(376002)(346002)(136003)(39860400002)(451199015)(46966006)(40470700004)(36840700001)(36860700001)(7696005)(86362001)(47076005)(426003)(40460700003)(2906002)(36756003)(26005)(40480700001)(82740400003)(82310400005)(41300700001)(8676002)(1076003)(966005)(186003)(2616005)(7636003)(478600001)(70586007)(5660300002)(356005)(4326008)(7416002)(54906003)(6636002)(110136005)(8936002)(70206006)(921005)(336012)(316002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2022 10:16:10.0159 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2b539402-91c1-439a-18e1-08dac3cdc11e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0000EE3D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7141 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org add device-tree binding documentation for Cypress cypd4226 type-C controller's I2C interface. It is a standard I2C slave with GPIO input as IRQ interface. Signed-off-by: Wayne Chang --- V1 -> V2:Based on the review comments. Fix some addressed issues on description, interrupts, cypress,firmware-build, connector, and additionalProperties properties. And also remove the status in the example. .../bindings/usb/cypress,cypd4226.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml diff --git a/Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml b/Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml new file mode 100644 index 000000000000..70db97e0ad31 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/cypress,cypd4226.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/cypress,cypd4226.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cypress cypd4226 UCSI I2C Type-C Controller + +maintainers: + - Wayne Chang + +description: + The Cypress cypd4226 UCSI I2C type-C controller is a I2C interface type-C + controller. + +properties: + compatible: + const: cypress,cypd4226 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + const: 0x08 + + interrupts: + items: + - description: cypd4226 I2C interrupt + + cypress,firmware-build: + enum: + - nvidia,gpu + - nvidia,jetson-agx-xavier + description: | + the name of the CCGx firmware built for product series. + should be set one of following: + - "nvidia,gpu" for the NVIDIA RTX product series + - "nvidia,jetson-agx-xavier" for the NVIDIA Jetson product series + +patternProperties: + '^connector@[0-1]+$': + $ref: /schemas/connector/usb-connector.yaml# + properties: + reg: + maxItems: 1 + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + +examples: + - | + #include + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <2>; + + ucsi-ccg@8 { + compatible = "cypress,cypd4226"; + interrupt-parent = <&gpio_aon>; + interrupts = ; + reg = <0x08>; + cypress,firmware-build = "nvidia,jetson-agx-xavier"; + #address-cells = <1>; + #size-cells = <0>; + ccg_typec_con0: connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + label = "USB-C"; + data-role = "dual"; + port { + ucsi_ccg_p0: endpoint { + remote-endpoint = <&usb_role_switch0>; + }; + }; + }; + }; + }; From patchwork Fri Nov 11 10:15:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 624054 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3076EC43217 for ; Fri, 11 Nov 2022 10:17:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233871AbiKKKRF (ORCPT ); Fri, 11 Nov 2022 05:17:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53056 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233651AbiKKKQn (ORCPT ); Fri, 11 Nov 2022 05:16:43 -0500 Received: from NAM04-MW2-obe.outbound.protection.outlook.com (mail-mw2nam04on2049.outbound.protection.outlook.com [40.107.101.49]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 835C98546F; Fri, 11 Nov 2022 02:16:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=W1o5fHCNsE3iS4ODctrN+7ulFtRfWbR+HZyRSk6VmXuiuxNkPuSZFIBm544FTS8L7RIxCqrJcEuACiaCVj4kzwC1KhSa1gTcrA3fIcT0hrzdys22fclgnfSh6NvLb+LaIpaVPl2irNiUs+KbCrr0tXPARO/jRrgzG7FszloYiDNXrE/xjuFacvfBPpKAIXG5xjMfJ1oKWsAyQ4epdlbs9W3M+Tz8N5CIqfqyYfou6+tVo/49abE11IJOGEj6kWNEEVZEMQBQpJetxWV44Gslv2PUyBhPgf8FCryx4loB0no/fXvShicjfP9/4F3z88ndSgyNX2z6/yWxE1NjqmR9KQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=f65T2XoEhiUfwf8HgFImqiGxkWSY66pNhbk64UYq/og=; b=jZhZ/9cL6rKlKn1vIKQAYgJamqFErPrvq60gHK2zXx5nQBHyMoC5NIb03i8abm6yx0G579qPof4gvPKV6BPzUwPVyv5duqvoPbQ4D4bU2CznIpMjbJsFh+T3iun8DddI4Jjj0xCKEkvdp0eYtxjU2yihuqvDgnZmpGFqhQ+ayQuU4lAHysPNGhZMzmV3Vnwhv41snXd3Qkn0e2N0iAZfKsL5gbgswVP2iKaghyjA8odZE1V/nVrYlRTztzuD7G5OFt0oeoAlzy2GT3+8EmZyHO+QqtXRNZOQ7vwExL1Y+dnZQbKVvDEzxcgKaXsGTQjGtgyZ/ly8zJXSjVpkXLJoWA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=linuxfoundation.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=f65T2XoEhiUfwf8HgFImqiGxkWSY66pNhbk64UYq/og=; b=Z7JJhMqVFtWBSieWqorjCrSOfIYks1JlOWlWDu1yuO5+tGapn7QxIdweLMEFTMAzKzJTgWsEPwA98SY1/1DujG0KgEn035dzUs5I7ta5pC20JYlRQjzdo0rGkiLKjEHNsd7oU5pXnD1HLQENMZ4UlimcgmniGbbLTcpqXlq9JFhrBuazOeZck9xoR9HQJpV7vRvDd3XSC7DEfbn0yrM1VKsGc8U89itTNWmeonxNSmFrPdh3S/eRlGSzZZOceXHB88cIgDeHImhBiSsMUnEfIlexZWOyDNIkkWbpU0R+mjx6iS9vquY6yk2QdCdkfgyzaUWbZ9KtcBH2RwGDOvS40w== Received: from BN8PR03CA0009.namprd03.prod.outlook.com (2603:10b6:408:94::22) by SJ0PR12MB6902.namprd12.prod.outlook.com (2603:10b6:a03:484::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.25; Fri, 11 Nov 2022 10:16:27 +0000 Received: from BL02EPF0000EE3C.namprd05.prod.outlook.com (2603:10b6:408:94:cafe::15) by BN8PR03CA0009.outlook.office365.com (2603:10b6:408:94::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.27 via Frontend Transport; Fri, 11 Nov 2022 10:16:26 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL02EPF0000EE3C.mail.protection.outlook.com (10.167.241.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.11 via Frontend Transport; Fri, 11 Nov 2022 10:16:26 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Fri, 11 Nov 2022 02:16:07 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 11 Nov 2022 02:16:07 -0800 Received: from waynec-Precision-5760.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Fri, 11 Nov 2022 02:16:03 -0800 From: Wayne Chang To: , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v2 06/13] usb: typec: ucsi_ccg: Add cypress, firmware-build as a well-known regex Date: Fri, 11 Nov 2022 18:15:02 +0800 Message-ID: <20221111101509.999589-7-waynec@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221111101509.999589-1-waynec@nvidia.com> References: <20221111101509.999589-1-waynec@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0000EE3C:EE_|SJ0PR12MB6902:EE_ X-MS-Office365-Filtering-Correlation-Id: b2d4e769-e181-45e0-1789-08dac3cdcb1b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YcmATPPuOP97y6bp+9I6FMmlt0CyewazvOdRogrJwvXS3bmVyKW7apoFB7c/1x3GMy+vWVu8LgQctTgOl1WWuhFRqaAgoUSQPOWbmD6Zf3qcFAniXsnfHxymp8Y73LkyJTXns1G1DOjlRYvdPu23ihZUCIvRB/xqysokt60E0RyrhHBi4WMtgZ9XEmVzQZN1Wu9Pjae0X7oGzgKT4XZqHdK4lAjZDHl9t+Ai6zBSrPAjcYqQvGkRWaT0mxBXUiZyvGnKpOpxsgizH0Noe8R9p8Wc88ZOdW7LpyyMC4PEIEA3Tg7H2noqd7HVI6vBPYeDfrwcQQOYFl44oz7FNZUStMhRXkH6xVFhFhEdKBriI9m1Y+BgtuX+GAWn46FiI8l4OtgnW2zs1PRve4zqFf3+a180MyA4vIdUpTMzmpQICxX0OvzF19U/GvdOFQzFwjAW9biikqt48J7RwRX6EyvNioyT2LmkAQc7osWz23WikPJS/Eh5rbHSR2mbyP4SIwYDiJNiBOR/QjEp61aAHoqp2jxYevGhPhXZTqTlti5v2ja6ouM4ablUPPGBoLe94kmLvZcH8LJK1aHGwE7J5gJElLLv289WfnSYNzabD88aD0Bo87wlpxsjyvOSxs5AoWY2Px+ReJ+lv4oYFHONpet8vCuj7E0EejYRwmdyZMd93/oKAzFCjaQGFK038Jh+1gDPJsIrrkKRjLxyG6LFXQL79bw3YCDdBXloInFpQYDiwAWi4YMRGNMggUNIwHG4fA/adnJW2MDi86z3O0kmbrolsNS+MnIKBKKIfA9WAvhoDcQ= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(39860400002)(136003)(376002)(346002)(396003)(451199015)(36840700001)(40470700004)(46966006)(2906002)(478600001)(7636003)(356005)(36756003)(7696005)(336012)(54906003)(70206006)(316002)(6636002)(110136005)(426003)(47076005)(86362001)(186003)(4326008)(40460700003)(8676002)(70586007)(1076003)(82310400005)(921005)(40480700001)(41300700001)(2616005)(8936002)(5660300002)(36860700001)(26005)(82740400003)(7416002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2022 10:16:26.7733 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b2d4e769-e181-45e0-1789-08dac3cdcb1b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0000EE3C.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB6902 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org ccgx is refer to the cypress cypd4226 typec controller. add cypress,firmware-build as a well-known regex. 16-bit value is not sufficient for descriptiva names. Using string instead of u16 to make it more descriptive. Signed-off-by: Wayne Chang --- V1 -> V2:New change added for adding cypress,firmware-build drivers/usb/typec/ucsi/ucsi_ccg.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/usb/typec/ucsi/ucsi_ccg.c b/drivers/usb/typec/ucsi/ucsi_ccg.c index 139707a2f3d6..e412a457bbfc 100644 --- a/drivers/usb/typec/ucsi/ucsi_ccg.c +++ b/drivers/usb/typec/ucsi/ucsi_ccg.c @@ -1343,6 +1343,7 @@ static int ucsi_ccg_probe(struct i2c_client *client, { struct device *dev = &client->dev; struct ucsi_ccg *uc; + const char *of_fw_build; int status; uc = devm_kzalloc(dev, sizeof(*uc), GFP_KERNEL); @@ -1363,6 +1364,17 @@ static int ucsi_ccg_probe(struct i2c_client *client, if (status) dev_err(uc->dev, "failed to get FW build information\n"); + status = device_property_read_string(dev, "cypress,firmware-build", + &of_fw_build); + if (!status) { + if (!strcmp(of_fw_build, "nvidia,jetson-agx-xavier")) + uc->fw_build = CCG_FW_BUILD_NVIDIA_TEGRA; + else if (!strcmp(of_fw_build, "nvidia,gpu")) + uc->fw_build = CCG_FW_BUILD_NVIDIA; + } else { + dev_err(uc->dev, "failed to get FW build information\n"); + } + /* reset ccg device and initialize ucsi */ status = ucsi_ccg_init(uc); if (status < 0) { From patchwork Fri Nov 11 10:15:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 624055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2294C433FE for ; Fri, 11 Nov 2022 10:17:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233772AbiKKKQy (ORCPT ); Fri, 11 Nov 2022 05:16:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233737AbiKKKQm (ORCPT ); Fri, 11 Nov 2022 05:16:42 -0500 Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam04on2044.outbound.protection.outlook.com [40.107.100.44]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2347683B94; Fri, 11 Nov 2022 02:16:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=niQ8xp4nylo0tYR3YusqOV5aXQX6z9ryWqmDFIpWWmNlepZI8szoLpslDzBOL9z1sgvTPgRrA1g+0xpXmAwImEWzyLzGlK41eLeZjv2WpzKC7x9krnZC+gYn2HAcHtlq+3v6A7ZAS+yWKj090dTdOwTkM01W7AYaznuLhZYjrZ0/d3T/hNkqKWXwbhDdhewXGPKIYOwi7An8Y7ECpcc0Scboe1kHMn/V+AVSirxxMr0bSMfCFAWzM2kTr84eXgBXGjsu5bB7K/0z530Bb6gq2Jwatk3ugA4NyFoIw8PVuii8t6rfJuPd5TxBSki/bvKMa2DJwnZY3H2k1tmpkO5M/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=RoOtlFxOTztopXclAbiCCC5OWKvXUyqImo9xMJ1Tn0I=; b=RbnjIU+KOJWEshbIpyL9124aQxBx4e0Y2nrBtj6EnTHZ2hNLXEeXwAfVF/Uegb++8XgANXyqIQZK3tPRQVlwHa6dKFR0mDDkT+FSGhd7BniZ+312tIBjE/EfPneX5EBiwrdKWCn5OOjhlhkacRvwUIlOzUYg7GOAXkguOC1Fqo1Wa4FAPgMEZ2CmvgUqx4rUWLwL0UIjHg2PFKSF0FsLOfrHmwefeEcvEyTDIcTgfSj9SFRkLBJ89eLkiEqmkSyS+lWj/9ikz5ePk162xrjt9f5fEmUMDywUjugvRG7R3X4vnosaGeqfH34nbZ9hMBqbgy7m1+CdCZ1v7TtZLk7OFA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=linuxfoundation.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=RoOtlFxOTztopXclAbiCCC5OWKvXUyqImo9xMJ1Tn0I=; b=QMaXrSmZLc++lOZaBR2EPz1Au29Qyldb828JDbFpd4kQO8p4NKlBeYihx8WSls8lNza8o05+bE6/PugylsCkpFzKez5Xw/j1aYFU8BoCpxyKA3gFS6HDpIy6xFQSdRj72z6O8CLwQbWfm61t7YdP4YUR007cx3OcvoPl6X2AJJOKfEBB1BWHVcOgBRe56ydweUw0VdJTg3dnnxixV7G7AjlCm4zRvYv+jTx5F7CxQMxE8jfUEFLakcc7u5pv0bc8N5g82pcgHa5Yk83V0u1HxnWZs6FnAuq3B+30t9PXa6dgyu7oJHKA2siJnobT4+k4K5jhMSPzSz5ZXFsEBh3PUA== Received: from DS7PR03CA0166.namprd03.prod.outlook.com (2603:10b6:5:3b2::21) by IA0PR12MB7508.namprd12.prod.outlook.com (2603:10b6:208:440::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.13; Fri, 11 Nov 2022 10:16:23 +0000 Received: from CY4PEPF0000B8EE.namprd05.prod.outlook.com (2603:10b6:5:3b2:cafe::a2) by DS7PR03CA0166.outlook.office365.com (2603:10b6:5:3b2::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.14 via Frontend Transport; Fri, 11 Nov 2022 10:16:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CY4PEPF0000B8EE.mail.protection.outlook.com (10.167.241.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.11 via Frontend Transport; Fri, 11 Nov 2022 10:16:23 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Fri, 11 Nov 2022 02:16:11 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 11 Nov 2022 02:16:11 -0800 Received: from waynec-Precision-5760.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Fri, 11 Nov 2022 02:16:07 -0800 From: Wayne Chang To: , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v2 07/13] i2c: nvidia-gpu: Add cypress,firmware-build as a well-known regex Date: Fri, 11 Nov 2022 18:15:03 +0800 Message-ID: <20221111101509.999589-8-waynec@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221111101509.999589-1-waynec@nvidia.com> References: <20221111101509.999589-1-waynec@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000B8EE:EE_|IA0PR12MB7508:EE_ X-MS-Office365-Filtering-Correlation-Id: 15d6c6a5-dc93-46aa-cf65-08dac3cdc92a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: S4BgHZW5cNk4WgdOCBalwlaLnZTyevvwTzKG5HbQttWq3aKPqeJUmnj0gYr6JoFtl0lL1RzqdSNZuOqlJHGgj41yAGwbM9untTM40N8suHS5rOY5VLWhPSsbOTNCBRw47jLbMNVaarxsluDgcwE4w3fG3w7hJLwmcLeiLyIT4J4mbNttv61RcgdJsfcOzssHM9y/2ayNirTYHCvwB8/v1k1YjbG/eQt10kk/WR8zWB3SUBriQ0veicLpm3ou9ldFKRxNax2oIt6jjoiLOa/urUUHcEwcVKuaPe7bxAfa8vy/2sRSennsA5/rWya0kBNd3hOJR5j0Q7Rea4yEHuU3hmipJ9MYFMn6fZ6rgdXgt/r4ttHxlH8Awudt4vnm/Ea586+sYhuOxiYV96K1EyhcZqIwgcsljhmr4KIO91FLmMTZa8mxMIFbtzCnKI8ZMNErPMB26ftDqeJy22/DX7AviTDT9vlJhuZHaWyBf8hqu+XVSBmfGeEWE/d/teu9ArXg/j8yshFXnQvTpVM7yr6+nDdIk0IcEFgsqPuDR9rfm30J9CFz0T5E7KM1hlJ+pge/Lzh1JtPHRkclAwdyzqkkclaizoRc6sKU/efwZ2QQTfajfL26yah7Gb1lxHj2eU32Jd/3gcA0/v/PBBHhlA9S1RUEvHUSpHUQc2ENSNTL+EPLFDcXG0+xM2EJMtIzlE3jJ4+2hAvO8TgKGL5dhtDCdlwk7hGCwoyPL/qMfgneiuE1ElX5pP5efsgOjQIAroDKP/u0PUjRkawdHY/AXTxd25Xtrg7Y2sZ6b5cY8XLBtYw= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(346002)(39860400002)(136003)(376002)(396003)(451199015)(36840700001)(40470700004)(46966006)(54906003)(6636002)(110136005)(7696005)(356005)(316002)(7636003)(36860700001)(4744005)(426003)(40480700001)(2906002)(47076005)(5660300002)(186003)(4326008)(2616005)(8936002)(70206006)(336012)(1076003)(40460700003)(7416002)(70586007)(8676002)(26005)(921005)(36756003)(41300700001)(478600001)(82310400005)(82740400003)(86362001)(6666004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2022 10:16:23.5678 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 15d6c6a5-dc93-46aa-cf65-08dac3cdc92a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000B8EE.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7508 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org ccgx is refer to the cypress cypd4226 typec controller. add cypress,firmware-build as a well-known regex. 16-bit value is not sufficient for descriptiva names. Using string instead of u16 to make it more descriptive. Signed-off-by: Wayne Chang --- V1 -> V2:New change for adding cypress,firmware-build drivers/i2c/busses/i2c-nvidia-gpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i2c/busses/i2c-nvidia-gpu.c b/drivers/i2c/busses/i2c-nvidia-gpu.c index 12e330cd7635..9b2e13bd44db 100644 --- a/drivers/i2c/busses/i2c-nvidia-gpu.c +++ b/drivers/i2c/busses/i2c-nvidia-gpu.c @@ -261,6 +261,7 @@ MODULE_DEVICE_TABLE(pci, gpu_i2c_ids); static const struct property_entry ccgx_props[] = { /* Use FW built for NVIDIA (nv) only */ PROPERTY_ENTRY_U16("ccgx,firmware-build", ('n' << 8) | 'v'), + PROPERTY_ENTRY_STRING("cypress,firmware-build", "nvidia,gpu"), { } }; From patchwork Fri Nov 11 10:15:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 624053 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 66A8DC4321E for ; Fri, 11 Nov 2022 10:17:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233885AbiKKKRJ (ORCPT ); Fri, 11 Nov 2022 05:17:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233577AbiKKKQq (ORCPT ); Fri, 11 Nov 2022 05:16:46 -0500 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2042.outbound.protection.outlook.com [40.107.220.42]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E174862F7; Fri, 11 Nov 2022 02:16:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=aod0ZopEarpsx0LXvAML7hu9nb/vIooFNEBwXP9hRKdVyzDuqZFbHQTWmonWMvRk+cIzfhKtu5sSoXTQNWYJwBKMiFvCQ3vxgFMPCTi6UGTw1v9njg842hwf/2n9v849tapvXYYsCc65F4l5ybqNBpgkayON7SW89e3jfznqFY59zzgSF5aKt7beezSx/kWLQ9SMqqVkSbthvpPvSj31vkg/2LBu6UcDMWWaC2S7HfsOqf+DfclPQLNf/3btqheLFqF3by2qebSHQ+zJbTat31+9YgJohP0lgyOkNufso4IfhscH32q9ywhaoUXHWEVL4D03mDqnoYddPd5RIfSppA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=5Dq4DR6bfOpMwbvWEHPF6B2z8xaLv7LRMxg0PuSwa04=; b=Q6vDWPcEPO2mVg6GsQpfEI9kDIDrq0OKWiw4DeYI5Ius/nREwom0fYvR5ibpsl1jsPleUx9A0UmpPKPnjyj/yc0qt6AVx9FOei/2/p8SxH8lGGev1W3C/uWJT1+HUvDqxxHkvCAyD0W0FT3cNZD4J0oVCU2T/uc/ZfEd+nf8dqAuO6pAktp/HMTD0dDsvzX0xdkq3btdYjsW7Bu7pIy2hnj3uhLwCP15+G37T/nRgk9qhJ7/E4k8VND3BX5p2bvpIph091FB6jAx1IMcpeXeQkpYuGjLhiE8Ax4MWKUQ/b6CywL4/J+oOVR1o0azxbxuQ07L1QQPTZP6o6iCiOiqlQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=linuxfoundation.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5Dq4DR6bfOpMwbvWEHPF6B2z8xaLv7LRMxg0PuSwa04=; b=gG+PtxwrRdcNHLHLXrK6o0tUMEqkgbTJABVLwViLTTl2H2PoyHv2VdmFNmw51GmE/LITGQc9Dr1WuSeTbPuN9oobyNcSvb+aU/vu8/h+qO7s6suHq5BYx8Is53XUg3K2yevrrij2xf45NnSlshug39TnqxANhM1GiZSpM0y8Ee2h97bfZMMEhySuvqQ1k+i9KTHqslFg4tH2e/lYmaJpkrPW2b4soalFfR0TDtXx7iba8eHMoRMl3oCzqQmLFd5zokhoJMTxhr0cSCuKUVUzOSdv+EVK1ic5QZ6J8BUbL4658F+fgDdKCEHhrIfZHTz/yhrwxaH84mP516J3Pj6t1A== Received: from MN2PR14CA0004.namprd14.prod.outlook.com (2603:10b6:208:23e::9) by LV2PR12MB5797.namprd12.prod.outlook.com (2603:10b6:408:17b::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.13; Fri, 11 Nov 2022 10:16:35 +0000 Received: from BL02EPF0000EE3D.namprd05.prod.outlook.com (2603:10b6:208:23e:cafe::11) by MN2PR14CA0004.outlook.office365.com (2603:10b6:208:23e::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.14 via Frontend Transport; Fri, 11 Nov 2022 10:16:35 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL02EPF0000EE3D.mail.protection.outlook.com (10.167.241.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.11 via Frontend Transport; Fri, 11 Nov 2022 10:16:35 +0000 Received: from rnnvmail204.nvidia.com (10.129.68.6) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Fri, 11 Nov 2022 02:16:20 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 11 Nov 2022 02:16:19 -0800 Received: from waynec-Precision-5760.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Fri, 11 Nov 2022 02:16:16 -0800 From: Wayne Chang To: , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v2 09/13] i2c: nvidia-gpu: Remove ccgx, firmware-build property Date: Fri, 11 Nov 2022 18:15:05 +0800 Message-ID: <20221111101509.999589-10-waynec@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221111101509.999589-1-waynec@nvidia.com> References: <20221111101509.999589-1-waynec@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0000EE3D:EE_|LV2PR12MB5797:EE_ X-MS-Office365-Filtering-Correlation-Id: 1e4e0a94-9151-4f2e-4e34-08dac3cdd058 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: EgZ0llBjlhOVUwc4swIorlHy75X+6Q5y2vE7g4tKqcdJOY2lhjnx4ZYXdaiqbqkJLMaKvJAxQiC86bWYzA8uj5rVd/kaHxpwq+MphQXbADThmCXziSrNNiJJTZK8pLNhQ5xR0z2u0AqE08VQSFEeyKkbQok52hBBB02VsF97/bRYlw64w1KXObP/+P95dN9Kva6jcbrpNr2gY/ifLwxnnT88ANux30q+BnMoVFsjyeQYQtgWvAvq7x8nM1G4wIenugXYyIbNcKMSa5WXpz5du97f0THv1L66Nri/DVH5hNAVliOL14ecyZFBgh67i2vpaB9XAPEUx5XA1IAgDa4+w42ZxrsEe9HPaehaPZEZ87DOeMbm6Oql8oRlpblDvBWXYPeuQDraa8zoDEpQGUjiXwXGRK34BTNz2xWjNoYY8vd9TXVGD9VMQdTX4pXFddQWTDEzAEE85mupb4mKjX/NzaGWE00wkDkTnZ3DY3sbak7vlp+jpSHujj8iSHtqdzxoYUo6HgDdSfcAEmWmyq4Vl1OMUMr/pkIYgofaUbbUMqRs17AqHjpFZXNS3d4tsPeSMVYq8tKmD5tbSBrUboeHkgkBYwTMgw3PDHTjQVxQ6y424eaj8MNrnI9PIJiZQvQzMru0A27GCmh1TFaYoMWJJ2+ciEmjjju3DA9inv4rzZh+JctUVJjwFwtgN2jlRAWlnPxhvEV2WGpnYItN+xUbyjs5K7k/gVdbdDMHjnQxNgczv+LJReivzEKpcNjLgO3egsOc5FKsvbcKryT/h/opcgLDDvegcu2KuazeUkuX7HQ= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(136003)(39860400002)(376002)(396003)(346002)(451199015)(40470700004)(46966006)(36840700001)(82310400005)(316002)(110136005)(54906003)(6636002)(2616005)(1076003)(41300700001)(47076005)(36860700001)(7416002)(186003)(26005)(5660300002)(40480700001)(40460700003)(426003)(86362001)(2906002)(4744005)(4326008)(7696005)(336012)(36756003)(70206006)(70586007)(8676002)(8936002)(921005)(478600001)(356005)(7636003)(82740400003)(83380400001)(6666004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2022 10:16:35.5631 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1e4e0a94-9151-4f2e-4e34-08dac3cdd058 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0000EE3D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5797 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Remove the property ccgx,firmware-build as we have added well-known regex cypress,firmware-build. Signed-off-by: Wayne Chang --- V1 -> V2:New added for bisectablility drivers/i2c/busses/i2c-nvidia-gpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-nvidia-gpu.c b/drivers/i2c/busses/i2c-nvidia-gpu.c index 9b2e13bd44db..092d4d52098c 100644 --- a/drivers/i2c/busses/i2c-nvidia-gpu.c +++ b/drivers/i2c/busses/i2c-nvidia-gpu.c @@ -259,8 +259,7 @@ static const struct pci_device_id gpu_i2c_ids[] = { MODULE_DEVICE_TABLE(pci, gpu_i2c_ids); static const struct property_entry ccgx_props[] = { - /* Use FW built for NVIDIA (nv) only */ - PROPERTY_ENTRY_U16("ccgx,firmware-build", ('n' << 8) | 'v'), + /* Use FW built for NVIDIA GPU only */ PROPERTY_ENTRY_STRING("cypress,firmware-build", "nvidia,gpu"), { } }; From patchwork Fri Nov 11 10:15:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wayne Chang X-Patchwork-Id: 624052 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0581DC43217 for ; Fri, 11 Nov 2022 10:17:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233189AbiKKKRN (ORCPT ); Fri, 11 Nov 2022 05:17:13 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233825AbiKKKQ7 (ORCPT ); Fri, 11 Nov 2022 05:16:59 -0500 Received: from NAM11-BN8-obe.outbound.protection.outlook.com (mail-bn8nam11on2041.outbound.protection.outlook.com [40.107.236.41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DD1B6829D; Fri, 11 Nov 2022 02:16:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=J2cdJUoJL9cGEfgnrxHzlX3+1zwUY3UIe3FP5F8WX9/gRuZslliceDv1cdje1tQRhWAFwMt+hyPLU/+PR/5s47TA565mAULZH/vh3aAf+HjT9Kiv8bKn+6DAatx6k9bsTL9+jDE1NxZp1UEMHgSLHeMW4Neh5CaqXpFFk2ORq72PKLYQTlH0RBI2+vMzfbL64FBBFHd6PEHE0Lt+hqgoP6ZCMAFjTlfBy/aLLjkkf05qgeOv8v5/a5S8Q3eOwbEXFHYMzcFsnwGM9MbrD9qZBNVuvUJ8rC1+ciXVIKdRrAM4mfrW1q8LngUzhl1+r6bwpAKBhzc75k2EaS8Zvcr9kA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=R/BM3Gb/NufbESyfLqjlRaEMDcCHlkycuONYHyeE4L4=; b=KG3kNjQhKJu5bVnRBPx8EM5OsobbNbz7z78NHnjM6UXGtnNaSHBgUGTQ44Mw23RAJXPPO19hModIoc/kGyH+Gxc+MF0+zFDhBWwZDLq4SnpNaue6MTdBVimi1NMlO4+6Hr9OO1WSI8exTzxGeQ3WNTDq+ihZbShF+MtDMMtG9oe+8swx+oIFR+7zX7ElBhbHCNut/jTzz01N0HUc69BuOsLnfeoLSceXPP1CwgFqdPQUmkgM9wEQ3jCZS7KGFHse82elbNAGB+s6JyJm3UrnNmZSc/aVXusRVMzY05Tr93ybxJJVwD17br0r6EkWmf2YAoXvlLgJy7CGFrsVLsm2NQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=linuxfoundation.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=R/BM3Gb/NufbESyfLqjlRaEMDcCHlkycuONYHyeE4L4=; b=c6SSDjcKArLgawoQ5WVD1BDjOhf4jFBNYFN0GQdWwmuKKh7EnDjHMWc2mXOjVE1N9c2xwuK5SigcOg7RaSkIxYhRJ4Ued+g1DZiGYumaUCoADAG0mm/d/4xGcANbjosPrc4RMKYek+SKtm1MWqN6PyaAJOkeFKEyl7icUpTPIHSJ8aaeGPAuXPzPcxLgMCUaPY7TM0b9+fmZ4OUDqZDfISHU65mdpIx6sVAm0Ji14FSsbwU7I3L8Gd2Ru7EHboPBIBzLdM7A/8TTEIP7vWbjuHg2vKe42wXeIFOByQD8neb8fufJSFq2ESsA2jMeJOcjXUxGm4XM701xuz18JJDDlQ== Received: from MN2PR14CA0005.namprd14.prod.outlook.com (2603:10b6:208:23e::10) by MN2PR12MB4471.namprd12.prod.outlook.com (2603:10b6:208:26f::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.13; Fri, 11 Nov 2022 10:16:50 +0000 Received: from BL02EPF0000EE3D.namprd05.prod.outlook.com (2603:10b6:208:23e:cafe::42) by MN2PR14CA0005.outlook.office365.com (2603:10b6:208:23e::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.14 via Frontend Transport; Fri, 11 Nov 2022 10:16:50 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL02EPF0000EE3D.mail.protection.outlook.com (10.167.241.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.11 via Frontend Transport; Fri, 11 Nov 2022 10:16:50 +0000 Received: from rnnvmail202.nvidia.com (10.129.68.7) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Fri, 11 Nov 2022 02:16:32 -0800 Received: from rnnvmail202.nvidia.com (10.129.68.7) by rnnvmail202.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.36; Fri, 11 Nov 2022 02:16:32 -0800 Received: from waynec-Precision-5760.nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server id 15.2.986.36 via Frontend Transport; Fri, 11 Nov 2022 02:16:28 -0800 From: Wayne Chang To: , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v2 12/13] usb: host: xhci-tegra: Add Tegra234 XHCI support Date: Fri, 11 Nov 2022 18:15:08 +0800 Message-ID: <20221111101509.999589-13-waynec@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221111101509.999589-1-waynec@nvidia.com> References: <20221111101509.999589-1-waynec@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0000EE3D:EE_|MN2PR12MB4471:EE_ X-MS-Office365-Filtering-Correlation-Id: fede80a5-347b-4f3b-03b3-08dac3cdd923 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 58Gv026AnskoUl+5ZL7vmI8QbLx4WhdcoN1ik6CT8gj62skDusATsHbcFgLlgISFe42zM03b6t43nC1fXy7OH9IeZFkFnQuPozJdIor0eOPA2OjzPkOa8Hb9Kcpm8pP79Bkx0wBWIaAJu+vp0ZeE33P42NbjN6WYSABnStf8k3uw/ThJNIxvZPhYbypF10uGCwMVYSNhomuydWFPg/MTNVI0xCLba6l43nhBaOBInbyo+zPR+5QVLuvHfjuqdFNICg3EGfvuwGBDnspR2y50ZwgY7nv9efT8gqS7PxsP0tj0icN5s1B477k4OIJ3Qj+wAtuMxezFPUCCyySphuVnaKQzs2N8kpxQcbFlFqlZP5fYfzQkIsdWpvxmXAfktxp3lWSjn8SSit4wpsH/fGpBkNj93wk6xKy9izN1RMr1U21Npphsyy/u6JFZCAPOEu6+wFKtladZzm4R2zM5PgmvHeTIuXTZkLXz4YSxqXlEdMVM1r1V1INTDlAH81dP85KCNJ95HH1eJPyZgONzbsbh5gG0nY300X6IFjpIGIZcgvQoYWK0De9nltYBCLgM91hkn5eey5HiLJkYfn1mQ25TNQkZRFW/WLf9fhfCquaclAtVZxx8bRSE5wgjQAGjHhXeYPae/vk5AQCulXRJClTq+++BL87xJdeGUjS3n4Z0/q6jVAdy/9nAu4MR0B6GqIcjJzafZms6epJEIj3MmJn7hSuRfY3kF5awKQAPNQ4HHrjD3rn3mX3BGMQzdyVhoMxEoa/tM7Kr43bsgEH4yZ/QewyeUHD5rVQIgRLLRbrdpnk= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(376002)(346002)(396003)(39860400002)(136003)(451199015)(46966006)(40470700004)(36840700001)(36756003)(36860700001)(316002)(356005)(86362001)(921005)(40460700003)(82740400003)(2906002)(41300700001)(4326008)(8676002)(7696005)(7416002)(40480700001)(6636002)(70586007)(54906003)(5660300002)(82310400005)(8936002)(30864003)(1076003)(70206006)(336012)(186003)(110136005)(83380400001)(2616005)(426003)(47076005)(7636003)(26005)(478600001)(6666004); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2022 10:16:50.2977 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fede80a5-347b-4f3b-03b3-08dac3cdd923 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0000EE3D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4471 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Sing-Han Chen This change adds Tegra234 XUSB host mode controller support. In Tegra234, some of the registers have moved to bar2 space. The new soc variable has_bar2 indicates the chip with bar2 area. This patch adds new reg helper to let the driver reuse the same code for those chips with bar2 support. Signed-off-by: Sing-Han Chen Co-developed-by: Wayne Chang Signed-off-by: Wayne Chang --- V1 -> V2:fix some issues on coding style extract tegra_xusb_load_firmware function refine has_bar2 and remove has_ifr/firmware on Tegra234 drivers/usb/host/xhci-tegra.c | 270 +++++++++++++++++++++++++++++----- 1 file changed, 232 insertions(+), 38 deletions(-) diff --git a/drivers/usb/host/xhci-tegra.c b/drivers/usb/host/xhci-tegra.c index bdb776553826..b2f07eae2c93 100644 --- a/drivers/usb/host/xhci-tegra.c +++ b/drivers/usb/host/xhci-tegra.c @@ -44,6 +44,9 @@ #define XUSB_CFG_4 0x010 #define XUSB_BASE_ADDR_SHIFT 15 #define XUSB_BASE_ADDR_MASK 0x1ffff +#define XUSB_CFG_7 0x01c +#define XUSB_BASE2_ADDR_SHIFT 16 +#define XUSB_BASE2_ADDR_MASK 0xffff #define XUSB_CFG_16 0x040 #define XUSB_CFG_24 0x060 #define XUSB_CFG_AXI_CFG 0x0f8 @@ -75,6 +78,20 @@ #define MBOX_SMI_INTR_FW_HANG BIT(1) #define MBOX_SMI_INTR_EN BIT(3) +/* BAR2 registers */ +#define XUSB_BAR2_ARU_MBOX_CMD 0x004 +#define XUSB_BAR2_ARU_MBOX_DATA_IN 0x008 +#define XUSB_BAR2_ARU_MBOX_DATA_OUT 0x00c +#define XUSB_BAR2_ARU_MBOX_OWNER 0x010 +#define XUSB_BAR2_ARU_SMI_INTR 0x014 +#define XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0 0x01c +#define XUSB_BAR2_ARU_IFRDMA_CFG0 0x0e0 +#define XUSB_BAR2_ARU_IFRDMA_CFG1 0x0e4 +#define XUSB_BAR2_ARU_IFRDMA_STREAMID_FIELD 0x0e8 +#define XUSB_BAR2_ARU_C11_CSBRANGE 0x9c +#define XUSB_BAR2_ARU_FW_SCRATCH 0x1000 +#define XUSB_BAR2_CSB_BASE_ADDR 0x2000 + /* IPFS registers */ #define IPFS_XUSB_HOST_MSI_BAR_SZ_0 0x0c0 #define IPFS_XUSB_HOST_MSI_AXI_BAR_ST_0 0x0c4 @@ -111,6 +128,9 @@ #define IMFILLRNG1_TAG_HI_SHIFT 16 #define XUSB_FALC_IMFILLCTL 0x158 +/* CSB ARU registers */ +#define XUSB_CSB_ARU_SCRATCH0 0x100100 + /* MP CSB registers */ #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00 #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04 @@ -131,6 +151,9 @@ #define IMEM_BLOCK_SIZE 256 +#define FW_IOCTL_TYPE_SHIFT 24 +#define FW_IOCTL_CFGTBL_READ 17 + struct tegra_xusb_fw_header { __le32 boot_loadaddr_in_imem; __le32 boot_codedfi_offset; @@ -175,6 +198,7 @@ struct tegra_xusb_mbox_regs { u16 data_in; u16 data_out; u16 owner; + u16 smi_intr; }; struct tegra_xusb_context_soc { @@ -189,6 +213,18 @@ struct tegra_xusb_context_soc { } fpci; }; +struct tegra_xusb; +struct tegra_xusb_soc_ops { + u32 (*mbox_reg_readl)(struct tegra_xusb *tegra, + unsigned int offset); + void (*mbox_reg_writel)(struct tegra_xusb *tegra, + u32 value, unsigned int offset); + u32 (*csb_reg_readl)(struct tegra_xusb *tegra, + unsigned int offset); + void (*csb_reg_writel)(struct tegra_xusb *tegra, + u32 value, unsigned int offset); +}; + struct tegra_xusb_soc { const char *firmware; const char * const *supply_names; @@ -205,11 +241,14 @@ struct tegra_xusb_soc { } ports; struct tegra_xusb_mbox_regs mbox; + const struct tegra_xusb_soc_ops *ops; bool scale_ss_clock; bool has_ipfs; bool lpm_support; bool otg_reset_sspi; + + bool has_bar2; }; struct tegra_xusb_context { @@ -230,6 +269,8 @@ struct tegra_xusb { void __iomem *ipfs_base; void __iomem *fpci_base; + void __iomem *bar2_base; + struct resource *bar2; const struct tegra_xusb_soc *soc; @@ -300,7 +341,33 @@ static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value, writel(value, tegra->ipfs_base + offset); } +static inline u32 bar2_readl(struct tegra_xusb *tegra, unsigned int offset) +{ + return readl(tegra->bar2_base + offset); +} + +static inline void bar2_writel(struct tegra_xusb *tegra, u32 value, + unsigned int offset) +{ + writel(value, tegra->bar2_base + offset); +} + static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset) +{ + const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; + + return ops->csb_reg_readl(tegra, offset); +} + +static void csb_writel(struct tegra_xusb *tegra, u32 value, + unsigned int offset) +{ + const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; + + ops->csb_reg_writel(tegra, value, offset); +} + +static u32 fpci_csb_readl(struct tegra_xusb *tegra, unsigned int offset) { u32 page = CSB_PAGE_SELECT(offset); u32 ofs = CSB_PAGE_OFFSET(offset); @@ -310,7 +377,7 @@ static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset) return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs); } -static void csb_writel(struct tegra_xusb *tegra, u32 value, +static void fpci_csb_writel(struct tegra_xusb *tegra, u32 value, unsigned int offset) { u32 page = CSB_PAGE_SELECT(offset); @@ -320,6 +387,26 @@ static void csb_writel(struct tegra_xusb *tegra, u32 value, fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs); } +static u32 bar2_csb_readl(struct tegra_xusb *tegra, unsigned int offset) +{ + u32 page = CSB_PAGE_SELECT(offset); + u32 ofs = CSB_PAGE_OFFSET(offset); + + bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE); + + return bar2_readl(tegra, XUSB_BAR2_CSB_BASE_ADDR + ofs); +} + +static void bar2_csb_writel(struct tegra_xusb *tegra, u32 value, + unsigned int offset) +{ + u32 page = CSB_PAGE_SELECT(offset); + u32 ofs = CSB_PAGE_OFFSET(offset); + + bar2_writel(tegra, page, XUSB_BAR2_ARU_C11_CSBRANGE); + bar2_writel(tegra, value, XUSB_BAR2_CSB_BASE_ADDR + ofs); +} + static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra, unsigned long rate) { @@ -451,6 +538,7 @@ static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd) static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, const struct tegra_xusb_mbox_msg *msg) { + const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; bool wait_for_idle = false; u32 value; @@ -459,15 +547,15 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, * ACK/NAK messages. */ if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) { - value = fpci_readl(tegra, tegra->soc->mbox.owner); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); if (value != MBOX_OWNER_NONE) { dev_err(tegra->dev, "mailbox is busy\n"); return -EBUSY; } - fpci_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner); + ops->mbox_reg_writel(tegra, MBOX_OWNER_SW, tegra->soc->mbox.owner); - value = fpci_readl(tegra, tegra->soc->mbox.owner); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); if (value != MBOX_OWNER_SW) { dev_err(tegra->dev, "failed to acquire mailbox\n"); return -EBUSY; @@ -477,17 +565,17 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, } value = tegra_xusb_mbox_pack(msg); - fpci_writel(tegra, value, tegra->soc->mbox.data_in); + ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.data_in); - value = fpci_readl(tegra, tegra->soc->mbox.cmd); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd); value |= MBOX_INT_EN | MBOX_DEST_FALC; - fpci_writel(tegra, value, tegra->soc->mbox.cmd); + ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd); if (wait_for_idle) { unsigned long timeout = jiffies + msecs_to_jiffies(250); while (time_before(jiffies, timeout)) { - value = fpci_readl(tegra, tegra->soc->mbox.owner); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); if (value == MBOX_OWNER_NONE) break; @@ -495,7 +583,7 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, } if (time_after(jiffies, timeout)) - value = fpci_readl(tegra, tegra->soc->mbox.owner); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.owner); if (value != MBOX_OWNER_NONE) return -ETIMEDOUT; @@ -507,11 +595,12 @@ static int tegra_xusb_mbox_send(struct tegra_xusb *tegra, static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data) { struct tegra_xusb *tegra = data; + const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; u32 value; /* clear mailbox interrupts */ - value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR); - fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.smi_intr); + ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.smi_intr); if (value & MBOX_SMI_INTR_FW_HANG) dev_err(tegra->dev, "controller firmware hang\n"); @@ -664,6 +753,7 @@ static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra, static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data) { struct tegra_xusb *tegra = data; + const struct tegra_xusb_soc_ops *ops = tegra->soc->ops; struct tegra_xusb_mbox_msg msg; u32 value; @@ -672,16 +762,16 @@ static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data) if (pm_runtime_suspended(tegra->dev) || tegra->suspended) goto out; - value = fpci_readl(tegra, tegra->soc->mbox.data_out); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.data_out); tegra_xusb_mbox_unpack(&msg, value); - value = fpci_readl(tegra, tegra->soc->mbox.cmd); + value = ops->mbox_reg_readl(tegra, tegra->soc->mbox.cmd); value &= ~MBOX_DEST_SMI; - fpci_writel(tegra, value, tegra->soc->mbox.cmd); + ops->mbox_reg_writel(tegra, value, tegra->soc->mbox.cmd); /* clear mailbox owner if no ACK/NAK is required */ if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd)) - fpci_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner); + ops->mbox_reg_writel(tegra, MBOX_OWNER_NONE, tegra->soc->mbox.owner); tegra_xusb_mbox_handle(tegra, &msg); @@ -709,6 +799,15 @@ static void tegra_xusb_config(struct tegra_xusb *tegra) value |= regs & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT); fpci_writel(tegra, value, XUSB_CFG_4); + /* Program BAR2 space */ + if (tegra->bar2) { + value = fpci_readl(tegra, XUSB_CFG_7); + value &= ~(XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT); + value |= tegra->bar2->start & + (XUSB_BASE2_ADDR_MASK << XUSB_BASE2_ADDR_SHIFT); + fpci_writel(tegra, value, XUSB_CFG_7); + } + usleep_range(100, 200); /* Enable bus master */ @@ -881,21 +980,36 @@ static int tegra_xusb_request_firmware(struct tegra_xusb *tegra) return 0; } -static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) +static int tegra_xusb_wait_for_falcon(struct tegra_xusb *tegra) +{ + struct xhci_cap_regs __iomem *cap_regs; + struct xhci_op_regs __iomem *op_regs; + int ret; + u32 value; + + cap_regs = tegra->regs; + op_regs = tegra->regs + HC_LENGTH(readl(&cap_regs->hc_capbase)); + + ret = readl_poll_timeout(&op_regs->status, value, !(value & STS_CNR), 1000, 200000); + + if (ret) + dev_err(tegra->dev, "XHCI Controller not ready. Falcon state: 0x%x\n", + csb_readl(tegra, XUSB_FALC_CPUCTL)); + + return ret; +} + +static int tegra_xusb_load_firmware_rom(struct tegra_xusb *tegra) { unsigned int code_tag_blocks, code_size_blocks, code_blocks; - struct xhci_cap_regs __iomem *cap = tegra->regs; struct tegra_xusb_fw_header *header; struct device *dev = tegra->dev; - struct xhci_op_regs __iomem *op; - unsigned long timeout; time64_t timestamp; u64 address; u32 value; int err; header = (struct tegra_xusb_fw_header *)tegra->fw.virt; - op = tegra->regs + HC_LENGTH(readl(&cap->hc_capbase)); if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) { dev_info(dev, "Firmware already loaded, Falcon state %#x\n", @@ -968,30 +1082,55 @@ static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) /* Boot Falcon CPU and wait for USBSTS_CNR to get cleared. */ csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL); - timeout = jiffies + msecs_to_jiffies(200); + if (tegra_xusb_wait_for_falcon(tegra)) + return -EIO; + + timestamp = le32_to_cpu(header->fwimg_created_time); - do { - value = readl(&op->status); - if ((value & STS_CNR) == 0) - break; + dev_info(dev, "Firmware timestamp: %ptTs UTC\n", ×tamp); + + return 0; +} + +static u32 tegra_xusb_read_firmware_header(struct tegra_xusb *tegra, u32 offset) +{ + /* + * We only accept reading the firmware config table + * The offset should not exceed the fw header structure + */ + if (offset >= sizeof(struct tegra_xusb_fw_header)) + return 0; - usleep_range(1000, 2000); - } while (time_is_after_jiffies(timeout)); + bar2_writel(tegra, (FW_IOCTL_CFGTBL_READ << FW_IOCTL_TYPE_SHIFT) | offset, + XUSB_BAR2_ARU_FW_SCRATCH); + return bar2_readl(tegra, XUSB_BAR2_ARU_SMI_ARU_FW_SCRATCH_DATA0); +} + +static int tegra_xusb_init_ifr_firmware(struct tegra_xusb *tegra) +{ + time64_t timestamp; - value = readl(&op->status); - if (value & STS_CNR) { - value = csb_readl(tegra, XUSB_FALC_CPUCTL); - dev_err(dev, "XHCI controller not read: %#010x\n", value); + if (tegra_xusb_wait_for_falcon(tegra)) return -EIO; - } - timestamp = le32_to_cpu(header->fwimg_created_time); +#define offsetof_32(X, Y) ((u8)(offsetof(X, Y) / sizeof(__le32))) + timestamp = tegra_xusb_read_firmware_header(tegra, + offsetof_32(struct tegra_xusb_fw_header, + fwimg_created_time) << 2); - dev_info(dev, "Firmware timestamp: %ptTs UTC\n", ×tamp); + dev_info(tegra->dev, "Firmware timestamp: %ptTs UTC\n", ×tamp); return 0; } +static int tegra_xusb_load_firmware(struct tegra_xusb *tegra) +{ + if (!tegra->soc->firmware) + return tegra_xusb_init_ifr_firmware(tegra); + else + return tegra_xusb_load_firmware_rom(tegra); +} + static void tegra_xusb_powerdomain_remove(struct device *dev, struct tegra_xusb *tegra) { @@ -1435,6 +1574,10 @@ static int tegra_xusb_probe(struct platform_device *pdev) tegra->ipfs_base = devm_platform_ioremap_resource(pdev, 2); if (IS_ERR(tegra->ipfs_base)) return PTR_ERR(tegra->ipfs_base); + } else if (tegra->soc->has_bar2) { + tegra->bar2_base = devm_platform_get_and_ioremap_resource(pdev, 2, &tegra->bar2); + if (IS_ERR(tegra->bar2_base)) + return PTR_ERR(tegra->bar2_base); } tegra->xhci_irq = platform_get_irq(pdev, 0); @@ -1651,10 +1794,13 @@ static int tegra_xusb_probe(struct platform_device *pdev) goto disable_phy; } - err = tegra_xusb_request_firmware(tegra); - if (err < 0) { - dev_err(&pdev->dev, "failed to request firmware: %d\n", err); - goto disable_phy; + if (tegra->soc->firmware) { + err = tegra_xusb_request_firmware(tegra); + if (err < 0) { + dev_err(&pdev->dev, + "failed to request firmware: %d\n", err); + goto disable_phy; + } } err = tegra_xusb_unpowergate_partitions(tegra); @@ -2271,6 +2417,13 @@ static const struct tegra_xusb_context_soc tegra124_xusb_context = { }, }; +static const struct tegra_xusb_soc_ops tegra124_ops = { + .mbox_reg_readl = &fpci_readl, + .mbox_reg_writel = &fpci_writel, + .csb_reg_readl = &fpci_csb_readl, + .csb_reg_writel = &fpci_csb_writel, +}; + static const struct tegra_xusb_soc tegra124_soc = { .firmware = "nvidia/tegra124/xusb.bin", .supply_names = tegra124_supply_names, @@ -2286,11 +2439,13 @@ static const struct tegra_xusb_soc tegra124_soc = { .scale_ss_clock = true, .has_ipfs = true, .otg_reset_sspi = false, + .ops = &tegra124_ops, .mbox = { .cmd = 0xe4, .data_in = 0xe8, .data_out = 0xec, .owner = 0xf0, + .smi_intr = XUSB_CFG_ARU_SMI_INTR, }, }; MODULE_FIRMWARE("nvidia/tegra124/xusb.bin"); @@ -2322,11 +2477,13 @@ static const struct tegra_xusb_soc tegra210_soc = { .scale_ss_clock = false, .has_ipfs = true, .otg_reset_sspi = true, + .ops = &tegra124_ops, .mbox = { .cmd = 0xe4, .data_in = 0xe8, .data_out = 0xec, .owner = 0xf0, + .smi_intr = XUSB_CFG_ARU_SMI_INTR, }, }; MODULE_FIRMWARE("nvidia/tegra210/xusb.bin"); @@ -2363,11 +2520,13 @@ static const struct tegra_xusb_soc tegra186_soc = { .scale_ss_clock = false, .has_ipfs = false, .otg_reset_sspi = false, + .ops = &tegra124_ops, .mbox = { .cmd = 0xe4, .data_in = 0xe8, .data_out = 0xec, .owner = 0xf0, + .smi_intr = XUSB_CFG_ARU_SMI_INTR, }, .lpm_support = true, }; @@ -2394,21 +2553,56 @@ static const struct tegra_xusb_soc tegra194_soc = { .scale_ss_clock = false, .has_ipfs = false, .otg_reset_sspi = false, + .ops = &tegra124_ops, .mbox = { .cmd = 0x68, .data_in = 0x6c, .data_out = 0x70, .owner = 0x74, + .smi_intr = XUSB_CFG_ARU_SMI_INTR, }, .lpm_support = true, }; MODULE_FIRMWARE("nvidia/tegra194/xusb.bin"); +static const struct tegra_xusb_soc_ops tegra234_ops = { + .mbox_reg_readl = &bar2_readl, + .mbox_reg_writel = &bar2_writel, + .csb_reg_readl = &bar2_csb_readl, + .csb_reg_writel = &bar2_csb_writel, +}; + +static const struct tegra_xusb_soc tegra234_soc = { + .supply_names = tegra194_supply_names, + .num_supplies = ARRAY_SIZE(tegra194_supply_names), + .phy_types = tegra194_phy_types, + .num_types = ARRAY_SIZE(tegra194_phy_types), + .context = &tegra186_xusb_context, + .ports = { + .usb3 = { .offset = 0, .count = 4, }, + .usb2 = { .offset = 4, .count = 4, }, + }, + .scale_ss_clock = false, + .has_ipfs = false, + .otg_reset_sspi = false, + .ops = &tegra234_ops, + .mbox = { + .cmd = XUSB_BAR2_ARU_MBOX_CMD, + .data_in = XUSB_BAR2_ARU_MBOX_DATA_IN, + .data_out = XUSB_BAR2_ARU_MBOX_DATA_OUT, + .owner = XUSB_BAR2_ARU_MBOX_OWNER, + .smi_intr = XUSB_BAR2_ARU_SMI_INTR, + }, + .lpm_support = true, + .has_bar2 = true, +}; + static const struct of_device_id tegra_xusb_of_match[] = { { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc }, { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc }, { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc }, { .compatible = "nvidia,tegra194-xusb", .data = &tegra194_soc }, + { .compatible = "nvidia,tegra234-xusb", .data = &tegra234_soc }, { }, }; MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);