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Fri, 11 Nov 2022 15:48:10 +0000 From: Frank Li To: shawnguo@kernel.org Cc: Frank.Li@nxp.com, aisheng.dong@nxp.com, devicetree@vger.kernel.org, festevam@gmail.com, han.xu@nxp.com, imx@lists.linux.dev, kernel@pengutronix.de, krzysztof.kozlowski+dt@linaro.org, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, peng.fan@nxp.com, robh+dt@kernel.org, s.hauer@pengutronix.de, shenwei.wang@nxp.com Subject: [PATCH v2 1/6] arm64: dts: imx8dxl: add adc0 support Date: Fri, 11 Nov 2022 10:47:37 -0500 Message-Id: <20221111154742.2753318-2-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111154742.2753318-1-Frank.Li@nxp.com> References: <20221111154742.2753318-1-Frank.Li@nxp.com> X-ClientProxiedBy: BYAPR05CA0046.namprd05.prod.outlook.com (2603:10b6:a03:74::23) To HE1PR0401MB2331.eurprd04.prod.outlook.com (2603:10a6:3:24::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: HE1PR0401MB2331:EE_|DB8PR04MB6969:EE_ X-MS-Office365-Filtering-Correlation-Id: ae86a1ed-8270-463e-48fb-08dac3fc224d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Change irq number for adc0. Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 52 +++++++++++++++++++ .../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 4 ++ 2 files changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index d7b4229bb4a2..bdbb660c2682 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -156,6 +156,34 @@ i2c3: i2c@5a830000 { status = "disabled"; }; + adc0: adc@5a880000 { + compatible = "nxp,imx8qxp-adc"; + reg = <0x5a880000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adc0_lpcg 0>, + <&adc0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_ADC_0>; + status = "disabled"; + }; + + adc1: adc@5a890000 { + compatible = "nxp,imx8qxp-adc"; + reg = <0x5a890000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&adc1_lpcg 0>, + <&adc1_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + power-domains = <&pd IMX_SC_R_ADC_1>; + status = "disabled"; + }; + i2c0_lpcg: clock-controller@5ac00000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5ac00000 0x10000>; @@ -203,4 +231,28 @@ i2c3_lpcg: clock-controller@5ac30000 { "i2c3_lpcg_ipg_clk"; power-domains = <&pd IMX_SC_R_I2C_3>; }; + + adc0_lpcg: clock-controller@5ac80000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac80000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_ADC_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "adc0_lpcg_clk", + "adc0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ADC_0>; + }; + + adc1_lpcg: clock-controller@5ac90000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5ac90000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_ADC_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "adc1_lpcg_clk", + "adc1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_ADC_1>; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi index 795d1d472fae..ac3362e32811 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi @@ -11,6 +11,10 @@ &dma_ipg_clk { clock-frequency = <160000000>; }; +&adc0 { + interrupts = ; +}; + &i2c0 { compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = ; From patchwork Fri Nov 11 15:47:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 624019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 845C0C433FE for ; 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Change flexspi0 irq number for imx8dxl. Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 17 ++++++++++++++++- .../boot/dts/freescale/imx8dxl-ss-lsio.dtsi | 5 +++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index 6446e6df7a9a..1f3d225e64ec 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -11,7 +11,8 @@ lsio_subsys: bus@5d000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0x5d000000 0x0 0x5d000000 0x1000000>; + ranges = <0x5d000000 0x0 0x5d000000 0x1000000>, + <0x08000000 0x0 0x08000000 0x10000000>; lsio_mem_clk: clock-lsio-mem { compatible = "fixed-clock"; @@ -107,6 +108,20 @@ lsio_gpio7: gpio@5d0f0000 { power-domains = <&pd IMX_SC_R_GPIO_7>; }; + flexspi0: spi@5d120000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8qxp-fspi"; + reg = <0x5d120000 0x10000>, <0x08000000 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = ; + clocks = <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_FSPI_0 IMX_SC_PM_CLK_PER>; + clock-names = "fspi", "fspi_en"; + power-domains = <&pd IMX_SC_R_FSPI_0>; + status = "disabled"; + }; + lsio_mu0: mailbox@5d1b0000 { reg = <0x5d1b0000 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi index 815bd987b09b..85e6131ec406 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi @@ -3,6 +3,11 @@ * Copyright 2019~2020, 2022 NXP */ +&flexspi0 { + compatible = "nxp,imx8dxl-fspi"; + interrupts = ; +}; + &lsio_gpio0 { compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio"; interrupts = ; From patchwork Fri Nov 11 15:47:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 624018 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34A98C433FE for ; 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Change irq number for 8dxl. Signed-off-by: Frank Li --- .../arm64/boot/dts/freescale/imx8-ss-dma.dtsi | 112 ++++++++++++++++++ .../boot/dts/freescale/imx8dxl-ss-adma.dtsi | 16 +++ 2 files changed, 128 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index bdbb660c2682..a943a1e2797f 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -20,6 +20,70 @@ dma_ipg_clk: clock-dma-ipg { clock-output-names = "dma_ipg_clk"; }; + lpspi0: spi@5a000000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a000000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&spi0_lpcg 0>, + <&spi0_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <20000000>; + power-domains = <&pd IMX_SC_R_SPI_0>; + status = "disabled"; + }; + + lpspi1: spi@5a010000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a010000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&spi1_lpcg 0>, + <&spi1_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_1>; + status = "disabled"; + }; + + lpspi2: spi@5a020000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a020000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&spi2_lpcg 0>, + <&spi2_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_2>; + status = "disabled"; + }; + + lpspi3: spi@5a030000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x5a030000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&spi3_lpcg 0>, + <&spi3_lpcg 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <60000000>; + power-domains = <&pd IMX_SC_R_SPI_3>; + status = "disabled"; + }; + lpuart0: serial@5a060000 { reg = <0x5a060000 0x1000>; interrupts = ; @@ -60,6 +124,54 @@ lpuart3: serial@5a090000 { status = "disabled"; }; + spi0_lpcg: clock-controller@5a400000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a400000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "spi0_lpcg_clk", + "spi0_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_0>; + }; + + spi1_lpcg: clock-controller@5a410000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a410000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_1 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "spi1_lpcg_clk", + "spi1_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_1>; + }; + + spi2_lpcg: clock-controller@5a420000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a420000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_2 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "spi2_lpcg_clk", + "spi2_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_2>; + }; + + spi3_lpcg: clock-controller@5a430000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a430000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_SPI_3 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = , ; + clock-output-names = "spi3_lpcg_clk", + "spi3_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_SPI_3>; + }; + uart0_lpcg: clock-controller@5a460000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a460000 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi index ac3362e32811..6881330ab4c6 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi @@ -54,3 +54,19 @@ &lpuart3 { compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; interrupts = ; }; + +&lpspi0 { + interrupts = ; +}; + +&lpspi1 { + interrupts = ; +}; + +&lpspi2 { + interrupts = ; +}; + +&lpspi3 { + interrupts = ; +};