From patchwork Thu Nov 10 19:22:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 623381 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 771AAC433FE for ; Thu, 10 Nov 2022 19:22:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230173AbiKJTWy (ORCPT ); Thu, 10 Nov 2022 14:22:54 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229591AbiKJTWx (ORCPT ); Thu, 10 Nov 2022 14:22:53 -0500 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A81C8218A for ; Thu, 10 Nov 2022 11:22:51 -0800 (PST) Received: by mail-lf1-x12e.google.com with SMTP id r12so5078168lfp.1 for ; Thu, 10 Nov 2022 11:22:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2UIsc+krPU1fGDfYe329apj6IkVzAs3KMEB9BP123HE=; b=xGsM2EAqwLZkorkLw2taqh3SSEK5T9RvT5LE0v8o0+f3q3wm/g9txVkNQ+hZp5/dXD BN9Hi2CUksCV8LCOLWpBnn9pgKhNa44Gt2JPutTERmbMPjvqWaNwrsLNQKsv5Qo2nCnK gOaXzc5qWhs5avgmf7V87AaXwEGEGkwnd+FkMVBMb8TivH0qJmIKzpF8vYf+4ParW1t2 ABAHJDpyzWVzgIhvRcr1DVc/H5WgYogLvlf77gmlRF5tVfl5q+WHNeHjNtKlFjrAzkNI wHl6GoxlKOwLctZdtN1zFne428sshFayuGcrloj5FxBmG9h2UvJ4fhyS/r9GDi2YNaCr 4SkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2UIsc+krPU1fGDfYe329apj6IkVzAs3KMEB9BP123HE=; b=q5XxUpsPWhOp1eZ939qk7NsgY+U6xK6sdIxvSIMKUbk1WWnUnlda8msTXRUkN8ZCof U4YMW7fgFgrvsq5l+60rs+31gfPxFxos43q3NfmC4FRxDoiEQz4w73mgL3M2vxPMZeLO Ur4UxkW3cRFN3iEX6ez6jJUX6DYLtiNaMPZwsMNXYLztd+Z+vhNWAE5/t88pwklSuWhl r6BGxq7gBiGXLuBLh2vEGvMhaBXWdsDXejdHukltPht/k1Gqz/T+B69PFT+hoKR1+0Er i/EUy7X0zDp7Fsy8EpDAs6dNt5DgJiyIINxkRxN6et+NLbbPckfV9mRoJtvXkjOKEYKg 49cQ== X-Gm-Message-State: ACrzQf2Yqkh8gOkcjpjz0cCjDvsAT9nf4CXQTAMuJqZau1FyvBKFL3bD Hu4MIO32yL5Uxf0uLvmdIhKqig== X-Google-Smtp-Source: AMsMyM7NS4nGToVkCC13upgnbeWT7NN05gXMSURAxNNTIE9HTHL4AQQDp0nTw2DXzJzoCihtZmd0kA== X-Received: by 2002:ac2:58e3:0:b0:4b0:fa45:9423 with SMTP id v3-20020ac258e3000000b004b0fa459423mr1892081lfo.154.1668108170073; Thu, 10 Nov 2022 11:22:50 -0800 (PST) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id h8-20020a05651c124800b0027758f0619fsm40345ljh.132.2022.11.10.11.22.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Nov 2022 11:22:49 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v3 01/13] phy: qcom-qmp: fix typo in QSERDES_COM_CMN_RSVD5 value Date: Thu, 10 Nov 2022 22:22:36 +0300 Message-Id: <20221110192248.873973-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> References: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Fix typo in QSERDES_COM_CMN_RSVD5 register definition. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h index fbaf6ef467f8..7fa5363feeb9 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com.h @@ -135,6 +135,6 @@ #define QSERDES_COM_CMN_MISC2 0x1b8 #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc #define QSERDES_COM_CORECLK_DIV_MODE2 0x1c0 -#define QSERDES_COM_CMN_RSVD5 0x1c0 +#define QSERDES_COM_CMN_RSVD5 0x1c4 #endif From patchwork Thu Nov 10 19:22:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 623380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DA48C43217 for ; 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Thu, 10 Nov 2022 11:22:50 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v3 02/13] phy: qcom-qmp: remove duplicate v5_5nm register definitions Date: Thu, 10 Nov 2022 22:22:37 +0300 Message-Id: <20221110192248.873973-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> References: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Remove duplicate defines from phy-qcom-qmp-qserdes-txrx-v5_5nm.h Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h index a1c088bd5158..a4a4e251348d 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v5_5nm.h @@ -7,11 +7,6 @@ #define QCOM_PHY_QMP_QSERDES_TXRX_V5_5NM_H_ /* Only for QMP V5 5NM PHY - TX registers */ -#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX 0x30 -#define QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX 0x34 -#define QSERDES_V5_5NM_TX_LANE_MODE_1 0x78 -#define QSERDES_V5_5NM_TX_LANE_MODE_2 0x7c -#define QSERDES_V5_5NM_TX_LANE_MODE_3 0x80 #define QSERDES_V5_5NM_TX_BIST_MODE_LANENO 0x00 #define QSERDES_V5_5NM_TX_BIST_INVERT 0x04 #define QSERDES_V5_5NM_TX_CLKBUF_ENABLE 0x08 From patchwork Thu Nov 10 19:22:38 2022 Content-Type: text/plain; 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Thu, 10 Nov 2022 11:22:51 -0800 (PST) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id h8-20020a05651c124800b0027758f0619fsm40345ljh.132.2022.11.10.11.22.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Nov 2022 11:22:51 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v3 03/13] phy: qcom-qmp-pcie: rework regs layout arrays Date: Thu, 10 Nov 2022 22:22:38 +0300 Message-Id: <20221110192248.873973-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> References: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use symbolic names for the values inside reg layout arrays. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 32 +++++++++++----------- drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h | 4 +++ 2 files changed, 20 insertions(+), 16 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 8fa66458c259..7de0ac23ff0b 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -77,24 +77,24 @@ enum qphy_reg_layout { }; static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x44, - [QPHY_PCS_STATUS] = 0x14, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, + [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, }; static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x08, - [QPHY_PCS_STATUS] = 0x174, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, + [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL, }; static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x08, - [QPHY_PCS_STATUS] = 0x174, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, + [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, }; static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { @@ -105,10 +105,10 @@ static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { }; static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x44, - [QPHY_PCS_STATUS] = 0x14, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, + [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, }; static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h index c8515f506872..2624a1ec3e73 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h @@ -7,7 +7,9 @@ #define QCOM_PHY_QMP_PCS_V2_H_ /* Only for QMP V2 PHY - PCS registers */ +#define QPHY_V2_PCS_SW_RESET 0x000 #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004 +#define QPHY_V2_PCS_START_CONTROL 0x008 #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024 #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028 #define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x034 @@ -43,4 +45,6 @@ #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 +#define QPHY_V2_PCS_PCI_PCS_STATUS 0x174 /* PCI */ + #endif From patchwork Thu Nov 10 19:22:39 2022 Content-Type: text/plain; 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Thu, 10 Nov 2022 11:22:52 -0800 (PST) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id h8-20020a05651c124800b0027758f0619fsm40345ljh.132.2022.11.10.11.22.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Nov 2022 11:22:51 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v3 04/13] phy: qcom-qmp-pcie: rename regs layout arrays Date: Thu, 10 Nov 2022 22:22:39 +0300 Message-Id: <20221110192248.873973-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> References: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rename regs layouts to follow the QMP PHY version. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 52 +++++++++++----------- drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 4 ++ 2 files changed, 30 insertions(+), 26 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 7de0ac23ff0b..4bab804a2ed8 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -76,21 +76,14 @@ enum qphy_reg_layout { QPHY_LAYOUT_SIZE }; -static const unsigned int ipq_pciephy_gen3_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, - [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, - [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, - [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, -}; - -static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { +static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL, }; -static const unsigned int sdm845_qmp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { +static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, @@ -104,13 +97,20 @@ static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, }; -static const unsigned int sm8250_pcie_regs_layout[QPHY_LAYOUT_SIZE] = { +static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, }; +static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, +}; + static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), @@ -1678,7 +1678,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_cfg = { .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), .vreg_list = NULL, .num_vregs = 0, - .regs = pciephy_regs_layout, + .regs = pciephy_v2_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS, @@ -1705,7 +1705,7 @@ static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = { .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), .vreg_list = NULL, .num_vregs = 0, - .regs = ipq_pciephy_gen3_regs_layout, + .regs = pciephy_v4_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS, @@ -1734,7 +1734,7 @@ static const struct qmp_phy_cfg ipq6018_pciephy_cfg = { .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), .vreg_list = NULL, .num_vregs = 0, - .regs = ipq_pciephy_gen3_regs_layout, + .regs = pciephy_v4_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS, @@ -1761,7 +1761,7 @@ static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sdm845_qmp_pciephy_regs_layout, + .regs = pciephy_v3_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS, @@ -1823,7 +1823,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8250_pcie_regs_layout, + .regs = pciephy_v4_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS, @@ -1860,7 +1860,7 @@ static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8250_pcie_regs_layout, + .regs = pciephy_v4_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS, @@ -1885,7 +1885,7 @@ static const struct qmp_phy_cfg msm8998_pciephy_cfg = { .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = pciephy_regs_layout, + .regs = pciephy_v3_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS, @@ -1914,7 +1914,7 @@ static const struct qmp_phy_cfg sc8180x_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8250_pcie_regs_layout, + .regs = pciephy_v4_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS, @@ -1949,7 +1949,7 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8250_pcie_regs_layout, + .regs = pciephy_v5_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS, @@ -1984,7 +1984,7 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8250_pcie_regs_layout, + .regs = pciephy_v5_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS, @@ -2022,7 +2022,7 @@ static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8250_pcie_regs_layout, + .regs = pciephy_v5_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS, @@ -2049,7 +2049,7 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8250_pcie_regs_layout, + .regs = pciephy_v4_regs_layout, .pwrdn_ctrl = SW_PWRDN, .phy_status = PHYSTATUS_4_20, @@ -2086,7 +2086,7 @@ static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8250_pcie_regs_layout, + .regs = pciephy_v5_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS, @@ -2123,7 +2123,7 @@ static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8250_pcie_regs_layout, + .regs = pciephy_v5_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS, @@ -2158,7 +2158,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8250_pcie_regs_layout, + .regs = pciephy_v4_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS, @@ -2200,7 +2200,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8250_pcie_regs_layout, + .regs = pciephy_v5_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h index 04f260711ea1..36cc80bb9059 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h @@ -7,6 +7,10 @@ #define QCOM_PHY_QMP_PCS_V5_H_ /* Only for QMP V5 PHY - USB/PCIe PCS registers */ +#define QPHY_V5_PCS_SW_RESET 0x000 +#define QPHY_V5_PCS_PCS_STATUS1 0x014 +#define QPHY_V5_PCS_POWER_DOWN_CONTROL 0x040 +#define QPHY_V5_PCS_START_CONTROL 0x044 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG1 0x0c4 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG2 0x0c8 #define QPHY_V5_PCS_LOCK_DETECT_CONFIG3 0x0cc From patchwork Thu Nov 10 19:22:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 623921 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3FDAC4167B for ; Thu, 10 Nov 2022 19:22:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230174AbiKJTW6 (ORCPT ); Thu, 10 Nov 2022 14:22:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230168AbiKJTW5 (ORCPT ); Thu, 10 Nov 2022 14:22:57 -0500 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D47B7655 for ; Thu, 10 Nov 2022 11:22:54 -0800 (PST) Received: by mail-lf1-x12f.google.com with SMTP id bp15so4991183lfb.13 for ; Thu, 10 Nov 2022 11:22:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vcPWjds6mbsRpPKp/5SVoMeEsYJwXwMrOPUv6AY8j7w=; b=hWPTENd16gDyfNtE90doqMgenYj/3vA75LrwWv/0LrS0uMCwx0ESxtzbalYTZ3oZKk 4uHFI4UO/Fx/ITkGiNmkO1fDojYrFkkiTI5MvZG0Wtmf2QBq6ZCneh4hPsXLI//CmO1T 18BpolUdU5railfc9gDEjT+wtFgoVpHs+jGFcAFHFow37KhuvQjpe89ZKnunzQhRxS43 xLCEnmING5OjWg4nu007657rNEWMmR8NWzSVK4aA4VT44CQ3lA+RtnnqoarCwdOsosap Z/f6EfKeDLk+n3XYGtJ9XVjgA+LoWQuVHCWa2mxY7yPW7xYT2Ia3m2Iu1iQdo9Vnabkb mbGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vcPWjds6mbsRpPKp/5SVoMeEsYJwXwMrOPUv6AY8j7w=; b=df/4zXfGY7LqwbzSu8yTn2vmQIZgDr2g2ewtWA3ujTVLk9/c1h4iaT1MXF3em3mUds /6ANsw5pGKBJyNsv363UPoS/kNR97ptVhM7JPOiQw9N4vzAtgzs02T0h56FCmGgjYOx9 rKSUR5dshJtumDcRqZeNJ4pUkbdJ+hCzwKjmb/Q2BueIZ8udBl7dnajxG/eZQueG7j+L Co9bcIkQhqX5+pnTjJ7f4zoPVt+YR8km1wIKBaZY+iZAZxI4Xnu7D27BisvkpcXCPYxa ouJlPzIV5n42Yp6XCfOr8idNF5hng6J0V6RgU/L2ydF3H/Lsk8654C5GsNhkesJ1R/m+ Z4sw== X-Gm-Message-State: ACrzQf04WPuwtYJHDwqag17YtE/QWLLtlOUoz7QrVDfFUZcGt+WOlNiI cNsqXxs5sRApEkXt0HICpPEXfA== X-Google-Smtp-Source: AMsMyM58KmcjPSKgeRBdweaOO+IIBjMMbArHcJIRO29TPoIrgAyAd4GioIIozN1yA+R0n1AGUVr7aQ== X-Received: by 2002:a19:f607:0:b0:4a2:4f6d:7963 with SMTP id x7-20020a19f607000000b004a24f6d7963mr1956428lfe.638.1668108172881; Thu, 10 Nov 2022 11:22:52 -0800 (PST) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id h8-20020a05651c124800b0027758f0619fsm40345ljh.132.2022.11.10.11.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Nov 2022 11:22:52 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v3 05/13] phy: qcom-qmp-pcie-msm8996: rework regs layout arrays Date: Thu, 10 Nov 2022 22:22:40 +0300 Message-Id: <20221110192248.873973-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> References: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use symbolic names for the values inside reg layout arrays. New register names are added following the PCS register layout that is used by the particular PHY. Note: ipq8074 tables appear to use a mixture of v2 and v3 registers. This might need additional fixes. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c index ff198d846fd2..b120a7e2e1ec 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c @@ -86,9 +86,9 @@ static const unsigned int pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_COM_POWER_DOWN_CONTROL] = 0x404, [QPHY_COM_START_CONTROL] = 0x408, [QPHY_COM_PCS_READY_STATUS] = 0x448, - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x08, - [QPHY_PCS_STATUS] = 0x174, + [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS, }; static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = { From patchwork Thu Nov 10 19:22:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 623922 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25A43C433FE for ; Thu, 10 Nov 2022 19:22:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230359AbiKJTW5 (ORCPT ); Thu, 10 Nov 2022 14:22:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230142AbiKJTW4 (ORCPT ); Thu, 10 Nov 2022 14:22:56 -0500 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6820B4385A for ; Thu, 10 Nov 2022 11:22:55 -0800 (PST) Received: by mail-lj1-x236.google.com with SMTP id h12so2063585ljg.9 for ; Thu, 10 Nov 2022 11:22:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3BHDXCEc9yM1hAdhh26DgWQ6QnhN+zY09vjuUUwzdXI=; b=DigvrI/JuvwhrVswqn2QTh0i3bytQXypFnvEVK163zU8nrZuOJ/9JUchLfxTOp5yR5 yEUvhud1Fg6sBDiy0f8RcYAv24bQLyngGXdJx5JC1v+12DUSYYSx7qRTXfMA+PXF4XVC IR4GXVTh/UGarD4TPaifW0fv7Q9oBpmpoeukVharWiHUrWPE2CWZ1Ju2tHq5N/qGVh49 CGnkkX+SDjH5LPGHAV6q5mW8ewHqzKgwCaof+tE5yuADJRp/PVjT3HKPoiBml33bSwcf hFHev+4xxKxCydnz3+qNUZgwQduUxzhNgcrmNr6mH+tqkxMS3s6rwk52oA0Rcj7SyAcR FjGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3BHDXCEc9yM1hAdhh26DgWQ6QnhN+zY09vjuUUwzdXI=; b=vb7a1o8Iw7RoQkbg0iSL9yaPQKBztt9YedRDFD53dEyvDxZuQI37zsPkhOHQH7BbMN zOcRuelfNz6daIh5UuM9wGueXCZrHZ1cAbtgUXUpLfeFsx7RhDCW+MnXJ3nKSKYo0DCv 8MjAtsWe8jB91zXlcPnaL/+DiX8sicNhuA4q/5WGZiWW9p+ic8GFHIrE/LjwpUuq65Vi 0vhAt00npLL27opqbCvI1mMbya1HA6y4mMkUh9ZU9s2t9tl3blklTdGwKE5i2lP+YJc2 qG9ySIDcXCHv5AKUlkVCNaYcwGEsABcQj0eDaiTK6i+QzNi++3ZDS3BVVACkI35fGgrp O2cg== X-Gm-Message-State: ACrzQf0Jv5Age6QJq5wcRySSfQGgXNe1wcKiCGOFLWkEBlVVjr/JTG6e zAqdonbiS/5n3jPgPGPp6hYoQg== X-Google-Smtp-Source: AMsMyM69fj7nDpaTmjwctl7AKCpnalTGpxlj8CDwKT+KX2r8AQ9X+e44SFnct0r7qfZPgkocT/xVmg== X-Received: by 2002:a2e:9096:0:b0:26d:d392:2f2e with SMTP id l22-20020a2e9096000000b0026dd3922f2emr9634925ljg.375.1668108173459; Thu, 10 Nov 2022 11:22:53 -0800 (PST) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id h8-20020a05651c124800b0027758f0619fsm40345ljh.132.2022.11.10.11.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Nov 2022 11:22:53 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v3 06/13] phy: qcom-qmp-ufs: split UFS-specific v2 PCS registers to a separate header Date: Thu, 10 Nov 2022 22:22:41 +0300 Message-Id: <20221110192248.873973-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> References: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Follow other QMP headers, split and rename UFS-specific PCS registers to ease comparing regs differences. Signed-off-by: Dmitry Baryshkov --- .../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h | 20 +++++++++++++++++++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h | 11 ---------- drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 18 ++++++++--------- drivers/phy/qualcomm/phy-qcom-qmp.h | 1 + 4 files changed, 30 insertions(+), 20 deletions(-) create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h new file mode 100644 index 000000000000..af870669a904 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017, The Linux Foundation. All rights reserved. + */ + +#ifndef QCOM_PHY_QMP_PCS_UFS_V2_H_ +#define QCOM_PHY_QMP_PCS_UFS_V2_H_ + +#define QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x034 +#define QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL 0x038 +#define QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x03c +#define QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL 0x040 + +#define QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc +#define QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL 0x13c +#define QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME 0x140 +#define QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2 0x148 +#define QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND 0x154 + +#endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h index 2624a1ec3e73..431e9148b8d0 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h @@ -12,10 +12,6 @@ #define QPHY_V2_PCS_START_CONTROL 0x008 #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024 #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028 -#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x034 -#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x038 -#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x03c -#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x040 #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054 #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058 #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060 @@ -32,13 +28,6 @@ #define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8 #define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL 0x0cc #define QPHY_V2_PCS_FLL_MAN_CODE 0x0d0 - -/* UFS only ? */ -#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc -#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c -#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140 -#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148 -#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154 #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 #define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac #define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 78d7daf34667..9a425be05ac2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -244,15 +244,15 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = { }; static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = { - QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_PWM_GEAR_BAND, 0x15), - QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_CTRL2, 0x6d), - QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL, 0x0f), - QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL, 0x02), - QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), - QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SYM_RESYNC_CTRL, 0x03), - QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL, 0x12), - QMP_PHY_INIT_CFG(QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f), - QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL, 0x12), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f), + QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ }; static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 29a48f0436d2..60c52a55f119 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -24,6 +24,7 @@ #include "phy-qcom-qmp-qserdes-pll.h" #include "phy-qcom-qmp-pcs-v2.h" +#include "phy-qcom-qmp-pcs-ufs-v2.h" #include "phy-qcom-qmp-pcs-v3.h" #include "phy-qcom-qmp-pcs-misc-v3.h" From patchwork Thu Nov 10 19:22:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 623377 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA395C43217 for ; Thu, 10 Nov 2022 19:22:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230168AbiKJTW6 (ORCPT ); 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Thu, 10 Nov 2022 11:22:53 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v3 07/13] phy: qcom-qmp-ufs: rework regs layout arrays Date: Thu, 10 Nov 2022 22:22:42 +0300 Message-Id: <20221110192248.873973-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> References: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use symbolic names for the values inside reg layout arrays. New register names are added following the PCS register layout that is used by the particular PHY. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h | 5 +++++ drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h | 3 +++ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 18 +++++++++--------- 3 files changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h index af870669a904..a0803a8783d2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v2.h @@ -6,6 +6,9 @@ #ifndef QCOM_PHY_QMP_PCS_UFS_V2_H_ #define QCOM_PHY_QMP_PCS_UFS_V2_H_ +#define QPHY_V2_PCS_UFS_PHY_START 0x000 +#define QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL 0x004 + #define QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x034 #define QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL 0x038 #define QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x03c @@ -17,4 +20,6 @@ #define QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2 0x148 #define QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND 0x154 +#define QPHY_V2_PCS_UFS_READY_STATUS 0x168 + #endif diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h index ba1ea29d2884..adea13c3a9e6 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v3.h @@ -6,12 +6,15 @@ #ifndef QCOM_PHY_QMP_PCS_UFS_V3_H_ #define QCOM_PHY_QMP_PCS_UFS_V3_H_ +#define QPHY_V3_PCS_UFS_PHY_START 0x000 +#define QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL 0x004 #define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x02c #define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x034 #define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL 0x134 #define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME 0x138 #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1 0x13c #define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2 0x140 +#define QPHY_V3_PCS_UFS_READY_STATUS 0x160 #define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1 0x1bc #define QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1 0x1c4 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 9a425be05ac2..8a7a3bfbd8d3 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -72,21 +72,21 @@ enum qphy_reg_layout { }; static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_START_CTRL] = 0x00, - [QPHY_PCS_READY_STATUS] = 0x168, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, + [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START, + [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL, }; static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_START_CTRL] = 0x00, - [QPHY_PCS_READY_STATUS] = 0x160, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, + [QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START, + [QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL, }; static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_START_CTRL] = 0x00, - [QPHY_PCS_READY_STATUS] = 0x168, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, + [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START, + [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL, }; static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { From patchwork Thu Nov 10 19:22:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 623376 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EC9EC4321E for ; Thu, 10 Nov 2022 19:23:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230237AbiKJTW7 (ORCPT ); Thu, 10 Nov 2022 14:22:59 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230323AbiKJTW5 (ORCPT ); Thu, 10 Nov 2022 14:22:57 -0500 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F8A145A12 for ; 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Signed-off-by: Dmitry Baryshkov --- .../phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h | 4 +++ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 33 ++++++++++--------- 2 files changed, 21 insertions(+), 16 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h index bcca23493b7e..43255e8bf038 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-ufs-v5.h @@ -8,6 +8,9 @@ #define QCOM_PHY_QMP_PCS_UFS_V5_H_ /* Only for QMP V5 PHY - UFS PCS registers */ +#define QPHY_V5_PCS_UFS_PHY_START 0x000 +#define QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL 0x004 +#define QPHY_V5_PCS_UFS_SW_RESET 0x008 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c @@ -21,6 +24,7 @@ #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 +#define QPHY_V5_PCS_UFS_READY_STATUS 0x180 #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index 8a7a3bfbd8d3..c9698e17b617 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -71,31 +71,32 @@ enum qphy_reg_layout { QPHY_LAYOUT_SIZE }; -static const unsigned int msm8996_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { +static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START, [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL, }; -static const unsigned int sdm845_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { +static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START, [QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL, }; -static const unsigned int sm6115_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START, - [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS, - [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL, -}; - -static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { +static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, }; +static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START, + [QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS, + [QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL, +}; + static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), @@ -647,7 +648,7 @@ static const struct qmp_phy_cfg msm8996_ufs_cfg = { .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = msm8996_ufsphy_regs_layout, + .regs = ufsphy_v2_regs_layout, .no_pcs_sw_reset = true, }; @@ -669,7 +670,7 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = { .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8150_ufsphy_regs_layout, + .regs = ufsphy_v5_regs_layout, }; static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { @@ -687,7 +688,7 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sdm845_ufsphy_regs_layout, + .regs = ufsphy_v3_regs_layout, .no_pcs_sw_reset = true, }; @@ -707,7 +708,7 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm6115_ufsphy_regs_layout, + .regs = ufsphy_v2_regs_layout, .no_pcs_sw_reset = true, }; @@ -727,7 +728,7 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8150_ufsphy_regs_layout, + .regs = ufsphy_v4_regs_layout, }; static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { @@ -745,7 +746,7 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8150_ufsphy_regs_layout, + .regs = ufsphy_v5_regs_layout, }; static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { @@ -763,7 +764,7 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = sm8150_ufsphy_regs_layout, + .regs = ufsphy_v5_regs_layout, }; static void qmp_ufs_configure_lane(void __iomem *base, From patchwork Thu Nov 10 19:22:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 623378 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FF9EC4332F for ; Thu, 10 Nov 2022 19:22:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230142AbiKJTW5 (ORCPT ); Thu, 10 Nov 2022 14:22:57 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230174AbiKJTW4 (ORCPT ); Thu, 10 Nov 2022 14:22:56 -0500 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA04D45A33 for ; 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Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 6 ------ 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h index 431e9148b8d0..c7e8e2a28e6e 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h @@ -28,6 +28,7 @@ #define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8 #define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL 0x0cc #define QPHY_V2_PCS_FLL_MAN_CODE 0x0d0 +#define QPHY_V2_PCS_LFPS_RXTERM_IRQ_STATUS 0x178 #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 #define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac #define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index 55029ea63f73..3d920a834486 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -56,9 +56,6 @@ /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ #define IRQ_CLEAR BIT(0) -/* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */ -#define RCVR_DETECT BIT(0) - /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ @@ -96,7 +93,6 @@ enum qphy_reg_layout { QPHY_PCS_STATUS, QPHY_PCS_AUTONOMOUS_MODE_CTRL, QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, - QPHY_PCS_LFPS_RXTERM_IRQ_STATUS, QPHY_PCS_POWER_DOWN_CONTROL, /* PCS_MISC registers */ QPHY_PCS_MISC_TYPEC_CTRL, @@ -110,7 +106,6 @@ static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_STATUS] = 0x17c, [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4, [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8, - [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178, [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, }; @@ -120,7 +115,6 @@ static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_STATUS] = 0x174, [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, - [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170, [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, }; From patchwork Thu Nov 10 19:22:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 623920 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF42AC43219 for ; Thu, 10 Nov 2022 19:23:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229757AbiKJTXA (ORCPT ); Thu, 10 Nov 2022 14:23:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230342AbiKJTW5 (ORCPT ); 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Thu, 10 Nov 2022 11:22:55 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v3 10/13] phy: qcom-qmp-usb: remove QPHY_PCS_MISC_TYPEC_CTRL reg Date: Thu, 10 Nov 2022 22:22:45 +0300 Message-Id: <20221110192248.873973-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> References: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The QPHY_PCS_MISC_TYPEC_CTRL register is not used, remove it from register layout. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index 3d920a834486..1c2c17880a40 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -94,8 +94,6 @@ enum qphy_reg_layout { QPHY_PCS_AUTONOMOUS_MODE_CTRL, QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, QPHY_PCS_POWER_DOWN_CONTROL, - /* PCS_MISC registers */ - QPHY_PCS_MISC_TYPEC_CTRL, /* Keep last to ensure regs_layout arrays are properly initialized */ QPHY_LAYOUT_SIZE }; @@ -136,7 +134,6 @@ static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8, [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc, [QPHY_PCS_STATUS] = 0x174, - [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00, }; static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { From patchwork Thu Nov 10 19:22:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 623919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F308C433FE for ; Thu, 10 Nov 2022 19:23:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230323AbiKJTXA (ORCPT ); Thu, 10 Nov 2022 14:23:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230403AbiKJTW6 (ORCPT ); Thu, 10 Nov 2022 14:22:58 -0500 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C1824385A for ; Thu, 10 Nov 2022 11:22:57 -0800 (PST) Received: by mail-lj1-x22c.google.com with SMTP id u2so2071963ljl.3 for ; Thu, 10 Nov 2022 11:22:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6VQsp9UBAbE2cRO3TEdvA806TXbC5gAFpniCLhjDPdc=; b=zOk9DmkIbQyOPdg3MYJAAXyh6OceWGK2JnfVoTaGvXFrDuzS4ZbSKeeR37A1idZCMn Nmf4vnsnZpYsdnPL2lvujfSSI6YZj4j32b7CkJIQ//FpPmVGzffNXnKmhyBRekzXUxVe Vs3pbVdpk34XozHp0VoqFj6oV1NpGOLShS6qmV6GjUsLRjqsGQ6DgTimZPbzGbWgg+Xy 4IgpAXxochXOwJbwoSDBv2OVKADp22lARTEK49Tgw9iv9CwnqJXxIxRHx9DEmDLKk1L/ akkPr0uTQ4WoyxNJ3su7tOXqOKGAJNsifohC3V45MwuxNoMKWjWCPNWxA81VUcxzfVax Rsow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6VQsp9UBAbE2cRO3TEdvA806TXbC5gAFpniCLhjDPdc=; b=LXzRSlDnLR1dJcpc4ILGbnqZ/SROpdyuX4ObPuRSmYrSAK1mT2F4qYZuZtr97k4W+W 06an/UdZ2W0bTWsfHjn0r35SjZAoltPGrIROOE8cm8BfGFCIKlqzB8JKDDNl5RcyZC3T 9xqUOyQODtV+QCLWQi1D9ZjjzPLCYG7Mr7vE9PJa85QEhxtuwKN7UUplnz4lwPY/N22v oNMhI45Ks+i4CMKpHyAbFpTWKxyFz1i0mtcBxRNQ4piJvQF05O9ZdT7GggGrr1E87NEK eE98BctqgEetudYGMCz1MryAC+5pYHedDi3QrLGfpyC8SMW/zK5bHZ75HZAtG+Da8JNO zYvg== X-Gm-Message-State: ACrzQf2ONVtJaKUhIs/eCerUxVBF0Aj6d9lKJHuvBQZgSouX6Og9BQzy pWjCqP8KgIYElGJ71MA4hyYaAQ== X-Google-Smtp-Source: AMsMyM5+xsImH5F3n8OY/nvttNljKSXIpZP4+Hx4iCb5aG7y9z9kJPxlXH0puqKk4zb+dtAfjvhjeA== X-Received: by 2002:a05:651c:516:b0:277:2428:3682 with SMTP id o22-20020a05651c051600b0027724283682mr9667491ljp.291.1668108176639; Thu, 10 Nov 2022 11:22:56 -0800 (PST) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id h8-20020a05651c124800b0027758f0619fsm40345ljh.132.2022.11.10.11.22.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Nov 2022 11:22:56 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v3 11/13] phy: qcom-qmp-usb: rework regs layout arrays Date: Thu, 10 Nov 2022 22:22:46 +0300 Message-Id: <20221110192248.873973-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> References: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use symbolic names for the values inside reg layout arrays. New register names are added following the PCS register layout that is used by the particular PHY. Note: ipq8074 tables appear to use a mixture of v2 and v3 registers. This might need additional fixes. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h | 3 ++ drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 52 +++++++++++----------- 2 files changed, 29 insertions(+), 26 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h index c7e8e2a28e6e..bf36399d0057 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h @@ -28,7 +28,10 @@ #define QPHY_V2_PCS_FLL_CNT_VAL_L 0x0c8 #define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL 0x0cc #define QPHY_V2_PCS_FLL_MAN_CODE 0x0d0 +#define QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL 0x0d4 +#define QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR 0x0d8 #define QPHY_V2_PCS_LFPS_RXTERM_IRQ_STATUS 0x178 +#define QPHY_V2_PCS_USB_PCS_STATUS 0x17c /* USB */ #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 #define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac #define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index 1c2c17880a40..aa6db5b679c0 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -98,42 +98,42 @@ enum qphy_reg_layout { QPHY_LAYOUT_SIZE }; -static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x08, - [QPHY_PCS_STATUS] = 0x17c, - [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4, - [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, +static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V2_PCS_USB_PCS_STATUS, + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL, + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL, }; static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x08, - [QPHY_PCS_STATUS] = 0x174, - [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, - [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, + [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, }; static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = 0x00, - [QPHY_START_CTRL] = 0x44, - [QPHY_PCS_STATUS] = 0x14, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, + [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, /* In PCS_USB */ - [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008, - [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014, + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, }; static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = 0x00, - [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, - [QPHY_START_CTRL] = 0x08, - [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8, - [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc, - [QPHY_PCS_STATUS] = 0x174, + [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, + [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, + [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, }; static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { @@ -1594,7 +1594,7 @@ static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = usb3phy_regs_layout, + .regs = qmp_v2_usb3phy_regs_layout, }; static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { From patchwork Thu Nov 10 19:22:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 623375 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7EDEC4332F for ; Thu, 10 Nov 2022 19:23:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230043AbiKJTXB (ORCPT ); Thu, 10 Nov 2022 14:23:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230224AbiKJTXA (ORCPT ); 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Thu, 10 Nov 2022 11:22:56 -0800 (PST) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I Cc: Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: [PATCH v3 12/13] phy: qcom-qmp-usb: fix regs layout arrays Date: Thu, 10 Nov 2022 22:22:47 +0300 Message-Id: <20221110192248.873973-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> References: <20221110192248.873973-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop qcm2290_usb3phy_regs_layout, it is a duplicate of qmp_v3_usb3phy_regs_layout. Introduce qmp_v5_usb3phy_regs_layout to be used for sm8350 and sc8280xp. Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index aa6db5b679c0..74c04cb497f8 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -127,13 +127,15 @@ static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, }; -static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { - [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, - [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, - [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, - [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, - [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, - [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, +static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, + + /* In PCS_USB */ + [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, + [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, }; static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { @@ -1662,7 +1664,7 @@ static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v4_usb3phy_regs_layout, + .regs = qmp_v5_usb3phy_regs_layout, }; static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { @@ -1878,7 +1880,7 @@ static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v4_usb3phy_regs_layout, + .regs = qmp_v5_usb3phy_regs_layout, .pcs_usb_offset = 0x300, .has_pwrdn_delay = true, @@ -1904,7 +1906,7 @@ static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qmp_v4_usb3phy_regs_layout, + .regs = qmp_v5_usb3phy_regs_layout, .pcs_usb_offset = 0x1000, .has_pwrdn_delay = true, @@ -1927,7 +1929,7 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = qcm2290_usb3phy_regs_layout, + .regs = qmp_v3_usb3phy_regs_layout, }; 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Signed-off-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 3 +++ drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 6 ++++++ drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 4 ++++ drivers/phy/qualcomm/phy-qcom-qmp-usb.c | 3 +++ drivers/phy/qualcomm/phy-qcom-qmp.h | 15 +-------------- 5 files changed, 17 insertions(+), 14 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c index 5e11b6a1d189..f6f6dcb8bc66 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c @@ -23,6 +23,9 @@ #include #include "phy-qcom-qmp.h" +#include "phy-qcom-qmp-pcs-misc-v3.h" +#include "phy-qcom-qmp-pcs-usb-v4.h" +#include "phy-qcom-qmp-pcs-usb-v5.h" /* QPHY_SW_RESET bit */ #define SW_RESET BIT(0) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 4bab804a2ed8..783b45486788 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -26,6 +26,12 @@ #include #include "phy-qcom-qmp.h" +#include "phy-qcom-qmp-pcs-misc-v3.h" +#include "phy-qcom-qmp-pcs-pcie-v4.h" +#include "phy-qcom-qmp-pcs-pcie-v4_20.h" +#include "phy-qcom-qmp-pcs-pcie-v5.h" +#include "phy-qcom-qmp-pcs-pcie-v5_20.h" +#include "phy-qcom-qmp-pcie-qhp.h" /* QPHY_SW_RESET bit */ #define SW_RESET BIT(0) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c index c9698e17b617..081ee526492a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c @@ -23,6 +23,10 @@ #include #include "phy-qcom-qmp.h" +#include "phy-qcom-qmp-pcs-ufs-v2.h" +#include "phy-qcom-qmp-pcs-ufs-v3.h" +#include "phy-qcom-qmp-pcs-ufs-v4.h" +#include "phy-qcom-qmp-pcs-ufs-v5.h" /* QPHY_SW_RESET bit */ #define SW_RESET BIT(0) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c index 74c04cb497f8..2d2136cb1723 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c @@ -23,6 +23,9 @@ #include #include "phy-qcom-qmp.h" +#include "phy-qcom-qmp-pcs-misc-v3.h" +#include "phy-qcom-qmp-pcs-usb-v4.h" +#include "phy-qcom-qmp-pcs-usb-v5.h" /* QPHY_SW_RESET bit */ #define SW_RESET BIT(0) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 60c52a55f119..fd99a5d02703 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -24,29 +24,16 @@ #include "phy-qcom-qmp-qserdes-pll.h" #include "phy-qcom-qmp-pcs-v2.h" -#include "phy-qcom-qmp-pcs-ufs-v2.h" #include "phy-qcom-qmp-pcs-v3.h" -#include "phy-qcom-qmp-pcs-misc-v3.h" -#include "phy-qcom-qmp-pcs-ufs-v3.h" #include "phy-qcom-qmp-pcs-v4.h" -#include "phy-qcom-qmp-pcs-pcie-v4.h" -#include "phy-qcom-qmp-pcs-usb-v4.h" -#include "phy-qcom-qmp-pcs-ufs-v4.h" #include "phy-qcom-qmp-pcs-v4_20.h" -#include "phy-qcom-qmp-pcs-pcie-v4_20.h" #include "phy-qcom-qmp-pcs-v5.h" -#include "phy-qcom-qmp-pcs-v5_20.h" -#include "phy-qcom-qmp-pcs-pcie-v5.h" -#include "phy-qcom-qmp-pcs-usb-v5.h" -#include "phy-qcom-qmp-pcs-ufs-v5.h" - -#include "phy-qcom-qmp-pcs-pcie-v5_20.h" -#include "phy-qcom-qmp-pcie-qhp.h" +#include "phy-qcom-qmp-pcs-v5_20.h" /* Only for QMP V3 & V4 PHY - DP COM registers */ #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00