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Mon, 7 Nov 2022 17:57:59 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT033.mail.protection.outlook.com (10.13.172.221) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5791.20 via Frontend Transport; Mon, 7 Nov 2022 17:57:59 +0000 Received: from pyuan-Cloudripper.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Mon, 7 Nov 2022 11:57:55 -0600 From: Perry Yuan To: , , CC: , , , , , , , , , Perry Yuan Subject: [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy performance preference cppc control Date: Tue, 8 Nov 2022 01:56:58 +0800 Message-ID: <20221107175705.2207842-2-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221107175705.2207842-1-Perry.Yuan@amd.com> References: <20221107175705.2207842-1-Perry.Yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT033:EE_|BL3PR12MB6379:EE_ X-MS-Office365-Filtering-Correlation-Id: 20428671-2beb-43cf-3d16-08dac0e99b5c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(346002)(396003)(376002)(136003)(39860400002)(451199015)(36840700001)(40470700004)(46966006)(36756003)(40480700001)(86362001)(16526019)(81166007)(41300700001)(356005)(110136005)(316002)(8676002)(8936002)(4326008)(70586007)(54906003)(70206006)(36860700001)(5660300002)(40460700003)(82740400003)(478600001)(186003)(336012)(1076003)(83380400001)(7696005)(26005)(82310400005)(2616005)(426003)(47076005)(2906002)(36900700001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2022 17:57:59.1835 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 20428671-2beb-43cf-3d16-08dac0e99b5c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6379 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add the EPP(Energy Performance Preference) support for the AMD SoCs without the dedicated CPPC MSR, those SoCs need to add this cppc acpi functions to update EPP values and desired perf value. In order to get EPP worked, cppc_get_epp_caps() will query EPP preference value and cppc_set_epp_perf() will set EPP new value. Before the EPP works, pstate driver will use cppc_set_auto_epp() to enable EPP function from firmware firstly. Signed-off-by: Perry Yuan --- drivers/acpi/cppc_acpi.c | 126 +++++++++++++++++++++++++++++++++++++++ include/acpi/cppc_acpi.h | 17 ++++++ 2 files changed, 143 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 093675b1a1ff..d9c38dee1f48 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1365,6 +1365,132 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) } EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); +/** + * cppc_get_epp_caps - Get the energy preference register value. + * @cpunum: CPU from which to get epp preference level. + * @perf_caps: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); + struct cpc_register_resource *energy_perf_reg; + u64 energy_perf; + + if (!cpc_desc) { + pr_warn("No CPC descriptor for CPU:%d\n", cpunum); + return -ENODEV; + } + + energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; + + if (!CPC_SUPPORTED(energy_perf_reg)) + pr_warn("energy perf reg update is unsupported!\n"); + + if (CPC_IN_PCC(energy_perf_reg)) { + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = 0; + + if (pcc_ss_id < 0) + return -ENODEV; + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + + if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) { + cpc_read(cpunum, energy_perf_reg, &energy_perf); + perf_caps->energy_perf = energy_perf; + } else { + ret = -EIO; + } + + up_write(&pcc_ss_data->pcc_lock); + + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cppc_get_epp_caps); + +int cppc_set_auto_epp(int cpu, bool enable) +{ + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cpc_register_resource *auto_sel_reg; + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = -EINVAL; + + if (!cpc_desc) { + pr_warn("No CPC descriptor for CPU:%d\n", cpu); + return -EINVAL; + } + + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; + + if (CPC_IN_PCC(auto_sel_reg)) { + if (pcc_ss_id < 0) + return -ENODEV; + + ret = cpc_write(cpu, auto_sel_reg, enable); + if (ret) + return ret; + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + /* after writing CPC, transfer the ownership of PCC to platform */ + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); + up_write(&pcc_ss_data->pcc_lock); + return ret; + } + + return cpc_write(cpu, auto_sel_reg, enable); +} +EXPORT_SYMBOL_GPL(cppc_set_auto_epp); + +/* + * Set Energy Performance Preference Register value through + * Performance Controls Interface + */ +int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cpc_register_resource *epp_set_reg; + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = -EINVAL; + + if (!cpc_desc) { + pr_warn("No CPC descriptor for CPU:%d\n", cpu); + return -EINVAL; + } + + epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; + + if (CPC_IN_PCC(epp_set_reg)) { + if (pcc_ss_id < 0) + return -ENODEV; + + ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf); + if (ret) + return ret; + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + /* after writing CPC, transfer the ownership of PCC to platform */ + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); + up_write(&pcc_ss_data->pcc_lock); + } + + return ret; +} +EXPORT_SYMBOL_GPL(cppc_set_epp_perf); + /** * cppc_set_enable - Set to enable CPPC on the processor by writing the * Continuous Performance Control package EnableRegister field. diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index c5614444031f..10d91aeedaca 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -108,12 +108,14 @@ struct cppc_perf_caps { u32 lowest_nonlinear_perf; u32 lowest_freq; u32 nominal_freq; + u32 energy_perf; }; struct cppc_perf_ctrls { u32 max_perf; u32 min_perf; u32 desired_perf; + u32 energy_perf; }; struct cppc_perf_fb_ctrs { @@ -149,6 +151,9 @@ extern bool cpc_ffh_supported(void); extern bool cpc_supported_by_cpu(void); extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val); extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val); +extern int cppc_set_auto_epp(int cpu, bool enable); +extern int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps); +extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); #else /* !CONFIG_ACPI_CPPC_LIB */ static inline int cppc_get_desired_perf(int cpunum, u64 *desired_perf) { @@ -202,6 +207,18 @@ static inline int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) { return -ENOTSUPP; } +static inline int cppc_set_auto_epp(int cpu, bool enable) +{ + return -ENOTSUPP; +} +static inline int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + return -ENOTSUPP; +} +static inline int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps) +{ + return -ENOTSUPP; +} #endif /* !CONFIG_ACPI_CPPC_LIB */ #endif /* _CPPC_ACPI_H*/ From patchwork Mon Nov 7 17:56:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 622555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 703F0C43217 for ; Mon, 7 Nov 2022 18:02:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232741AbiKGSCj (ORCPT ); Mon, 7 Nov 2022 13:02:39 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40080 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233202AbiKGSCJ (ORCPT ); Mon, 7 Nov 2022 13:02:09 -0500 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2042.outbound.protection.outlook.com [40.107.94.42]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CAE2212AED; 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Mon, 7 Nov 2022 17:58:31 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT110.mail.protection.outlook.com (10.13.173.205) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5791.20 via Frontend Transport; Mon, 7 Nov 2022 17:58:31 +0000 Received: from pyuan-Cloudripper.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Mon, 7 Nov 2022 11:57:58 -0600 From: Perry Yuan To: , , CC: , , , , , , , , , Perry Yuan Subject: [PATCH v3 2/8] Documentation: amd-pstate: add EPP profiles introduction Date: Tue, 8 Nov 2022 01:56:59 +0800 Message-ID: <20221107175705.2207842-3-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221107175705.2207842-1-Perry.Yuan@amd.com> References: <20221107175705.2207842-1-Perry.Yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT110:EE_|PH0PR12MB5481:EE_ X-MS-Office365-Filtering-Correlation-Id: cc1dbd9e-c792-4ed5-27e4-08dac0e9ae92 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(39860400002)(136003)(376002)(346002)(396003)(451199015)(40470700004)(36840700001)(46966006)(36860700001)(7696005)(54906003)(110136005)(316002)(40480700001)(5660300002)(47076005)(2616005)(2906002)(426003)(40460700003)(8936002)(336012)(16526019)(186003)(1076003)(26005)(86362001)(70586007)(36756003)(70206006)(8676002)(4326008)(41300700001)(83380400001)(356005)(81166007)(82740400003)(82310400005)(478600001)(36900700001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2022 17:58:31.4447 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cc1dbd9e-c792-4ed5-27e4-08dac0e9ae92 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT110.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5481 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The patch add AMD pstate EPP feature introduction and what EPP preference supported for AMD processors. User can get supported list from energy_performance_available_preferences attribute file, or update current profile to energy_performance_preference file 1) See all EPP profiles $ sudo cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_available_preferences default performance balance_performance balance_power power 2) Check current EPP profile $ sudo cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference performance 3) Set new EPP profile $ sudo bash -c "echo power > /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference" Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 8f3d30c5a0d8..78c6525d5a49 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -262,6 +262,25 @@ lowest non-linear performance in `AMD CPPC Performance Capability `_.) This attribute is read-only. +``energy_performance_available_preferences`` + +All the supported EPP preference could be selected, List of the strings that +can be set to the ``energy_performance_preference`` attribute +those different profiles represent different energy vs efficiency hints provided +to low-level firmware +however, the ``default`` represents the epp value is set by platform firmware +This attribute is read-only. + +``energy_performance_preference`` + +The current energy performance preference can be read from this attribute. +and user can change current preference according to energy or performance needs +Please get all support profiles list from +``energy_performance_available_preferences`` attribute, all the profiles are +integer values defined between 0 to 255 when EPP feature is enabled by platform +firmware, if EPP feature is disabled, driver will ignore the written value +This attribute is read-write. + Other performance and frequency values can be read back from ``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`. 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Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 89 ++++++++++++++++++++++++++++++++++++ include/linux/amd-pstate.h | 1 + 2 files changed, 90 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index eb82bc6a7f66..6ce9fca0a128 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1195,6 +1195,93 @@ static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) return 0; } +static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) +{ + struct cppc_perf_ctrls perf_ctrls; + u64 value, max_perf; + int ret; + + ret = amd_pstate_enable(true); + if (ret) + pr_err("failed to enable amd pstate during resume, return %d\n", ret); + + value = READ_ONCE(cpudata->cppc_req_cached); + max_perf = READ_ONCE(cpudata->highest_perf); + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + } else { + perf_ctrls.max_perf = max_perf; + perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached); + cppc_set_perf(cpudata->cpu, &perf_ctrls); + } +} + +static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + + pr_debug("AMD CPU Core %d going online\n", cpudata->cpu); + + if (cppc_active) { + amd_pstate_epp_reenable(cpudata); + cpudata->suspended = false; + } + + return 0; +} + +static void amd_pstate_epp_offline(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + struct cppc_perf_ctrls perf_ctrls; + int min_perf; + u64 value; + + min_perf = READ_ONCE(cpudata->lowest_perf); + value = READ_ONCE(cpudata->cppc_req_cached); + + mutex_lock(&amd_pstate_limits_lock); + if (boot_cpu_has(X86_FEATURE_CPPC)) { + cpudata->epp_policy = CPUFREQ_POLICY_UNKNOWN; + + /* Set max perf same as min perf */ + value &= ~AMD_CPPC_MAX_PERF(~0L); + value |= AMD_CPPC_MAX_PERF(min_perf); + value &= ~AMD_CPPC_MIN_PERF(~0L); + value |= AMD_CPPC_MIN_PERF(min_perf); + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + } else { + perf_ctrls.desired_perf = 0; + perf_ctrls.max_perf = min_perf; + perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(AMD_CPPC_EPP_POWERSAVE); + cppc_set_perf(cpudata->cpu, &perf_ctrls); + } + mutex_unlock(&amd_pstate_limits_lock); +} + +static int amd_pstate_cpu_offline(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + + pr_debug("AMD CPU Core %d going offline\n", cpudata->cpu); + + if (cpudata->suspended) + return 0; + + if (cppc_active) + amd_pstate_epp_offline(policy); + + return 0; +} + +static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy) +{ + amd_pstate_clear_update_util_hook(policy->cpu); + + return amd_pstate_cpu_offline(policy); +} + static void amd_pstate_verify_cpu_policy(struct amd_cpudata *cpudata, struct cpufreq_policy_data *policy) { @@ -1229,6 +1316,8 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .init = amd_pstate_epp_cpu_init, .exit = amd_pstate_epp_cpu_exit, .update_limits = amd_pstate_epp_update_limits, + .offline = amd_pstate_epp_cpu_offline, + .online = amd_pstate_epp_cpu_online, .name = "amd_pstate_epp", .attr = amd_pstate_epp_attr, }; diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 7e6e8cab97b3..c0ad7eedcae3 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -99,6 +99,7 @@ struct amd_cpudata { u64 cppc_cap1_cached; struct update_util_data update_util; struct amd_aperf_mperf sample; + bool suspended; }; /** From patchwork Mon Nov 7 17:57:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 622553 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2775C43219 for ; Mon, 7 Nov 2022 18:03:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232877AbiKGSDZ (ORCPT ); Mon, 7 Nov 2022 13:03:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233276AbiKGSCR (ORCPT ); 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Mon, 7 Nov 2022 11:58:42 -0600 From: Perry Yuan To: , , CC: , , , , , , , , , Perry Yuan Subject: [PATCH v3 7/8] cpufreq: amd-pstate: add frequency dynamic boost sysfs control Date: Tue, 8 Nov 2022 01:57:04 +0800 Message-ID: <20221107175705.2207842-8-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221107175705.2207842-1-Perry.Yuan@amd.com> References: <20221107175705.2207842-1-Perry.Yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT037:EE_|PH7PR12MB6907:EE_ X-MS-Office365-Filtering-Correlation-Id: 1c598324-b526-45a6-b465-08dac0e9bed3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: g+nC3y0X7czgDXKJl+5yZHSPbvxcp5Pj5c7WEoYpIkkQL70XqUUJfo04sr7cZ31zNcnw6af5recbdpEaV0SUsVvCbDJNcFgVfhy+zptaWH9v4DeIMe7R37DFnr+XvWUtpE0T34IwFIo2lwRGSggjU5YAFVphO5pXIzUciPxab2VI3H0nHIedWzAVyGB87TPWYYMuflSTombL7mjpoJ9r6kAYcWOkg9ixyta/0HF1gUBD3/okL0/Ahmyq/tyTwzsTUZIfoqMcdrOKNsRD0GdD1WLYzmo+HVDiq8q8nk926F7QXq1Pk0Uuao7LYeFioOgJQ1X1sdv4DUtXgQz+3oVuY9d2VI33cWx9ufdczBDPwJeSV53iHPELn299juxQRAygkrp3hMxy3MDRXtjwkVuwEhz955Oq7fQN3HtD0qDnMoYSqoczVNdPtenlX6ywJ4IfoxG58nQvhozFQIHGpBAbDd0Xabxs2wSURMdXuwN9Pg3NMb/nBCdCD2DtLfoCI4360NL1hezC9NJ5RQO9FSrBRzpw+/lof1a96PpS/3b27C+SDWTfxDydv34DrePGyf8LWz6MqZLsQkQ/PYjreCVJARdaKKN50AQRilXG2KxV4Pp523Y+wH4RpGOG2BoJwxPv+I4kOB/qg0UbWPE/PmTrQpX3eEgc1L2aSuR0kicZMgQTjJW1sPxI3joeS+UtHxMhrvCH/8WAv+NJEXgskI2KlcBsad2fpVHUw3K5gYBhNpMb78OAkohwyVTHI/SxksAcZAzPTf66EAy3EfDzlpT+ZXyAEPir2O4MZ+iaKSJGIjFJhwRTqcqhRhHiFNP4HZwbrKVv/Hipd8eilMfI+1wjY71cizh87EnLtUG8a8qeVcA= X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 53 ++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 841b1e2383b8..6958c5fd9e1c 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -786,12 +786,46 @@ static ssize_t show_energy_performance_preference( return sprintf(buf, "%s\n", energy_perf_strings[preference]); } +static void amd_pstate_update_policies(void) +{ + int cpu; + + for_each_possible_cpu(cpu) + cpufreq_update_policy(cpu); +} + +static ssize_t show_pstate_dynamic_boost(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%u\n", cppc_boost); +} + +static ssize_t store_pstate_dynamic_boost(struct kobject *a, + struct kobj_attribute *b, + const char *buf, size_t count) +{ + unsigned int input; + int ret; + + ret = kstrtouint(buf, 10, &input); + if (ret) + return ret; + + mutex_lock(&amd_pstate_driver_lock); + cppc_boost = !!input; + amd_pstate_update_policies(); + mutex_unlock(&amd_pstate_driver_lock); + + return count; +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); cpufreq_freq_attr_ro(amd_pstate_highest_perf); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); +define_one_global_rw(pstate_dynamic_boost); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -809,6 +843,15 @@ static struct freq_attr *amd_pstate_epp_attr[] = { NULL, }; +static struct attribute *pstate_global_attributes[] = { + &pstate_dynamic_boost.attr, + NULL +}; + +static const struct attribute_group amd_pstate_global_attr_group = { + .attrs = pstate_global_attributes, +}; + static inline void update_boost_state(void) { u64 misc_en; @@ -1416,6 +1459,16 @@ static int __init amd_pstate_init(void) pr_err("failed to register amd pstate driver with return %d\n", ret); + amd_pstate_kobj = kobject_create_and_add("amd-pstate", &cpu_subsys.dev_root->kobj); + if (!amd_pstate_kobj) + pr_err("amd-pstate: Global sysfs registration failed.\n"); + + ret = sysfs_create_group(amd_pstate_kobj, &amd_pstate_global_attr_group); + if (ret) { + pr_err("amd-pstate: Sysfs attribute export failed with error %d.\n", + ret); + } + return ret; } device_initcall(amd_pstate_init);