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Signed-off-by: Dipen Patel Acked-by: Thierry Reding Acked-by: Thierry Reding --- MAINTAINERS | 3 +++ 1 file changed, 3 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index cf0f18502372..37b17c1f1388 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9414,6 +9414,9 @@ F: drivers/input/touchscreen/htcpen.c HTE SUBSYSTEM M: Dipen Patel +L: timestamp@lists.linux.dev +T: git git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux.git +Q: https://patchwork.kernel.org/project/timestamp/list/ S: Maintained F: Documentation/devicetree/bindings/timestamp/ F: Documentation/driver-api/hte/ From patchwork Thu Nov 3 17:45:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 621178 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9C79C4167B for ; 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Thu, 3 Nov 2022 10:45:35 -0700 From: Dipen Patel To: , , , , , , , , CC: Dipen Patel Subject: [PATCH 2/7] hte: Add Tegra234 provider Date: Thu, 3 Nov 2022 10:45:18 -0700 Message-ID: <20221103174523.29592-3-dipenp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221103174523.29592-1-dipenp@nvidia.com> References: <20221103174523.29592-1-dipenp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT058:EE_|DM4PR12MB5357:EE_ X-MS-Office365-Filtering-Correlation-Id: ff83a33d-fd21-4fab-4880-08dabdc33c18 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: pA4utFYPXiP4DCRGt8R8WlRQ/fhlBQCqG72iOIf1u3pv6ypgF7IAM12TGb79xMPo3201x3YEFIx5Tr8NxrGEYCIE8p9ei0e8z44D7UZs8PM0LSmpZexpgPuRxRGKkZjz5I6KltgFWS3jm8adkaStseuBS4Bsrmu2vx+eFfl54U1uemPh/G5mupU3ZLrpppz8+r+l/igAaFAuZolJEwToWaNglB39StBYrffete1fEMYjNh4qsOkKIycQuyrBNzHhHauLEoieqKkRDHMx07HFTDjUgR9IU6Asm0bB43iYLrMHoaunYF+8s7ELsfCcGby83O9gtpoqzaGWIh66cCX/RXUwgDwr7nqAuQvf8cQefp8QyHRk/KXthOG387/s0PaB8uhNug0MdmRwSqe7SXpWoTzCyEIDh3RtBW7n8vhOtDfsP11lMdcHVk4C29CJcASJee/ANCexG1i6rAYWTLaIGiRgxKABUT5CY3aD8YPEgyLnZfPeSoMazpytOJXztOEzaRByFd7eqLMrw8ThsTn7olRy1u+WfVQ1umGUxyfhUOG4QDZZQHCSS1Xcl6Vx7KmnuufguNECWl5nqpMA1Y9lLXmJ14NucV/XFaDgDylmqUYsResnRu29DzoEk5H2BsrVsdLlrYYgPa6hakqZ2gM692J+sGubm88e7KouQloY9uChgseZ82c15kw1j4xIM/a02+/S8um8lOZeSsZuSZMv+GakeaW7gBkJ/S7zkigM0zExodWuDbhpIpfR4d95cOODN/6HHA/Q/mPWAYIOWAPO+6IJjGfAH0IZv3edotN1lwI= X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(39860400002)(376002)(396003)(136003)(346002)(451199015)(36840700001)(40470700004)(46966006)(186003)(336012)(1076003)(2616005)(107886003)(7696005)(26005)(36860700001)(83380400001)(6666004)(426003)(47076005)(2906002)(40480700001)(40460700003)(82310400005)(110136005)(5660300002)(478600001)(41300700001)(70206006)(8936002)(8676002)(70586007)(4326008)(316002)(36756003)(7636003)(356005)(86362001)(82740400003)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2022 17:45:44.9905 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff83a33d-fd21-4fab-4880-08dabdc33c18 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT058.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5357 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The Tegra234 AON GPIO instance and LIC IRQ support HTE. For the GPIO HTE support, it requires to add mapping between GPIO and HTE framework. Signed-off-by: Dipen Patel --- drivers/hte/hte-tegra194-test.c | 2 +- drivers/hte/hte-tegra194.c | 124 ++++++++++++++++++++++++++++++-- 2 files changed, 121 insertions(+), 5 deletions(-) diff --git a/drivers/hte/hte-tegra194-test.c b/drivers/hte/hte-tegra194-test.c index 5d776a185bd6..d79c28a80517 100644 --- a/drivers/hte/hte-tegra194-test.c +++ b/drivers/hte/hte-tegra194-test.c @@ -16,7 +16,7 @@ #include /* - * This sample HTE GPIO test driver demonstrates HTE API usage by enabling + * This sample HTE test driver demonstrates HTE API usage by enabling * hardware timestamp on gpio_in and specified LIC IRQ lines. * * Note: gpio_out and gpio_in need to be shorted externally in order for this diff --git a/drivers/hte/hte-tegra194.c b/drivers/hte/hte-tegra194.c index 49a27af22742..5d1f947db0f6 100644 --- a/drivers/hte/hte-tegra194.c +++ b/drivers/hte/hte-tegra194.c @@ -62,6 +62,10 @@ #define NV_AON_HTE_SLICE2_IRQ_GPIO_25 25 #define NV_AON_HTE_SLICE2_IRQ_GPIO_26 26 #define NV_AON_HTE_SLICE2_IRQ_GPIO_27 27 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_28 28 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_29 29 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_30 30 +#define NV_AON_HTE_SLICE2_IRQ_GPIO_31 31 #define HTE_TECTRL 0x0 #define HTE_TETSCH 0x4 @@ -220,7 +224,100 @@ static const struct tegra_hte_line_mapped tegra194_aon_gpio_sec_map[] = { [39] = {NV_AON_SLICE_INVALID, 0}, }; -static const struct tegra_hte_data aon_hte = { +static const struct tegra_hte_line_mapped tegra234_aon_gpio_map[] = { + /* gpio, slice, bit_index */ + /* AA port */ + [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, + [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, + [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, + [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, + [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, + [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, + [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, + [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, + /* BB port */ + [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, + [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, + [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, + [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, + /* CC port */ + [12] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, + [13] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, + [14] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, + [15] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, + [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, + [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, + [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, + [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, + /* DD port */ + [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, + [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, + [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, + /* EE port */ + [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, + [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, + [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, + [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, + [27] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, + [28] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, + [29] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, + [30] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, + /* GG port */ + [31] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, +}; + +static const struct tegra_hte_line_mapped tegra234_aon_gpio_sec_map[] = { + /* gpio, slice, bit_index */ + /* AA port */ + [0] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_11}, + [1] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_10}, + [2] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_9}, + [3] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_8}, + [4] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_7}, + [5] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_6}, + [6] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_5}, + [7] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_4}, + /* BB port */ + [8] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_3}, + [9] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_2}, + [10] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_1}, + [11] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_0}, + [12] = {NV_AON_SLICE_INVALID, 0}, + [13] = {NV_AON_SLICE_INVALID, 0}, + [14] = {NV_AON_SLICE_INVALID, 0}, + [15] = {NV_AON_SLICE_INVALID, 0}, + /* CC port */ + [16] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_22}, + [17] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_21}, + [18] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_20}, + [19] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_19}, + [20] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_18}, + [21] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_17}, + [22] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_16}, + [23] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_15}, + /* DD port */ + [24] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_14}, + [25] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_13}, + [26] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_12}, + [27] = {NV_AON_SLICE_INVALID, 0}, + [28] = {NV_AON_SLICE_INVALID, 0}, + [29] = {NV_AON_SLICE_INVALID, 0}, + [30] = {NV_AON_SLICE_INVALID, 0}, + [31] = {NV_AON_SLICE_INVALID, 0}, + /* EE port */ + [32] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_31}, + [33] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_30}, + [34] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_29}, + [35] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_28}, + [36] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_27}, + [37] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_26}, + [38] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_25}, + [39] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_24}, + /* GG port */ + [40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23}, +}; + +static const struct tegra_hte_data t194_aon_hte = { .map_sz = ARRAY_SIZE(tegra194_aon_gpio_map), .map = tegra194_aon_gpio_map, .sec_map_sz = ARRAY_SIZE(tegra194_aon_gpio_sec_map), @@ -228,6 +325,14 @@ static const struct tegra_hte_data aon_hte = { .type = HTE_TEGRA_TYPE_GPIO, }; +static const struct tegra_hte_data t234_aon_hte = { + .map_sz = ARRAY_SIZE(tegra234_aon_gpio_map), + .map = tegra234_aon_gpio_map, + .sec_map_sz = ARRAY_SIZE(tegra234_aon_gpio_sec_map), + .sec_map = tegra234_aon_gpio_sec_map, + .type = HTE_TEGRA_TYPE_GPIO, +}; + static const struct tegra_hte_data lic_hte = { .map_sz = 0, .map = NULL, @@ -535,7 +640,9 @@ static bool tegra_hte_match_from_linedata(const struct hte_chip *chip, static const struct of_device_id tegra_hte_of_match[] = { { .compatible = "nvidia,tegra194-gte-lic", .data = &lic_hte}, - { .compatible = "nvidia,tegra194-gte-aon", .data = &aon_hte}, + { .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte}, + { .compatible = "nvidia,tegra234-gte-lic", .data = &lic_hte}, + { .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte}, { } }; MODULE_DEVICE_TABLE(of, tegra_hte_of_match); @@ -635,8 +742,17 @@ static int tegra_hte_probe(struct platform_device *pdev) gc->match_from_linedata = tegra_hte_match_from_linedata; - hte_dev->c = gpiochip_find("tegra194-gpio-aon", - tegra_get_gpiochip_from_name); + if (of_device_is_compatible(dev->of_node, + "nvidia,tegra194-gte-aon")) + hte_dev->c = gpiochip_find("tegra194-gpio-aon", + tegra_get_gpiochip_from_name); + else if (of_device_is_compatible(dev->of_node, + "nvidia,tegra234-gte-aon")) + hte_dev->c = gpiochip_find("tegra234-gpio-aon", + tegra_get_gpiochip_from_name); + else + return -ENODEV; + if (!hte_dev->c) return dev_err_probe(dev, -EPROBE_DEFER, "wait for gpio controller\n"); From patchwork Thu Nov 3 17:45:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 621548 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B122C352A1 for ; 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Thu, 3 Nov 2022 10:45:35 -0700 From: Dipen Patel To: , , , , , , , , CC: Dipen Patel Subject: [PATCH 3/7] gpio: tegra186: Add Tegra234 hte support Date: Thu, 3 Nov 2022 10:45:19 -0700 Message-ID: <20221103174523.29592-4-dipenp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221103174523.29592-1-dipenp@nvidia.com> References: <20221103174523.29592-1-dipenp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT033:EE_|MW4PR12MB7285:EE_ X-MS-Office365-Filtering-Correlation-Id: 711f4adc-dffa-47c4-210a-08dabdc33fd0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Bih/pXl+24HmxWG3ZCyPgj2wMM49bjdQIMRhuinuNdENKzT/Ns6goH51oXGOzOJhn+CB1zbCEqOJG0OXD/owjI1VPaDY/C7iBOUuSJfBDZhB1hocd9szKwcBTxtnEEufL9j39Dyl3UetABTBaQv1rkJoqqP5QcG7oXimcP7q8t5oB2HLDKfVtDvlCROCwssDVHu7BXwOWLLURoxuQ5SmdkORry5JeWjTnktLG/vf3xr3jxjTmoAZnw+ctnPTH2+0pMNgRG07d8JHewm2bVMBSjNMs0uabyRruE6onthV60ewyXfZqjitg50tqKJi3cysXGjlIHmqzDeN0hOYB1gAX6s9Q72hDtizmm/4IKZdDqcnRNWWG6h8BeGYWsBj2i6PKyc6HoMRa2p1ZzkA4rx6O30e/1rWhe6vi/U7dhP41w3L2qOK5OTqZQibtKPGG56fxa4Vs+pWcaVLMyGt1g+Ys+oQiF5ivC/nLZgBeb7UPLUYSd6Vathlpb/6cWMT6EP2D+0o6Gxqfac9VXKquqytFsQVmgrgISjB4uftPyYGoY63Rl1y67gLimi6/cn9pRlmwTiTYGwvHQ7Q9U/Fcn8wg15LLel/iABH7pxgcehW7SLdJ/XXIROhzCc0wOSVPZtWwASeJeKwEG9eceANriaNX+PnB9KT0l2J6OQkLLewrbXNR5kYYSET0i412dzR6LcLulAp2EBqpqRnCZ77zddYhb0pHUToVylqq28od3riEUAt3y7qxO4mLfEei7ieZF+yZMpj6n/WQIX28yuUUXxfHSHbzVht6SZHqz5wrxcZ8jE= X-Forefront-Antispam-Report: CIP:216.228.118.232; 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Signed-off-by: Dipen Patel Acked-by: Thierry Reding --- drivers/gpio/gpio-tegra186.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index 54d9fa7da9c1..c2ccfee52608 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -1136,6 +1136,7 @@ static const struct tegra_gpio_soc tegra234_aon_soc = { .name = "tegra234-gpio-aon", .instance = 1, .num_irqs_per_bank = 8, + .has_gte = true, }; #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ From patchwork Thu Nov 3 17:45:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 621176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A97BEC3A5A1 for ; Thu, 3 Nov 2022 17:46:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230421AbiKCRqS (ORCPT ); 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Signed-off-by: Dipen Patel --- .../timestamp/nvidia,tegra194-hte.yaml | 44 +++++++++++++++++-- 1 file changed, 40 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml index c31e207d1652..158dbe58c49f 100644 --- a/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml +++ b/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Tegra194 on chip generic hardware timestamping engine (HTE) +title: Tegra on chip generic hardware timestamping engine (HTE) provider maintainers: - Dipen Patel @@ -23,6 +23,8 @@ properties: enum: - nvidia,tegra194-gte-aon - nvidia,tegra194-gte-lic + - nvidia,tegra234-gte-aon + - nvidia,tegra234-gte-lic reg: maxItems: 1 @@ -43,9 +45,8 @@ properties: description: HTE lines are arranged in 32 bit slice where each bit represents different line/signal that it can enable/configure for the timestamp. It is u32 - property and depends on the HTE instance in the chip. The value 3 is for - GPIO GTE and 11 for IRQ GTE. - enum: [3, 11] + property and the value depends on the HTE instance in the chip. + enum: [3, 11, 17] '#timestamp-cells': description: @@ -55,6 +56,41 @@ properties: mentioned in the nvidia GPIO device tree binding document. const: 1 +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-gte-aon + - nvidia,tegra234-gte-aon + then: + properties: + nvidia,slices: + const: 3 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra194-gte-lic + then: + properties: + nvidia,slices: + const: 11 + + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra234-gte-lic + then: + properties: + nvidia,slices: + const: 17 + required: - compatible - reg From patchwork Thu Nov 3 17:45:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 621549 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BE87C41535 for ; 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Thu, 3 Nov 2022 10:45:36 -0700 From: Dipen Patel To: , , , , , , , , CC: Dipen Patel Subject: [PATCH 5/7] hte: Re-phrase tegra API document Date: Thu, 3 Nov 2022 10:45:21 -0700 Message-ID: <20221103174523.29592-6-dipenp@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221103174523.29592-1-dipenp@nvidia.com> References: <20221103174523.29592-1-dipenp@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT058:EE_|PH0PR12MB5403:EE_ X-MS-Office365-Filtering-Correlation-Id: 10f4b3c2-dd7c-4f5c-a0a1-08dabdc33cb5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: PxJeRt6HJWwkdNgg/bXp5d1hOoTq51BBGDfRFdNm5uwxCgckgWsjpwJn6hqW6UxVEfCnHFju0sR16PjFWIt2S+P+MSKNHxCBTlto3ZFmU+TBoJqTgSHmvlGTCTjSzbDVhAGFXgI/U+S44bm3G9OeeOT4pyF2m+SKGwJOMooKlhDz+XF8HIYMa7X+ZpRfc/VxbaEMZIZhZKCz1OOqC/XjwOPpA19Ci6LB/+zzJ3PSja9Vcqlh64+bn8owAiKaO5/wNTIk+qxC6vxg3L3hVs4+epRCZM7BEaxk3pHx92HhUrGzepEY88ynIui7xBf8A8uBt5Az/cGE1CNAeVO6tAZ1A99l7TznttXvdiQOZP9JgTLD+RsfwLBhiVihPIQ+lfb2bssyLJucz+mjtgT31Aj7I7Co8kkvg34Y0MqekErjxWqYXOJsnZLT9ULp9alXFWAEMiDkcsfcMeiKvCAIxTORO8PUzh2Htxiw7RTK8DR9i2ZV371p1FLc9S7qgbrfTUrjmeVd6iUETlFqkN+d9OcpCGuIk3u3XkBqR0/bEEhY9kgbAxhFr6mFQ730HFnPPxsg85b6UH8fzSlJJJKN1H4xURCM4mQZN17xhhNpjTA+9kfWeL2PYnfd8sJsCbeC51UWCcE1yBhd51Wy4r7dUD46yGF3FvrKK4ISuTp9wpVOkksZOAMwB/BSCt1pBfiEuD8N23gIOSduYbejYo9/HPHLAloyTJsIEvJSq+wxHkbEKbdrrsjaoTKpi0AH4EkMcobciWHCA6sy5Bb5uKwYO2zxEbLmCdRW4yjWgxwEaL0PuNQ= X-Forefront-Antispam-Report: CIP:216.228.118.233; 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Signed-off-by: Dipen Patel --- Documentation/driver-api/hte/tegra194-hte.rst | 33 +++++++++---------- 1 file changed, 16 insertions(+), 17 deletions(-) diff --git a/Documentation/driver-api/hte/tegra194-hte.rst b/Documentation/driver-api/hte/tegra194-hte.rst index f2d617265546..85e654772782 100644 --- a/Documentation/driver-api/hte/tegra194-hte.rst +++ b/Documentation/driver-api/hte/tegra194-hte.rst @@ -5,25 +5,25 @@ HTE Kernel provider driver Description ----------- -The Nvidia tegra194 HTE provider driver implements two GTE -(Generic Timestamping Engine) instances: 1) GPIO GTE and 2) LIC -(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the -timestamp from the system counter TSC which has 31.25MHz clock rate, and the -driver converts clock tick rate to nanoseconds before storing it as timestamp -value. +The Nvidia tegra HTE provider also known as GTE (Generic Timestamping Engine) +driver implements two GTE instances: 1) GPIO GTE and 2) LIC +(Legacy Interrupt Controller) IRQ GTE. Both GTE instances get the timestamp +from the system counter TSC which has 31.25MHz clock rate, and the driver +converts clock tick rate to nanoseconds before storing it as timestamp value. GPIO GTE -------- This GTE instance timestamps GPIO in real time. For that to happen GPIO -needs to be configured as input. The always on (AON) GPIO controller instance -supports timestamping GPIOs in real time and it has 39 GPIO lines. The GPIO GTE -and AON GPIO controller are tightly coupled as it requires very specific bits -to be set in GPIO config register before GPIO GTE can be used, for that GPIOLIB -adds two optional APIs as below. The GPIO GTE code supports both kernel -and userspace consumers. The kernel space consumers can directly talk to HTE -subsystem while userspace consumers timestamp requests go through GPIOLIB CDEV -framework to HTE subsystem. +needs to be configured as input. Only the always on (AON) GPIO controller +instance supports timestamping GPIOs in real time as it is tightly coupled with +the GPIO GTE. To support this, GPIOLIB adds two optional APIs as mentioned +below. The GPIO GTE code supports both kernel and userspace consumers. The +kernel space consumers can directly talk to HTE subsystem while userspace +consumers timestamp requests go through GPIOLIB CDEV framework to HTE +subsystem. The hte devicetree binding described at +``Documentation/devicetree/bindings/timestamp`` provides an example of how a +consumer can request an GPIO line. See gpiod_enable_hw_timestamp_ns() and gpiod_disable_hw_timestamp_ns(). @@ -34,9 +34,8 @@ returns the timestamp in nanoseconds. LIC (Legacy Interrupt Controller) IRQ GTE ----------------------------------------- -This GTE instance timestamps LIC IRQ lines in real time. There are 352 IRQ -lines which this instance can add timestamps to in real time. The hte -devicetree binding described at ``Documentation/devicetree/bindings/timestamp`` +This GTE instance timestamps LIC IRQ lines in real time. The hte devicetree +binding described at ``Documentation/devicetree/bindings/timestamp`` provides an example of how a consumer can request an IRQ line. Since it is a one-to-one mapping with IRQ GTE provider, consumers can simply specify the IRQ number that they are interested in. There is no userspace consumer support for From patchwork Thu Nov 3 17:45:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 621175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7D2BC3A5A3 for ; Thu, 3 Nov 2022 17:46:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231792AbiKCRqQ (ORCPT ); Thu, 3 Nov 2022 13:46:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231616AbiKCRp4 (ORCPT ); Thu, 3 Nov 2022 13:45:56 -0400 Received: from NAM04-DM6-obe.outbound.protection.outlook.com (mail-dm6nam04on2041.outbound.protection.outlook.com [40.107.102.41]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F05F1AF22; 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Signed-off-by: Dipen Patel --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 20 ++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 20 ++++++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 41f3a7e188d0..67927d97956e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1366,6 +1366,16 @@ status = "disabled"; }; + hte_lic: hardware-timestamp@3aa0000 { + compatible = "nvidia,tegra194-gte-lic"; + reg = <0x3aa0000 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + nvidia,slices = <11>; + #timestamp-cells = <1>; + status = "okay"; + }; + hsp_top0: hsp@3c00000 { compatible = "nvidia,tegra194-hsp"; reg = <0x03c00000 0xa0000>; @@ -1579,6 +1589,16 @@ #mbox-cells = <2>; }; + hte_aon: hardware-timestamp@c1e0000 { + compatible = "nvidia,tegra194-gte-aon"; + reg = <0xc1e0000 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + nvidia,slices = <3>; + #timestamp-cells = <1>; + status = "okay"; + }; + gen2_i2c: i2c@c240000 { compatible = "nvidia,tegra194-i2c"; reg = <0x0c240000 0x10000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 0170bfa8a467..fecf9ab1bf17 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -949,6 +949,16 @@ clock-names = "fuse"; }; + hte_lic: hardware-timestamp@3aa0000 { + compatible = "nvidia,tegra234-gte-lic"; + reg = <0x3aa0000 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + nvidia,slices = <17>; + #timestamp-cells = <1>; + status = "okay"; + }; + hsp_top0: hsp@3c00000 { compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; reg = <0x03c00000 0xa0000>; @@ -1466,6 +1476,16 @@ #mbox-cells = <2>; }; + hte_aon: hardware-timestamp@c1e0000 { + compatible = "nvidia,tegra234-gte-aon"; + reg = <0xc1e0000 0x10000>; + interrupts = ; + nvidia,int-threshold = <1>; + nvidia,slices = <3>; + #timestamp-cells = <1>; + status = "okay"; + }; + gen2_i2c: i2c@c240000 { compatible = "nvidia,tegra194-i2c"; reg = <0xc240000 0x100>; From patchwork Thu Nov 3 17:45:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dipen Patel X-Patchwork-Id: 621177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E50FC433FE for ; Thu, 3 Nov 2022 17:46:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231689AbiKCRqN (ORCPT ); Thu, 3 Nov 2022 13:46:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53502 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231406AbiKCRpv (ORCPT ); Thu, 3 Nov 2022 13:45:51 -0400 Received: from NAM10-DM6-obe.outbound.protection.outlook.com (mail-dm6nam10on2079.outbound.protection.outlook.com [40.107.93.79]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8E081ADAF; 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Signed-off-by: Dipen Patel --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 0b6af3348e79..c6e04a4f89d5 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1307,6 +1307,9 @@ CONFIG_INTERCONNECT_QCOM_SM8150=m CONFIG_INTERCONNECT_QCOM_SM8250=m CONFIG_INTERCONNECT_QCOM_SM8350=m CONFIG_INTERCONNECT_QCOM_SM8450=m +CONFIG_HTE=y +CONFIG_HTE_TEGRA194=y +CONFIG_HTE_TEGRA194_TEST=m CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS_POSIX_ACL=y