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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id h64sm4098293pfj.40.2019.03.06.09.47.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Mar 2019 09:47:11 -0800 (PST) From: Bjorn Andersson To: Michael Turquette , Stephen Boyd , Rob Herring , Mark Rutland Cc: Andy Gross , David Brown , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] dt-bindings: clock: Introduce Qualcomm Turing Clock controller Date: Wed, 6 Mar 2019 09:47:56 -0800 Message-Id: <20190306174758.22462-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190306174758.22462-1-bjorn.andersson@linaro.org> References: <20190306174758.22462-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add devicetree binding for the turing clock controller found in QCS404. Signed-off-by: Bjorn Andersson --- .../bindings/clock/qcom,turingcc.txt | 19 +++++++++++++++++++ .../dt-bindings/clock/qcom,turingcc-qcs404.h | 15 +++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,turingcc.txt create mode 100644 include/dt-bindings/clock/qcom,turingcc-qcs404.h -- 2.18.0 diff --git a/Documentation/devicetree/bindings/clock/qcom,turingcc.txt b/Documentation/devicetree/bindings/clock/qcom,turingcc.txt new file mode 100644 index 000000000000..126517de5f9a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,turingcc.txt @@ -0,0 +1,19 @@ +Qualcomm Turing Clock & Reset Controller Binding +------------------------------------------------ + +Required properties : +- compatible: shall contain "qcom,qcs404-turingcc". +- reg: shall contain base register location and length. +- clocks: ahb clock for the TuringCC +- #clock-cells: from common clock binding, shall contain 1. +- #reset-cells: from common reset binding, shall contain 1. + +Example: + turingcc: clock-controller@800000 { + compatible = "qcom,qcs404-turingcc"; + reg = <0x00800000 0x30000>; + clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/qcom,turingcc-qcs404.h b/include/dt-bindings/clock/qcom,turingcc-qcs404.h new file mode 100644 index 000000000000..838faef57c67 --- /dev/null +++ b/include/dt-bindings/clock/qcom,turingcc-qcs404.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019, Linaro Ltd + */ + +#ifndef _DT_BINDINGS_CLK_TURING_QCS404_H +#define _DT_BINDINGS_CLK_TURING_QCS404_H + +#define TURING_Q6SS_Q6_AXIM_CLK 0 +#define TURING_Q6SS_AHBM_AON_CLK 1 +#define TURING_WRAPPER_AON_CLK 2 +#define TURING_Q6SS_AHBS_AON_CLK 3 +#define TURING_WRAPPER_QOS_AHBS_AON_CLK 4 + +#endif From patchwork Wed Mar 6 17:47:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 159760 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp6449200jad; Wed, 6 Mar 2019 09:47:28 -0800 (PST) X-Google-Smtp-Source: APXvYqzFGjZvdeIXMUViW6Ljh54W3mRC6fvk6fdCkf8L0ZKl8mXz7QhTdeYubm8ZEYikjqPy/CZf X-Received: by 2002:a17:902:5e3:: with SMTP id f90mr3844911plf.141.1551894448040; Wed, 06 Mar 2019 09:47:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551894448; cv=none; d=google.com; s=arc-20160816; b=0mwyUqZlprrLKZPNDco1tl+4rznJnLjvAQ5jDM2uvvLizSaBWx5xZdxmFMaTVAy+ja AQj91BRgwKm0IDltR+/ayyHJCakPc612xH7B8uwxX7PgP32oHIVPRWoGjtvoN0kfS0+N Lui+F44Cv4YS6pW/WZtmk9dYVdWk3FdT0kKjmenbPRhJIds3fYODKPJXlAr44tJ/otEj 11h9VT216u2KQ/YKEHu/0gIT2WsL1jnb/eQ81WLOxERDfmO6JLKcjPypBeOU9bDkabDY 3tOHUPf6Xgv0OvvJjqniK2Yjt7s/zQ3cAWydhWlHDCpe2RLvv9xsQdVGOxT/Nz8PcFaP 4Ulw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=oBZ8sxxMGg3aMYJDNUgn+TSIDMbgVfPO7ogD65Yj6kM=; b=Fo24C2fopDaejV7DrQv4yiEtsmezaSU0fXYB9Yzc4iBxbfH965gxbGi9hv8XFrqU2D qWy9YkzSVLVQtmiQWvTwvrFl/0da7rA8dgljHAMEeoLCu5SvAH4buZvckF9vdamtdrnQ S0/JQYW5Ylf98KrHSsOCG3XBMNT7EafDpeudeNtkkbtx2caSpEvXNUnYlQMrJFdbpX96 6KsfrtEa68HnOkU5W6g++2d6UqmIXKVLtOzF/48lMltqknqhgXmeCFE3oTjwwT1H0hsS hsmQqcs+JaOPhHNZjb/GDyD2WN5dR/ckcadPUWbAumo9+ctaXnxh3a+NEsN5zPBNDcjy LMLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nI2UrWF7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id h64sm4098293pfj.40.2019.03.06.09.47.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Mar 2019 09:47:13 -0800 (PST) From: Bjorn Andersson To: Michael Turquette , Stephen Boyd Cc: Andy Gross , David Brown , Rob Herring , Mark Rutland , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] clk: qcom: branch: Add AON clock ops Date: Wed, 6 Mar 2019 09:47:57 -0800 Message-Id: <20190306174758.22462-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190306174758.22462-1-bjorn.andersson@linaro.org> References: <20190306174758.22462-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Some clocks can only be turned on by resetting the block containing them, provide a clock type that allow us to reference these clocks and have the client drivers enable and "disable" them. Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/clk-branch.c | 6 ++++++ drivers/clk/qcom/clk-branch.h | 1 + 2 files changed, 7 insertions(+) -- 2.18.0 diff --git a/drivers/clk/qcom/clk-branch.c b/drivers/clk/qcom/clk-branch.c index 99446bf630aa..f869fc6aaed6 100644 --- a/drivers/clk/qcom/clk-branch.c +++ b/drivers/clk/qcom/clk-branch.c @@ -146,6 +146,12 @@ const struct clk_ops clk_branch2_ops = { }; EXPORT_SYMBOL_GPL(clk_branch2_ops); +const struct clk_ops clk_branch2_aon_ops = { + .enable = clk_branch2_enable, + .is_enabled = clk_is_enabled_regmap, +}; +EXPORT_SYMBOL_GPL(clk_branch2_aon_ops); + const struct clk_ops clk_branch_simple_ops = { .enable = clk_enable_regmap, .disable = clk_disable_regmap, diff --git a/drivers/clk/qcom/clk-branch.h b/drivers/clk/qcom/clk-branch.h index b3561e0a3984..17a58119165e 100644 --- a/drivers/clk/qcom/clk-branch.h +++ b/drivers/clk/qcom/clk-branch.h @@ -40,6 +40,7 @@ struct clk_branch { extern const struct clk_ops clk_branch_ops; extern const struct clk_ops clk_branch2_ops; extern const struct clk_ops clk_branch_simple_ops; +extern const struct clk_ops clk_branch2_aon_ops; #define to_clk_branch(_hw) \ container_of(to_clk_regmap(_hw), struct clk_branch, clkr)