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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bp6-20020a5d5a86000000b00228a6ce17b4sm1301236wrb.37.2022.10.27.07.02.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 07:02:11 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jerome Forissier Subject: [PATCH 1/2] hw/arm/boot: Set SME and SVE EL3 vector lengths when booting kernel Date: Thu, 27 Oct 2022 15:02:06 +0100 Message-Id: <20221027140207.413084-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221027140207.413084-1-peter.maydell@linaro.org> References: <20221027140207.413084-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org When we direct boot a kernel on a CPU which emulates EL3, we need to set up the EL3 system registers as the Linux kernel documentation specifies: https://www.kernel.org/doc/Documentation/arm64/booting.rst For SVE and SME this includes: - ZCR_EL3.LEN must be initialised to the same value for all CPUs the kernel is executed on. - SMCR_EL3.LEN must be initialised to the same value for all CPUs the kernel will execute on. Although we are technically compliant with this, the "same value" we currently use by default is the reset value of 0. This will end up forcing the guest kernel's SVE and SME vector length to be only the smallest supported length. Initialize the vector length fields to their maximum possible value, which is 0xf. If the implementation doesn't actually support that vector length then the effective vector length will be constrained down to the maximum supported value at point of use. This allows the guest to use all the vector lengths the emulated CPU supports (by programming the _EL2 and _EL1 versions of these registers.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/boot.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index b0b92af1889..0e4d1e5a816 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -762,10 +762,12 @@ static void do_cpu_reset(void *opaque) } if (cpu_isar_feature(aa64_sve, cpu)) { env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK; + env->vfp.zcr_el[3] = 0xf; } if (cpu_isar_feature(aa64_sme, cpu)) { env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK; env->cp15.scr_el3 |= SCR_ENTP2; + env->vfp.smcr_el[3] = 0xf; } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); From patchwork Thu Oct 27 14:02:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 619194 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp314122pvb; Thu, 27 Oct 2022 07:04:27 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6gPJYZNgITI1LcRNTKje7ofsOuQzYEC7R+bAwhVGEAGtV3g3q9a3pxSIi1u45+kBEuUcDq X-Received: by 2002:a5d:588c:0:b0:231:891c:6fc1 with SMTP id n12-20020a5d588c000000b00231891c6fc1mr31749302wrf.25.1666879467672; Thu, 27 Oct 2022 07:04:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666879467; cv=none; d=google.com; s=arc-20160816; b=pJERGZk/cjiLPRQ7ifZaHc4Qm92CgqjdZkPraDsJ0W2OeLNPlQL0v//mxc58Ym8CT9 c3IIgJ8j8BLwooC7Nvm/EGMJ8qf+qop90UIB6WJAqSwt7IRctyyPGIm77iSXbPl1SreK Qp4zXgKqJpfJ7cxXuIxHqdETgeIjAavaf3B3AdRr0JZ6ja/Mbq5whkIQt3C+HkBIWvCc mz15zWQ1vUNWvP3l7gu9HjRlRW9RJE9NBu7+Cy9CwqCS9QbOshyvepBXTJ4OvvtWTOh4 1bxYGAcykak7Lit1YRVz3ceffpfXghZH30U9DQQqXEcP0DuhrIoHqW1EetpnmrDB0IQr EwzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:sender:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nNtjyiRH/CIEjeKDHvpJCfaqZyeMGogdKG4xYD/wkmY=; b=Jbq+URLGA7g+Y/cX6mrrZnEg6a3m/j2H+hnD1yoBSP1nrnpTcqb6DADzqVbg68yqKO +2JAyzABd7mWxbJcIocVDsmgFRQIdFgnNyFfy4hW+Wam0VP4w5usZmLZNpkXX/5IhCeJ A2ySYNkwEeI1Ik0fc47fOFPM0ZsOOGFn2QoqKyKpSW0BvunRhV3Vx/MJAKKIAC7BxRw/ fYif2+PtNSXJXgKq4vdhaRpIOX1WkKSzMgDaS6uwLDUufbgqouub9IfOtVyW/GGyL/iP 7/C+5naQTpJnreTbQ9ofVCKpn15FeGHk9vVT0MJ8z8j5N0RQ80kyUxnErTyzxerJD2Dv RZ1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yrBraNwz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bp6-20020a5d5a86000000b00228a6ce17b4sm1301236wrb.37.2022.10.27.07.02.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Oct 2022 07:02:12 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jerome Forissier Subject: [PATCH 2/2] hw/arm/boot: Set SCR_EL3.HXEn when booting kernel Date: Thu, 27 Oct 2022 15:02:07 +0100 Message-Id: <20221027140207.413084-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221027140207.413084-1-peter.maydell@linaro.org> References: <20221027140207.413084-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Qemu-devel" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org When we direct boot a kernel on a CPU which emulates EL3, we need to set up the EL3 system registers as the Linux kernel documentation specifies: https://www.kernel.org/doc/Documentation/arm64/booting.rst For CPUs with FEAT_HCX support this includes: - SCR_EL3.HXEn (bit 38) must be initialised to 0b1. but we forgot to do this when implementing FEAT_HCX, which would mean that a guest trying to access the HCRX_EL2 register would crash. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/arm/boot.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 0e4d1e5a816..ddb7b1bdba0 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -769,6 +769,9 @@ static void do_cpu_reset(void *opaque) env->cp15.scr_el3 |= SCR_ENTP2; env->vfp.smcr_el[3] = 0xf; } + if (cpu_isar_feature(aa64_hcx, cpu)) { + env->cp15.scr_el3 |= SCR_HXEN; + } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); /* This hook is only supported for AArch32 currently: