From patchwork Fri Oct 21 16:18:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 617275 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D319FA373D for ; Fri, 21 Oct 2022 16:19:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229667AbiJUQTZ (ORCPT ); Fri, 21 Oct 2022 12:19:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52850 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229997AbiJUQTU (ORCPT ); Fri, 21 Oct 2022 12:19:20 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC124285B5A; Fri, 21 Oct 2022 09:19:17 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0600A61F1C; Fri, 21 Oct 2022 16:19:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 14A22C433D6; Fri, 21 Oct 2022 16:19:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666369156; bh=Ja1c5TLvRUJZ5yA/TNCgNqMFbfeQ7091tgqg/zH5PCc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=i90H23GTaAwjaBybJSxB/AfvreN4Amdmd0mxiZpJe6V2aW2X63wiXcHCRTabE8e9r VqFB1vFiOfjJqLZ0qZJfMZ36UhISaBBudckZicN8/Hbs3r/miGmQqnKtPYTpQaIOGP KZ+fvqRf+WyOMYpDQxvVwBIFz3vlfa9QqH8ynrs3GbxGEh4Gs7cliVd6vgoWbRwlKE rUttoDfGbt6GTPuederwk+/C+TmRhSWuUx8eK/2VC5Hq/JwOLmQnSPWNgHsHMjcQ9a ZpXi9GEhrrDSaoZ3G5vs8OcJ3z9qj8iN2fwHLsjUhQ6sl4edDwFgMtAFgAJ8BPEfO9 e8MI8v3XnE46w== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, matthias.bgg@gmail.com, linux-mediatek@lists.infradead.org, lorenzo.bianconi@redhat.com, Bo.Jiao@mediatek.com, sujuan.chen@mediatek.com, ryder.Lee@mediatek.com, evelyn.tsai@mediatek.com, devicetree@vger.kernel.org, robh@kernel.org, daniel@makrotopia.org Subject: [PATCH net-next 2/6] dt-bindings: net: mediatek: add WED RX binding for MT7986 eth driver Date: Fri, 21 Oct 2022 18:18:32 +0200 Message-Id: <7a454984f0001a71964114b71f353cb47af95ee6.1666368566.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document the binding for the RX Wireless Ethernet Dispatch core on the MT7986 ethernet driver used to offload traffic received by WLAN NIC and forwarded to LAN/WAN one. Signed-off-by: Lorenzo Bianconi --- .../arm/mediatek/mediatek,mt7622-wed.yaml | 126 ++++++++++++++++++ .../arm/mediatek/mediatek,mt7986-wo-boot.yaml | 45 +++++++ .../arm/mediatek/mediatek,mt7986-wo-ccif.yaml | 49 +++++++ .../arm/mediatek/mediatek,mt7986-wo-dlm.yaml | 66 +++++++++ 4 files changed, 286 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml index 84fb0a146b6e..623f11df5545 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml @@ -29,6 +29,59 @@ properties: interrupts: maxItems: 1 + mediatek,wocpu_emi: + $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 + description: + Phandle to a node describing reserved memory used by mtk wed firmware + (see bindings/reserved-memory/reserved-memory.txt) + + mediatek,wocpu_data: + $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 + description: + Phandle to a node describing reserved memory used by mtk wed firmware + (see bindings/reserved-memory/reserved-memory.txt) + + mediatek,wocpu_ilm: + $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 + description: + Phandle to a node describing memory used by mtk wed firmware + + mediatek,ap2woccif: + $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 + description: + Phandle to the mediatek wed-wo controller. + + mediatek,wocpu_boot: + $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 + description: + Phandle to the mediatek wed-wo boot interface. + + mediatek,wocpu_dlm: + $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 + description: + Phandle to the mediatek wed-wo rx hw ring. + +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt7986-wed + then: + properties: + mediatek,wocpu_data: true + mediatek,wocpu_boot: true + mediatek,wocpu_emi: true + mediatek,wocpu_ilm: true + mediatek,ap2woccif: true + mediatek,wocpu_dlm: true + required: - compatible - reg @@ -49,3 +102,76 @@ examples: interrupts = ; }; }; + + - | + #include + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + wocpu0_emi: wocpu0_emi@4fd00000 { + reg = <0 0x4fd00000 0 0x40000>; + no-map; + }; + + wocpu_data: wocpu_data@4fd80000 { + reg = <0 0x4fd80000 0 0x240000>; + no-map; + }; + }; + + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7986-ethsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + + #clock-cells = <1>; + #reset-cells = <1>; + ethsysrst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>; + }; + }; + + wocpu0_ilm: wocpu0_ilm@151e0000 { + compatible = "mediatek,wocpu0_ilm"; + reg = <0 0x151e0000 0 0x8000>; + }; + + cpu_boot: wocpu_boot@15194000 { + compatible = "mediatek,wocpu_boot", "syscon"; + reg = <0 0x15194000 0 0x1000>; + }; + + ap2woccif0: ap2woccif@151a5000 { + compatible = "mediatek,ap2woccif", "syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupts = ; + }; + + wocpu0_dlm: wocpu_dlm@151e8000 { + compatible = "mediatek,wocpu_dlm"; + reg = <0 0x151e8000 0 0x2000>; + resets = <ðsysrst 0>; + reset-names = "wocpu_rst"; + }; + + wed1: wed@1020a000 { + compatible = "mediatek,mt7986-wed","syscon"; + reg = <0 0x15010000 0 0x1000>; + interrupts = ; + + mediatek,wocpu_data = <&wocpu_data>; + mediatek,ap2woccif = <&ap2woccif0>; + mediatek,wocpu_ilm = <&wocpu0_ilm>; + mediatek,wocpu_dlm = <&wocpu0_dlm>; + mediatek,wocpu_emi = <&wocpu_emi>; + mediatek,wocpu_boot = <&cpu_boot>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml new file mode 100644 index 000000000000..dc8fdb706960 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-boot.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-boot.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek WED WO boot controller interface for MT7986 + +maintainers: + - Lorenzo Bianconi + - Felix Fietkau + +description: + The mediatek wo-boot provides a configuration interface for WED WO + boot controller on MT7986 soc. + +properties: + compatible: + items: + - enum: + - mediatek,wocpu_boot + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + cpu_boot: wocpu_boot@15194000 { + compatible = "mediatek,wocpu_boot", "syscon"; + reg = <0 0x15194000 0 0x1000>; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml new file mode 100644 index 000000000000..8fea86425983 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-ccif.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-ccif.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek WED WO Controller for MT7986 + +maintainers: + - Lorenzo Bianconi + - Felix Fietkau + +description: + The mediatek WO-ccif provides a configuration interface for WED WO + controller on MT7986 soc. + +properties: + compatible: + items: + - enum: + - mediatek,ap2woccif + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + ap2woccif0: ap2woccif@151a5000 { + compatible = "mediatek,ap2woccif", "syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupts = ; + }; + }; diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml new file mode 100644 index 000000000000..529343c57e4b --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7986-wo-dlm.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wo-dlm.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: MediaTek WED WO hw rx ring interface for MT7986 + +maintainers: + - Lorenzo Bianconi + - Felix Fietkau + +description: + The mediatek WO-dlm provides a configuration interface for WED WO + rx ring on MT7986 soc. + +properties: + compatible: + const: mediatek,wocpu_dlm + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + maxItems: 1 + +required: + - compatible + - reg + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + ethsys: syscon@15000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mediatek,mt7986-ethsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + + #clock-cells = <1>; + #reset-cells = <1>; + ethsysrst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>; + }; + }; + + wocpu0_dlm: wocpu_dlm@151e8000 { + compatible = "mediatek,wocpu_dlm"; + reg = <0 0x151e8000 0 0x2000>; + resets = <ðsysrst 0>; + reset-names = "wocpu_rst"; + }; + }; From patchwork Fri Oct 21 16:18:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 617274 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76A5BC433FE for ; Fri, 21 Oct 2022 16:19:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229997AbiJUQTh (ORCPT ); Fri, 21 Oct 2022 12:19:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52754 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230432AbiJUQTe (ORCPT ); Fri, 21 Oct 2022 12:19:34 -0400 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 803D027CEB; Fri, 21 Oct 2022 09:19:28 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 7BEB2B82CAE; Fri, 21 Oct 2022 16:19:26 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B4578C433D7; Fri, 21 Oct 2022 16:19:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666369165; bh=Uu4ajun6OKbC2FOpjqG1BqowKmQx4mfjQJgdvI1gg3M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=MNAeB8QsyHJpjLBDyeDJ4hzB1IWvEQajSoZ6MZwy6oSN3GitkYdWUk7ddBYOVdb5/ vykTzmidnkc2XdCan0mzE6/2Ln9C+LHK2NGNZEoZSzmdVX45G6iSB6fwJ58rWn7Ugi 6KgSHg//LtUBkHX2+llbaCo+2/sSTnh7MamZ8rrQ8XD9O5g9vjjoHtsvOcIgMIOO6m M53X4BDe599LzNJYwEgyCf/UQ2H0MxvtHVp3CEQETD6Zu6HmYpDZ2O7r9sgniUKXha wK5tgeA4hLtKXysn7vhcc1xgTYnWQU8DP1VMICxj5RaDMRRXkaBgRsbyBZfQhxVjFA 4ttfr2vbqK6CA== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, matthias.bgg@gmail.com, linux-mediatek@lists.infradead.org, lorenzo.bianconi@redhat.com, Bo.Jiao@mediatek.com, sujuan.chen@mediatek.com, ryder.Lee@mediatek.com, evelyn.tsai@mediatek.com, devicetree@vger.kernel.org, robh@kernel.org, daniel@makrotopia.org Subject: [PATCH net-next 4/6] net: ethernet: mtk_wed: introduce wed wo support Date: Fri, 21 Oct 2022 18:18:34 +0200 Message-Id: X-Mailer: git-send-email 2.37.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Introduce WO chip support to mtk wed driver. MTK WED WO is used to implement RX Wireless Ethernet Dispatch and offload traffic received by wlan nic to the wired interface. Tested-by: Daniel Golle Co-developed-by: Sujuan Chen Signed-off-by: Sujuan Chen Signed-off-by: Lorenzo Bianconi --- drivers/net/ethernet/mediatek/Makefile | 2 +- drivers/net/ethernet/mediatek/mtk_wed.c | 7 +- drivers/net/ethernet/mediatek/mtk_wed.h | 2 + drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 3 +- drivers/net/ethernet/mediatek/mtk_wed_wo.c | 545 ++++++++++++++++++++ drivers/net/ethernet/mediatek/mtk_wed_wo.h | 107 ++++ 6 files changed, 662 insertions(+), 4 deletions(-) create mode 100644 drivers/net/ethernet/mediatek/mtk_wed_wo.c diff --git a/drivers/net/ethernet/mediatek/Makefile b/drivers/net/ethernet/mediatek/Makefile index d4bdefa77159..8e0c61c33ff8 100644 --- a/drivers/net/ethernet/mediatek/Makefile +++ b/drivers/net/ethernet/mediatek/Makefile @@ -5,7 +5,7 @@ obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o -mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o +mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o ifdef CONFIG_DEBUG_FS mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o endif diff --git a/drivers/net/ethernet/mediatek/mtk_wed.c b/drivers/net/ethernet/mediatek/mtk_wed.c index 65e01bf4b4d2..9c9dd17332b6 100644 --- a/drivers/net/ethernet/mediatek/mtk_wed.c +++ b/drivers/net/ethernet/mediatek/mtk_wed.c @@ -16,6 +16,7 @@ #include "mtk_wed_regs.h" #include "mtk_wed.h" #include "mtk_ppe.h" +#include "mtk_wed_wo.h" #define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000) @@ -355,6 +356,8 @@ mtk_wed_detach(struct mtk_wed_device *dev) mtk_wed_free_buffer(dev); mtk_wed_free_tx_rings(dev); + if (hw->version != 1) + mtk_wed_wo_deinit(hw); if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) { struct device_node *wlan_node; @@ -878,9 +881,11 @@ mtk_wed_attach(struct mtk_wed_device *dev) } mtk_wed_hw_init_early(dev); - if (hw->hifsys) + if (hw->version == 1) regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, BIT(hw->index), 0); + else + ret = mtk_wed_wo_init(hw); out: mutex_unlock(&hw_lock); diff --git a/drivers/net/ethernet/mediatek/mtk_wed.h b/drivers/net/ethernet/mediatek/mtk_wed.h index ae420ca01a48..af656fd31ff9 100644 --- a/drivers/net/ethernet/mediatek/mtk_wed.h +++ b/drivers/net/ethernet/mediatek/mtk_wed.h @@ -10,6 +10,7 @@ #include struct mtk_eth; +struct mtk_wed_wo; struct mtk_wed_hw { struct device_node *node; @@ -22,6 +23,7 @@ struct mtk_wed_hw { struct regmap *mirror; struct dentry *debugfs_dir; struct mtk_wed_device *wed_dev; + struct mtk_wed_wo *wed_wo; u32 debugfs_reg; u32 num_flows; u8 version; diff --git a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c index 4100258b0ec1..94f9dd981ff8 100644 --- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c +++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c @@ -122,8 +122,7 @@ mtk_wed_mcu_skb_send_msg(struct mtk_wed_wo *wo, struct sk_buff *skb, if (id == MTK_WED_MODULE_ID_WO) hdr->flag |= cpu_to_le16(MTK_WED_WARP_CMD_FLAG_FROM_TO_WO); - dev_kfree_skb(skb); - return 0; + return mtk_wed_wo_queue_tx_skb(wo, &wo->q_tx, skb); } static int diff --git a/drivers/net/ethernet/mediatek/mtk_wed_wo.c b/drivers/net/ethernet/mediatek/mtk_wed_wo.c new file mode 100644 index 000000000000..ffc602449d0b --- /dev/null +++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.c @@ -0,0 +1,545 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (C) 2022 Lorenzo Bianconi */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mtk_wed.h" +#include "mtk_wed_regs.h" +#include "mtk_wed_wo.h" + +static u32 +mtk_wed_mmio_r32(struct mtk_wed_wo *wo, u32 reg) +{ + u32 val; + + if (regmap_read(wo->mmio.regs, reg, &val)) + val = ~0; + + return val; +} + +static void +mtk_wed_mmio_w32(struct mtk_wed_wo *wo, u32 reg, u32 val) +{ + regmap_write(wo->mmio.regs, reg, val); +} + +static u32 +mtk_wed_wo_get_isr(struct mtk_wed_wo *wo) +{ + u32 val = mtk_wed_mmio_r32(wo, MTK_WED_WO_CCIF_RCHNUM); + + return val & MTK_WED_WO_CCIF_RCHNUM_MASK; +} + +static void +mtk_wed_wo_set_isr(struct mtk_wed_wo *wo, u32 mask) +{ + mtk_wed_mmio_w32(wo, MTK_WED_WO_CCIF_IRQ0_MASK, mask); +} + +static void +mtk_wed_wo_set_ack(struct mtk_wed_wo *wo, u32 mask) +{ + mtk_wed_mmio_w32(wo, MTK_WED_WO_CCIF_ACK, mask); +} + +static void +mtk_wed_wo_set_isr_mask(struct mtk_wed_wo *wo, u32 mask, u32 val, bool set) +{ + unsigned long flags; + + spin_lock_irqsave(&wo->mmio.lock, flags); + wo->mmio.irq_mask &= ~mask; + wo->mmio.irq_mask |= val; + if (set) + mtk_wed_wo_set_isr(wo, wo->mmio.irq_mask); + spin_unlock_irqrestore(&wo->mmio.lock, flags); +} + +static void +mtk_wed_wo_irq_enable(struct mtk_wed_wo *wo, u32 mask) +{ + mtk_wed_wo_set_isr_mask(wo, 0, mask, false); + tasklet_schedule(&wo->mmio.irq_tasklet); +} + +static void +mtk_wed_wo_irq_disable(struct mtk_wed_wo *wo, u32 mask) +{ + mtk_wed_wo_set_isr_mask(wo, mask, 0, true); +} + +static void +mtk_wed_wo_kickout(struct mtk_wed_wo *wo) +{ + mtk_wed_mmio_w32(wo, MTK_WED_WO_CCIF_BUSY, 1 << MTK_WED_WO_TXCH_NUM); + mtk_wed_mmio_w32(wo, MTK_WED_WO_CCIF_TCHNUM, MTK_WED_WO_TXCH_NUM); +} + +static void +mtk_wed_wo_queue_kick(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q, + u32 val) +{ + wmb(); + mtk_wed_mmio_w32(wo, q->regs.cpu_idx, val); +} + +static void * +mtk_wed_wo_dequeue(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q, u32 *len, + bool flush) +{ + int buf_len = SKB_WITH_OVERHEAD(q->buf_size); + int index = (q->tail + 1) % q->n_desc; + struct mtk_wed_wo_queue_entry *entry; + struct mtk_wed_wo_queue_desc *desc; + void *buf; + + if (!q->queued) + return NULL; + + if (flush) + q->desc[index].ctrl |= cpu_to_le32(MTK_WED_WO_CTL_DMA_DONE); + else if (!(q->desc[index].ctrl & cpu_to_le32(MTK_WED_WO_CTL_DMA_DONE))) + return NULL; + + q->tail = index; + q->queued--; + + desc = &q->desc[index]; + entry = &q->entry[index]; + buf = entry->buf; + if (len) + *len = FIELD_GET(MTK_WED_WO_CTL_SD_LEN0, + le32_to_cpu(READ_ONCE(desc->ctrl))); + if (buf) + dma_unmap_single(wo->hw->dev, entry->addr, buf_len, + DMA_FROM_DEVICE); + entry->buf = NULL; + + return buf; +} + +static int +mtk_wed_wo_queue_rx_skb(struct mtk_wed_wo *wo, struct sk_buff *skb) +{ + struct mtk_wed_mcu_hdr *hdr = (struct mtk_wed_mcu_hdr *)skb->data; + int ret; + + ret = mtk_wed_mcu_check_msg(wo, skb); + if (ret) { + dev_kfree_skb(skb); + return ret; + } + + if (hdr->flag & cpu_to_le16(MTK_WED_WARP_CMD_FLAG_RSP)) + mtk_wed_mcu_rx_event(wo, skb); + else + mtk_wed_mcu_rx_unsolicited_event(wo, skb); + + return 0; +} + +static int +mtk_wed_wo_queue_refill(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q, + gfp_t gfp, bool rx) +{ + enum dma_data_direction dir = rx ? DMA_FROM_DEVICE : DMA_TO_DEVICE; + int n_buf = 0; + + spin_lock_bh(&q->lock); + while (q->queued < q->n_desc) { + void *buf = page_frag_alloc(&q->cache, q->buf_size, gfp); + struct mtk_wed_wo_queue_entry *entry; + dma_addr_t addr; + + if (!buf) + break; + + addr = dma_map_single(wo->hw->dev, buf, q->buf_size, dir); + if (unlikely(dma_mapping_error(wo->hw->dev, addr))) { + skb_free_frag(buf); + break; + } + + q->head = (q->head + 1) % q->n_desc; + entry = &q->entry[q->head]; + entry->addr = addr; + entry->len = q->buf_size; + q->entry[q->head].buf = buf; + + if (rx) { + struct mtk_wed_wo_queue_desc *desc = &q->desc[q->head]; + u32 ctrl = MTK_WED_WO_CTL_LAST_SEC0 | + FIELD_PREP(MTK_WED_WO_CTL_SD_LEN0, + entry->len); + + WRITE_ONCE(desc->buf0, cpu_to_le32(addr)); + WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl)); + } + q->queued++; + n_buf++; + } + spin_unlock_bh(&q->lock); + + return n_buf; +} + +static void +mtk_wed_wo_poll_complete(struct mtk_wed_wo *wo) +{ + mtk_wed_wo_set_ack(wo, MTK_WED_WO_RXCH_INT_MASK); + mtk_wed_wo_irq_enable(wo, MTK_WED_WO_RXCH_INT_MASK); +} + +static int +mtk_wed_wo_rx_process(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q, + int budget) +{ + int done = 0; + + while (done < budget) { + struct sk_buff *skb; + void *data; + u32 len; + + data = mtk_wed_wo_dequeue(wo, q, &len, false); + if (!data) + break; + + skb = build_skb(data, q->buf_size); + if (!skb) { + skb_free_frag(data); + continue; + } + + __skb_put(skb, len); + mtk_wed_wo_queue_rx_skb(wo, skb); + done++; + } + + if (mtk_wed_wo_queue_refill(wo, q, GFP_ATOMIC, true)) { + u32 index = (q->head - 1) % q->n_desc; + + mtk_wed_wo_queue_kick(wo, q, index); + } + + return done; +} + +static int +mtk_wed_wo_rx_poll(struct napi_struct *napi, int budget) +{ + struct mtk_wed_wo *wo = container_of(napi->dev, struct mtk_wed_wo, + mmio.napi_dev); + int done = 0, cur; + + rcu_read_lock(); + do { + cur = mtk_wed_wo_rx_process(wo, &wo->q_rx, budget - done); + /* rx packet handle */ + done += cur; + } while (cur && done < budget); + rcu_read_unlock(); + + if (done < budget && napi_complete(napi)) + mtk_wed_wo_poll_complete(wo); + + return done; +} + +static irqreturn_t +mtk_wed_wo_irq_handler(int irq, void *data) +{ + struct mtk_wed_wo *wo = data; + + mtk_wed_wo_set_isr(wo, 0); + tasklet_schedule(&wo->mmio.irq_tasklet); + + return IRQ_HANDLED; +} + +static void mtk_wed_wo_irq_tasklet(struct tasklet_struct *t) +{ + struct mtk_wed_wo *wo = from_tasklet(wo, t, mmio.irq_tasklet); + u32 intr, mask; + + /* disable interrupts */ + mtk_wed_wo_set_isr(wo, 0); + + intr = mtk_wed_wo_get_isr(wo); + intr &= wo->mmio.irq_mask; + mask = intr & (MTK_WED_WO_RXCH_INT_MASK | MTK_WED_WO_EXCEPTION_INT_MASK); + mtk_wed_wo_irq_disable(wo, mask); + + if (intr & MTK_WED_WO_RXCH_INT_MASK) + napi_schedule(&wo->mmio.napi); +} + +/* mtk wed wo hw queues */ + +static int +mtk_wed_wo_queue_alloc(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q, + int n_desc, int buf_size, int index, + struct mtk_wed_wo_queue_regs *regs) +{ + spin_lock_init(&q->lock); + q->regs = *regs; + q->n_desc = n_desc; + q->buf_size = buf_size; + + q->desc = dmam_alloc_coherent(wo->hw->dev, n_desc * sizeof(*q->desc), + &q->desc_dma, GFP_KERNEL); + if (!q->desc) + return -ENOMEM; + + q->entry = devm_kzalloc(wo->hw->dev, n_desc * sizeof(*q->entry), + GFP_KERNEL); + if (!q->entry) + return -ENOMEM; + + return 0; +} + +static void +mtk_wed_wo_queue_free(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q) +{ + mtk_wed_mmio_w32(wo, q->regs.cpu_idx, 0); + dma_free_coherent(wo->hw->dev, q->n_desc * sizeof(*q->desc), q->desc, + q->desc_dma); +} + +static void +mtk_wed_wo_queue_tx_clean(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q) +{ + struct page *page; + int i; + + spin_lock_bh(&q->lock); + for (i = 0; i < q->n_desc; i++) { + struct mtk_wed_wo_queue_entry *entry = &q->entry[i]; + + dma_unmap_single(wo->hw->dev, entry->addr, entry->len, + DMA_TO_DEVICE); + skb_free_frag(entry->buf); + entry->buf = NULL; + } + spin_unlock_bh(&q->lock); + + if (!q->cache.va) + return; + + page = virt_to_page(q->cache.va); + __page_frag_cache_drain(page, q->cache.pagecnt_bias); + memset(&q->cache, 0, sizeof(q->cache)); +} + +static void +mtk_wed_wo_queue_rx_clean(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q) +{ + struct page *page; + + spin_lock_bh(&q->lock); + for (;;) { + void *buf = mtk_wed_wo_dequeue(wo, q, NULL, true); + + if (!buf) + break; + + skb_free_frag(buf); + } + spin_unlock_bh(&q->lock); + + if (!q->cache.va) + return; + + page = virt_to_page(q->cache.va); + __page_frag_cache_drain(page, q->cache.pagecnt_bias); + memset(&q->cache, 0, sizeof(q->cache)); +} + +static void +mtk_wed_wo_queue_reset(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q) +{ + mtk_wed_mmio_w32(wo, q->regs.cpu_idx, 0); + mtk_wed_mmio_w32(wo, q->regs.desc_base, q->desc_dma); + mtk_wed_mmio_w32(wo, q->regs.ring_size, q->n_desc); +} + +int mtk_wed_wo_queue_tx_skb(struct mtk_wed_wo *wo, struct mtk_wed_wo_queue *q, + struct sk_buff *skb) +{ + struct mtk_wed_wo_queue_entry *entry; + struct mtk_wed_wo_queue_desc *desc; + int ret = 0, index; + u32 ctrl; + + spin_lock_bh(&q->lock); + + q->tail = mtk_wed_mmio_r32(wo, q->regs.dma_idx); + index = (q->head + 1) % q->n_desc; + if (q->tail == index) { + ret = -ENOMEM; + goto out; + } + + entry = &q->entry[index]; + if (skb->len > entry->len) { + ret = -ENOMEM; + goto out; + } + + desc = &q->desc[index]; + q->head = index; + + dma_sync_single_for_cpu(wo->hw->dev, entry->addr, skb->len, + DMA_TO_DEVICE); + memcpy(entry->buf, skb->data, skb->len); + dma_sync_single_for_device(wo->hw->dev, entry->addr, skb->len, + DMA_TO_DEVICE); + + ctrl = FIELD_PREP(MTK_WED_WO_CTL_SD_LEN0, skb->len) | + MTK_WED_WO_CTL_LAST_SEC0 | MTK_WED_WO_CTL_DMA_DONE; + WRITE_ONCE(desc->buf0, cpu_to_le32(entry->addr)); + WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl)); + + mtk_wed_wo_queue_kick(wo, q, q->head); + mtk_wed_wo_kickout(wo); +out: + spin_unlock_bh(&q->lock); + + dev_kfree_skb(skb); + + return ret; +} + +static int +mtk_wed_wo_exception_init(struct mtk_wed_wo *wo) +{ + return 0; +} + +static int +mtk_wed_wo_hardware_init(struct mtk_wed_wo *wo) +{ + struct mtk_wed_wo_queue_regs regs; + struct device_node *np; + int ret; + + np = of_parse_phandle(wo->hw->node, "mediatek,ap2woccif", 0); + if (!np) + return -ENODEV; + + wo->mmio.regs = syscon_regmap_lookup_by_phandle(np, NULL); + if (IS_ERR_OR_NULL(wo->mmio.regs)) + return PTR_ERR(wo->mmio.regs); + + wo->mmio.irq = irq_of_parse_and_map(np, 0); + wo->mmio.irq_mask = MTK_WED_WO_ALL_INT_MASK; + spin_lock_init(&wo->mmio.lock); + tasklet_setup(&wo->mmio.irq_tasklet, mtk_wed_wo_irq_tasklet); + + ret = devm_request_irq(wo->hw->dev, wo->mmio.irq, + mtk_wed_wo_irq_handler, IRQF_TRIGGER_HIGH, + KBUILD_MODNAME, wo); + if (ret) + goto error; + + regs.desc_base = MTK_WED_WO_CCIF_DUMMY1; + regs.ring_size = MTK_WED_WO_CCIF_DUMMY2; + regs.dma_idx = MTK_WED_WO_CCIF_SHADOW4; + regs.cpu_idx = MTK_WED_WO_CCIF_DUMMY3; + + ret = mtk_wed_wo_queue_alloc(wo, &wo->q_tx, MTK_WED_WO_RING_SIZE, + MTK_WED_WO_CMD_LEN, MTK_WED_WO_TXCH_NUM, + ®s); + if (ret) + goto error; + + mtk_wed_wo_queue_refill(wo, &wo->q_tx, GFP_KERNEL, false); + mtk_wed_wo_queue_reset(wo, &wo->q_tx); + + regs.desc_base = MTK_WED_WO_CCIF_DUMMY5; + regs.ring_size = MTK_WED_WO_CCIF_DUMMY6; + regs.dma_idx = MTK_WED_WO_CCIF_SHADOW8; + regs.cpu_idx = MTK_WED_WO_CCIF_DUMMY7; + + ret = mtk_wed_wo_queue_alloc(wo, &wo->q_rx, MTK_WED_WO_RING_SIZE, + MTK_WED_WO_CMD_LEN, MTK_WED_WO_RXCH_NUM, + ®s); + if (ret) + goto error; + + init_dummy_netdev(&wo->mmio.napi_dev); + snprintf(wo->mmio.napi_dev.name, sizeof(wo->mmio.napi_dev.name), "%s", + "mtk_wed_wo"); + netif_napi_add(&wo->mmio.napi_dev, &wo->mmio.napi, mtk_wed_wo_rx_poll); + mtk_wed_wo_queue_refill(wo, &wo->q_rx, GFP_KERNEL, true); + mtk_wed_wo_queue_reset(wo, &wo->q_rx); + napi_enable(&wo->mmio.napi); + + /* rx queue irqmask */ + mtk_wed_wo_set_isr(wo, wo->mmio.irq_mask); + + return 0; + +error: + devm_free_irq(wo->hw->dev, wo->mmio.irq, wo); + + return ret; +} + +static void +mtk_wed_wo_hw_deinit(struct mtk_wed_wo *wo) +{ + /* disable interrupts */ + mtk_wed_wo_set_isr(wo, 0); + + tasklet_disable(&wo->mmio.irq_tasklet); + netif_napi_del(&wo->mmio.napi); + + disable_irq(wo->mmio.irq); + devm_free_irq(wo->hw->dev, wo->mmio.irq, wo); + + mtk_wed_wo_queue_tx_clean(wo, &wo->q_tx); + mtk_wed_wo_queue_rx_clean(wo, &wo->q_rx); + mtk_wed_wo_queue_free(wo, &wo->q_tx); + mtk_wed_wo_queue_free(wo, &wo->q_rx); +} + +int mtk_wed_wo_init(struct mtk_wed_hw *hw) +{ + struct mtk_wed_wo *wo; + int ret; + + wo = devm_kzalloc(hw->dev, sizeof(*wo), GFP_KERNEL); + if (!wo) + return -ENOMEM; + + hw->wed_wo = wo; + wo->hw = hw; + + ret = mtk_wed_wo_hardware_init(wo); + if (ret) + return ret; + + ret = mtk_wed_mcu_init(wo); + if (ret) + return ret; + + return mtk_wed_wo_exception_init(wo); +} + +void mtk_wed_wo_deinit(struct mtk_wed_hw *hw) +{ + struct mtk_wed_wo *wo = hw->wed_wo; + + mtk_wed_wo_hw_deinit(wo); +} diff --git a/drivers/net/ethernet/mediatek/mtk_wed_wo.h b/drivers/net/ethernet/mediatek/mtk_wed_wo.h index bf33adcb7320..cabaa09956e6 100644 --- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h +++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h @@ -79,6 +79,54 @@ enum mtk_wed_dummy_cr_idx { #define MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK BIT(5) #define MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK BIT(0) +#define MTK_WED_WO_RING_SIZE 256 +#define MTK_WED_WO_CMD_LEN 1504 + +#define MTK_WED_WO_TXCH_NUM 0 +#define MTK_WED_WO_RXCH_NUM 1 +#define MTK_WED_WO_RXCH_WO_EXCEPTION 7 + +#define MTK_WED_WO_TXCH_INT_MASK BIT(0) +#define MTK_WED_WO_RXCH_INT_MASK BIT(1) +#define MTK_WED_WO_EXCEPTION_INT_MASK BIT(7) +#define MTK_WED_WO_ALL_INT_MASK (MTK_WED_WO_RXCH_INT_MASK | \ + MTK_WED_WO_EXCEPTION_INT_MASK) + +#define MTK_WED_WO_CCIF_BUSY 0x004 +#define MTK_WED_WO_CCIF_START 0x008 +#define MTK_WED_WO_CCIF_TCHNUM 0x00c +#define MTK_WED_WO_CCIF_RCHNUM 0x010 +#define MTK_WED_WO_CCIF_RCHNUM_MASK GENMASK(7, 0) + +#define MTK_WED_WO_CCIF_ACK 0x014 +#define MTK_WED_WO_CCIF_IRQ0_MASK 0x018 +#define MTK_WED_WO_CCIF_IRQ1_MASK 0x01c +#define MTK_WED_WO_CCIF_DUMMY1 0x020 +#define MTK_WED_WO_CCIF_DUMMY2 0x024 +#define MTK_WED_WO_CCIF_DUMMY3 0x028 +#define MTK_WED_WO_CCIF_DUMMY4 0x02c +#define MTK_WED_WO_CCIF_SHADOW1 0x030 +#define MTK_WED_WO_CCIF_SHADOW2 0x034 +#define MTK_WED_WO_CCIF_SHADOW3 0x038 +#define MTK_WED_WO_CCIF_SHADOW4 0x03c +#define MTK_WED_WO_CCIF_DUMMY5 0x050 +#define MTK_WED_WO_CCIF_DUMMY6 0x054 +#define MTK_WED_WO_CCIF_DUMMY7 0x058 +#define MTK_WED_WO_CCIF_DUMMY8 0x05c +#define MTK_WED_WO_CCIF_SHADOW5 0x060 +#define MTK_WED_WO_CCIF_SHADOW6 0x064 +#define MTK_WED_WO_CCIF_SHADOW7 0x068 +#define MTK_WED_WO_CCIF_SHADOW8 0x06c + +#define MTK_WED_WO_CTL_SD_LEN1 GENMASK(13, 0) +#define MTK_WED_WO_CTL_LAST_SEC1 BIT(14) +#define MTK_WED_WO_CTL_BURST BIT(15) +#define MTK_WED_WO_CTL_SD_LEN0_SHIFT 16 +#define MTK_WED_WO_CTL_SD_LEN0 GENMASK(29, 16) +#define MTK_WED_WO_CTL_LAST_SEC0 BIT(30) +#define MTK_WED_WO_CTL_DMA_DONE BIT(31) +#define MTK_WED_WO_INFO_WINFO GENMASK(15, 0) + struct mtk_wed_fw_region_meta { const char *name; void __iomem *addr; @@ -111,10 +159,53 @@ struct mtk_wed_fw_trailer { u32 crc; }; +struct mtk_wed_wo_queue_regs { + u32 desc_base; + u32 ring_size; + u32 cpu_idx; + u32 dma_idx; +}; + +struct mtk_wed_wo_queue_desc { + __le32 buf0; + __le32 ctrl; + __le32 buf1; + __le32 info; + __le32 reserved[4]; +} __packed __aligned(32); + +struct mtk_wed_wo_queue_entry { + dma_addr_t addr; + void *buf; + u32 len; +}; + +struct mtk_wed_wo_queue { + struct mtk_wed_wo_queue_regs regs; + + struct page_frag_cache cache; + spinlock_t lock; + + struct mtk_wed_wo_queue_desc *desc; + dma_addr_t desc_dma; + + struct mtk_wed_wo_queue_entry *entry; + + u16 head; + u16 tail; + int n_desc; + int queued; + int buf_size; + +}; + struct mtk_wed_wo { struct mtk_wed_hw *hw; struct regmap *boot; + struct mtk_wed_wo_queue q_tx; + struct mtk_wed_wo_queue q_rx; + struct { struct mutex mutex; int timeout; @@ -123,6 +214,18 @@ struct mtk_wed_wo { struct sk_buff_head res_q; wait_queue_head_t wait; } mcu; + + struct { + struct regmap *regs; + + spinlock_t lock; + struct tasklet_struct irq_tasklet; + int irq; + u32 irq_mask; + + struct net_device napi_dev; + struct napi_struct napi; + } mmio; }; static inline int @@ -148,5 +251,9 @@ void mtk_wed_mcu_rx_unsolicited_event(struct mtk_wed_wo *wo, int mtk_wed_mcu_send_msg(struct mtk_wed_wo *wo, int id, int cmd, const void *data, int len, bool wait_resp); int mtk_wed_mcu_init(struct mtk_wed_wo *wo); +int mtk_wed_wo_init(struct mtk_wed_hw *hw); +void mtk_wed_wo_deinit(struct mtk_wed_hw *hw); +int mtk_wed_wo_queue_tx_skb(struct mtk_wed_wo *dev, struct mtk_wed_wo_queue *q, + struct sk_buff *skb); #endif /* __MTK_WED_WO_H */ From patchwork Fri Oct 21 16:18:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Bianconi X-Patchwork-Id: 617273 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31AE2FA373D for ; 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d=kernel.org; s=k20201202; t=1666369174; bh=qXT4GPzDeP9IpTekE6kjrT6VMQoqce0Ms6UpGOHy2nk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZR8r9yjYUOErfzFZjbKYliEB6G0CWhEdE86roAA2ixpSF6HKWxaBhAL1LLPy3f5J+ qDe6zRxqGywbnEkTgkJBeGkd04AV/3+chi3DhIWIYT82/U/tsj8spD+lJvGlz7s3z9 H+L2UssekGHzy3/AyU1gD40XlNn8rAuSBphXPwdbXjPLpceKLe9sLsc6AG+LpyI4P0 0dRO+bc+m7zLVzekDSpj5N0F0lQ/f3JdmBuaiKX4R79WlanecZbigdKGE1gc55dVW7 426gl1RctB9Irr9zWHXLOK8ad65Wom/pLFe1LEWnKRihjhT1Gj3YqwgB8PuAOl7jST 1zJRp4T6AC6KQ== From: Lorenzo Bianconi To: netdev@vger.kernel.org Cc: nbd@nbd.name, john@phrozen.org, sean.wang@mediatek.com, Mark-MC.Lee@mediatek.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, matthias.bgg@gmail.com, linux-mediatek@lists.infradead.org, lorenzo.bianconi@redhat.com, Bo.Jiao@mediatek.com, sujuan.chen@mediatek.com, ryder.Lee@mediatek.com, evelyn.tsai@mediatek.com, devicetree@vger.kernel.org, robh@kernel.org, daniel@makrotopia.org Subject: [PATCH net-next 6/6] net: ethernet: mtk_wed: add rx mib counters Date: Fri, 21 Oct 2022 18:18:36 +0200 Message-Id: <5909a53b0b37b9409b74335919d0a0efb307d1d5.1666368566.git.lorenzo@kernel.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Introduce WED RX MIB counters support available on MT7986a SoC. Tested-by: Daniel Golle Co-developed-by: Sujuan Chen Signed-off-by: Sujuan Chen Signed-off-by: Lorenzo Bianconi --- .../net/ethernet/mediatek/mtk_wed_debugfs.c | 87 +++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c index f420f187e837..56f663439721 100644 --- a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c +++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c @@ -2,6 +2,7 @@ /* Copyright (C) 2021 Felix Fietkau */ #include +#include #include "mtk_wed.h" #include "mtk_wed_regs.h" @@ -18,6 +19,8 @@ enum { DUMP_TYPE_WDMA, DUMP_TYPE_WPDMA_TX, DUMP_TYPE_WPDMA_TXFREE, + DUMP_TYPE_WPDMA_RX, + DUMP_TYPE_WED_RRO, }; #define DUMP_STR(_str) { _str, 0, DUMP_TYPE_STRING } @@ -36,6 +39,9 @@ enum { #define DUMP_WPDMA_TX_RING(_n) DUMP_RING("WPDMA_TX" #_n, 0, DUMP_TYPE_WPDMA_TX, _n) #define DUMP_WPDMA_TXFREE_RING DUMP_RING("WPDMA_RX1", 0, DUMP_TYPE_WPDMA_TXFREE) +#define DUMP_WPDMA_RX_RING(_n) DUMP_RING("WPDMA_RX" #_n, 0, DUMP_TYPE_WPDMA_RX, _n) +#define DUMP_WED_RRO_RING(_base)DUMP_RING("WED_RRO_MIOD", MTK_##_base, DUMP_TYPE_WED_RRO) +#define DUMP_WED_RRO_FDBK(_base)DUMP_RING("WED_RRO_FDBK", MTK_##_base, DUMP_TYPE_WED_RRO) static void print_reg_val(struct seq_file *s, const char *name, u32 val) @@ -57,6 +63,7 @@ dump_wed_regs(struct seq_file *s, struct mtk_wed_device *dev, cur > regs ? "\n" : "", cur->name); continue; + case DUMP_TYPE_WED_RRO: case DUMP_TYPE_WED: val = wed_r32(dev, cur->offset); break; @@ -69,6 +76,9 @@ dump_wed_regs(struct seq_file *s, struct mtk_wed_device *dev, case DUMP_TYPE_WPDMA_TXFREE: val = wpdma_txfree_r32(dev, cur->offset); break; + case DUMP_TYPE_WPDMA_RX: + val = wpdma_rx_r32(dev, cur->base, cur->offset); + break; } print_reg_val(s, cur->name, val); } @@ -132,6 +142,80 @@ wed_txinfo_show(struct seq_file *s, void *data) } DEFINE_SHOW_ATTRIBUTE(wed_txinfo); +static int +wed_rxinfo_show(struct seq_file *s, void *data) +{ + static const struct reg_dump regs[] = { + DUMP_STR("WPDMA RX"), + DUMP_WPDMA_RX_RING(0), + DUMP_WPDMA_RX_RING(1), + + DUMP_STR("WPDMA RX"), + DUMP_WED(WED_WPDMA_RX_D_MIB(0)), + DUMP_WED_RING(WED_WPDMA_RING_RX_DATA(0)), + DUMP_WED(WED_WPDMA_RX_D_PROCESSED_MIB(0)), + DUMP_WED(WED_WPDMA_RX_D_MIB(1)), + DUMP_WED_RING(WED_WPDMA_RING_RX_DATA(1)), + DUMP_WED(WED_WPDMA_RX_D_PROCESSED_MIB(1)), + DUMP_WED(WED_WPDMA_RX_D_COHERENT_MIB), + + DUMP_STR("WED RX"), + DUMP_WED_RING(WED_RING_RX_DATA(0)), + DUMP_WED_RING(WED_RING_RX_DATA(1)), + + DUMP_STR("WED RRO"), + DUMP_WED_RRO_RING(WED_RROQM_MIOD_CTRL0), + DUMP_WED(WED_RROQM_MID_MIB), + DUMP_WED(WED_RROQM_MOD_MIB), + DUMP_WED(WED_RROQM_MOD_COHERENT_MIB), + DUMP_WED_RRO_FDBK(WED_RROQM_FDBK_CTRL0), + DUMP_WED(WED_RROQM_FDBK_IND_MIB), + DUMP_WED(WED_RROQM_FDBK_ENQ_MIB), + DUMP_WED(WED_RROQM_FDBK_ANC_MIB), + DUMP_WED(WED_RROQM_FDBK_ANC2H_MIB), + + DUMP_STR("WED Route QM"), + DUMP_WED(WED_RTQM_R2H_MIB(0)), + DUMP_WED(WED_RTQM_R2Q_MIB(0)), + DUMP_WED(WED_RTQM_Q2H_MIB(0)), + DUMP_WED(WED_RTQM_R2H_MIB(1)), + DUMP_WED(WED_RTQM_R2Q_MIB(1)), + DUMP_WED(WED_RTQM_Q2H_MIB(1)), + DUMP_WED(WED_RTQM_Q2N_MIB), + DUMP_WED(WED_RTQM_Q2B_MIB), + DUMP_WED(WED_RTQM_PFDBK_MIB), + + DUMP_STR("WED WDMA TX"), + DUMP_WED(WED_WDMA_TX_MIB), + DUMP_WED_RING(WED_WDMA_RING_TX), + + DUMP_STR("WDMA TX"), + DUMP_WDMA(WDMA_GLO_CFG), + DUMP_WDMA_RING(WDMA_RING_TX(0)), + DUMP_WDMA_RING(WDMA_RING_TX(1)), + + DUMP_STR("WED RX BM"), + DUMP_WED(WED_RX_BM_BASE), + DUMP_WED(WED_RX_BM_RX_DMAD), + DUMP_WED(WED_RX_BM_PTR), + DUMP_WED(WED_RX_BM_TKID_MIB), + DUMP_WED(WED_RX_BM_BLEN), + DUMP_WED(WED_RX_BM_STS), + DUMP_WED(WED_RX_BM_INTF2), + DUMP_WED(WED_RX_BM_INTF), + DUMP_WED(WED_RX_BM_ERR_STS), + }; + struct mtk_wed_hw *hw = s->private; + struct mtk_wed_device *dev = hw->wed_dev; + + if (!dev) + return 0; + + dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs)); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(wed_rxinfo); static int mtk_wed_reg_set(void *data, u64 val) @@ -175,4 +259,7 @@ void mtk_wed_hw_add_debugfs(struct mtk_wed_hw *hw) debugfs_create_u32("regidx", 0600, dir, &hw->debugfs_reg); debugfs_create_file_unsafe("regval", 0600, dir, hw, &fops_regval); debugfs_create_file_unsafe("txinfo", 0400, dir, hw, &wed_txinfo_fops); + if (hw->version != 1) + debugfs_create_file_unsafe("rxinfo", 0400, dir, hw, + &wed_rxinfo_fops); }