From patchwork Thu Oct 20 10:31:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 616866 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 069A6C433FE for ; Thu, 20 Oct 2022 10:31:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229933AbiJTKbc (ORCPT ); Thu, 20 Oct 2022 06:31:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229992AbiJTKbY (ORCPT ); Thu, 20 Oct 2022 06:31:24 -0400 Received: from mail-lj1-x229.google.com (mail-lj1-x229.google.com [IPv6:2a00:1450:4864:20::229]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B31E05A2FC for ; Thu, 20 Oct 2022 03:31:23 -0700 (PDT) Received: by mail-lj1-x229.google.com with SMTP id i21so22804676ljh.12 for ; Thu, 20 Oct 2022 03:31:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6lkosi1G8fiwOAzxV9MPf8p6ZfuhJ8Ws+fSLTcn2Ll0=; b=cTy8wXVvzrpTrxRXAnAK8Yc16JmTJNsRsKc9xjmOvmAQ3Ctol1uUBWBnW78+s4ro2E GRlZEx5e+Rk4kA4ogHxoUuVs42goH27dYfqyxqQXl3jPBbsKL5+sroiz+auTQ9ggitsK lnyRaTZik8Wi+2jGrTpHs5Cq6+bTz0m50C3MbOzhtszTYcUKwa5P+IBTBsCTZUqMfzkS EXe6ycttqJSFyWQD2jG42ryCE9Ng/Qj2NMUuwIDQnMhzLPOSSVJKD62uF0TlNtuTxqT+ TtzVMB/Qkpu/vFiEJzvwZe6FYJTFKVbRTxI/h5+fP9A5XbR/b2xWDyvJDzlXL2tSijW7 DwAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6lkosi1G8fiwOAzxV9MPf8p6ZfuhJ8Ws+fSLTcn2Ll0=; b=PBG1JLWVuvjIQbNp7rjsOvsb35s+LEiwkm5r63NpuOtX0Wnp9ADzj5GH2nDJI1GPQY ECAHeziEM5qgwwvC06P/U4H/DoWtIo/eY7KwOHP+ZjehIHDWATX+V5/XkDhiQ/PfAhaj 3Er90IW0/ghAW6kq8b0LttAmf4+jigtiUn7doMuOYwTeOiJ6TW0oHMYOxTh5WXjKrYcR TYUMIR9MnqDiKMH547Gxx9cyKcl4Vlp+qMvwR/dtnUdPel83+Y0HVwpc6zYUunamejT5 lqgrrIXPB0kta6PoiDQK180KNDd9VHH58xmpSsWjLRBewrp30BlWcUBa0LrECar5vZsq Tuhg== X-Gm-Message-State: ACrzQf2gQ31XXgcPlxYQrmrq2sunCaklhmKSFTzfKcQ85tCTvvz4CLjh mBA+ndfTRaW9ZTNgmQYOYr+bWLt/NAj9cA== X-Google-Smtp-Source: AMsMyM6/orQWde4hd0X2/yba//8yJqaLyXF6qQMtSWiPdoU3Z/FrNZCeNqV2lF8ne0cGlhHCpSsj9g== X-Received: by 2002:a2e:834b:0:b0:26d:ffb1:dae7 with SMTP id l11-20020a2e834b000000b0026dffb1dae7mr4574079ljh.128.1666261882067; Thu, 20 Oct 2022 03:31:22 -0700 (PDT) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id l2-20020a2e3e02000000b0026be1de1500sm2829019lja.79.2022.10.20.03.31.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 03:31:21 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, Johan Hovold Subject: [PATCH 1/4] PCI: qcom: Move 2_1_0 defines close to the struct definition Date: Thu, 20 Oct 2022 13:31:17 +0300 Message-Id: <20221020103120.1541862-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020103120.1541862-1-dmitry.baryshkov@linaro.org> References: <20221020103120.1541862-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Move the QCOM_PCIE_2_1_0_MAX_* just before the struct qcom_pcie_resources_2_1_0 to follow the example of other structs. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index f711acacaeaf..939f19241356 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -117,11 +117,10 @@ #define DEVICE_TYPE_RC 0x4 -#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 -#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 - #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) +#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 +#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 struct qcom_pcie_resources_2_1_0 { struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS]; struct reset_control *pci_reset; From patchwork Thu Oct 20 10:31:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 618329 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B0860C43217 for ; Thu, 20 Oct 2022 10:31:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229992AbiJTKbc (ORCPT ); Thu, 20 Oct 2022 06:31:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41992 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230161AbiJTKb0 (ORCPT ); Thu, 20 Oct 2022 06:31:26 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3ABC106922 for ; Thu, 20 Oct 2022 03:31:24 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id bp15so32770420lfb.13 for ; Thu, 20 Oct 2022 03:31:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u5BmTwpjRBMqOjFOAsW0IWwVCfl5QyLsy8zHhQXR3YM=; b=v0IV7+00vtmHwXP1s0u1LEplz2dx2rb0YSGSqUyAwib/LqCEDEgITGv9qovXLtqF54 EXucQE3/rnHoBo9bbKr+PItaZuZMQmTdJXr18kQJZz4Vva9hWCBAAxMJwr4nIgVHtegJ vz8Eg7isAC2AuKWiHbnRmyB//TNUPRFVXkVmhNDjjq+0dLAPZ7PmFeTrbTRCh46g2srl 4vSSKvSuShfsCGJ3xQYXdfozrcQ4l5cOkleeA/2r+ji5xQk4IsM/GkSGpzW2uBIYAIOm 1ZHh7Xclz8cw2CaX97MahgD9Tq+71iagKLoyhWlYUobZgtSi4b1zKunHizdYKqftdj1M 59JA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u5BmTwpjRBMqOjFOAsW0IWwVCfl5QyLsy8zHhQXR3YM=; b=u60Q8/wqMX+C9TWOgoD3wwivS1ORKOgXOHBkJH2LIbk0WyM4QU0K2BJw5ifwbJNfpQ /IF/994/8rsVEuRmmnVXavEhIVc6t5zXl3MNcFhXOi6H2Lh44NMi3RepNVRV2ylJuBM4 ZMFK+fshGzhMIRwldzvbUe6/8f/oPDLXvbiom6jacqvB5mwAqI+adV9HVgFbbdFw9syJ 2ml2A+TevqRDG+Tj3zKfvOGwzRkKLmju3Esst3WOX/6rRNgHahXGQ+h3QedXWvs3pkQs vTYnXiSjTBSw92JcufEtaN5kCfwEVXuQpuvPktb1ZFERY4JZWqjQD7OfNfR2OwdWitLK R+Qg== X-Gm-Message-State: ACrzQf1BmCos8Nswm/VUygUyoyQElz93WuKCpOpa/zpNTM6HLuviTH3o /Mhyf/JpQTh5WNgpCtg0jzlKRw== X-Google-Smtp-Source: AMsMyM6yHpG4iAaYCbgn6F8NWMX4mEnM+cRq8ja/E0ftK7uoyWkOaTDleJVjd5v5A5+kSCStZrmYdg== X-Received: by 2002:a05:6512:68b:b0:4a2:5304:bde4 with SMTP id t11-20020a056512068b00b004a25304bde4mr4615616lfe.324.1666261882852; Thu, 20 Oct 2022 03:31:22 -0700 (PDT) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id l2-20020a2e3e02000000b0026be1de1500sm2829019lja.79.2022.10.20.03.31.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 03:31:22 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, Johan Hovold Subject: [PATCH 2/4] PCI: qcom: Use clk_bulk_ API for 1.0.0 clocks handling Date: Thu, 20 Oct 2022 13:31:18 +0300 Message-Id: <20221020103120.1541862-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020103120.1541862-1-dmitry.baryshkov@linaro.org> References: <20221020103120.1541862-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change hand-coded implementation of bulk clocks to use the existing clk_bulk_* API. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 67 ++++++-------------------- 1 file changed, 16 insertions(+), 51 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 939f19241356..74588438db07 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -133,10 +133,7 @@ struct qcom_pcie_resources_2_1_0 { }; struct qcom_pcie_resources_1_0_0 { - struct clk *iface; - struct clk *aux; - struct clk *master_bus; - struct clk *slave_bus; + struct clk_bulk_data clks[4]; struct reset_control *core; struct regulator *vdda; }; @@ -472,26 +469,20 @@ static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; + int ret; res->vdda = devm_regulator_get(dev, "vdda"); if (IS_ERR(res->vdda)) return PTR_ERR(res->vdda); - res->iface = devm_clk_get(dev, "iface"); - if (IS_ERR(res->iface)) - return PTR_ERR(res->iface); - - res->aux = devm_clk_get(dev, "aux"); - if (IS_ERR(res->aux)) - return PTR_ERR(res->aux); - - res->master_bus = devm_clk_get(dev, "master_bus"); - if (IS_ERR(res->master_bus)) - return PTR_ERR(res->master_bus); + res->clks[0].id = "aux"; + res->clks[1].id = "iface"; + res->clks[2].id = "master_bus"; + res->clks[3].id = "slave_bus"; - res->slave_bus = devm_clk_get(dev, "slave_bus"); - if (IS_ERR(res->slave_bus)) - return PTR_ERR(res->slave_bus); + ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + if (ret < 0) + return ret; res->core = devm_reset_control_get_exclusive(dev, "core"); return PTR_ERR_OR_ZERO(res->core); @@ -502,10 +493,7 @@ static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie) struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; reset_control_assert(res->core); - clk_disable_unprepare(res->slave_bus); - clk_disable_unprepare(res->master_bus); - clk_disable_unprepare(res->iface); - clk_disable_unprepare(res->aux); + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); regulator_disable(res->vdda); } @@ -522,45 +510,22 @@ static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie) return ret; } - ret = clk_prepare_enable(res->aux); + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); + dev_err(dev, "cannot prepare/enable clocks\n"); goto err_res; } - ret = clk_prepare_enable(res->iface); - if (ret) { - dev_err(dev, "cannot prepare/enable iface clock\n"); - goto err_aux; - } - - ret = clk_prepare_enable(res->master_bus); - if (ret) { - dev_err(dev, "cannot prepare/enable master_bus clock\n"); - goto err_iface; - } - - ret = clk_prepare_enable(res->slave_bus); - if (ret) { - dev_err(dev, "cannot prepare/enable slave_bus clock\n"); - goto err_master; - } - ret = regulator_enable(res->vdda); if (ret) { dev_err(dev, "cannot enable vdda regulator\n"); - goto err_slave; + goto err_clocks; } return 0; -err_slave: - clk_disable_unprepare(res->slave_bus); -err_master: - clk_disable_unprepare(res->master_bus); -err_iface: - clk_disable_unprepare(res->iface); -err_aux: - clk_disable_unprepare(res->aux); + +err_clocks: + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); err_res: reset_control_assert(res->core); From patchwork Thu Oct 20 10:31:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 616865 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37F15C433FE for ; Thu, 20 Oct 2022 10:31:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230197AbiJTKbh (ORCPT ); Thu, 20 Oct 2022 06:31:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230163AbiJTKb1 (ORCPT ); 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Thu, 20 Oct 2022 03:31:23 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, Johan Hovold Subject: [PATCH 3/4] PCI: qcom: Use clk_bulk_ API for 2.3.2 clocks handling Date: Thu, 20 Oct 2022 13:31:19 +0300 Message-Id: <20221020103120.1541862-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020103120.1541862-1-dmitry.baryshkov@linaro.org> References: <20221020103120.1541862-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change hand-coded implementation of bulk clocks to use the existing clk_bulk_* API. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 68 ++++++-------------------- 1 file changed, 15 insertions(+), 53 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 74588438db07..eee4d2179e90 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -139,11 +139,9 @@ struct qcom_pcie_resources_1_0_0 { }; #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 +#define QCOM_PCIE_2_3_2_MAX_CLOCKS 4 struct qcom_pcie_resources_2_3_2 { - struct clk *aux_clk; - struct clk *master_clk; - struct clk *slave_clk; - struct clk *cfg_clk; + struct clk_bulk_data clks[QCOM_PCIE_2_3_2_MAX_CLOCKS]; struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; }; @@ -571,21 +569,14 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) if (ret) return ret; - res->aux_clk = devm_clk_get(dev, "aux"); - if (IS_ERR(res->aux_clk)) - return PTR_ERR(res->aux_clk); - - res->cfg_clk = devm_clk_get(dev, "cfg"); - if (IS_ERR(res->cfg_clk)) - return PTR_ERR(res->cfg_clk); - - res->master_clk = devm_clk_get(dev, "bus_master"); - if (IS_ERR(res->master_clk)) - return PTR_ERR(res->master_clk); + res->clks[0].id = "aux"; + res->clks[1].id = "cfg"; + res->clks[2].id = "master"; + res->clks[3].id = "slave"; - res->slave_clk = devm_clk_get(dev, "bus_slave"); - if (IS_ERR(res->slave_clk)) - return PTR_ERR(res->slave_clk); + ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + if (ret < 0) + return ret; return 0; } @@ -594,11 +585,7 @@ static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; - clk_disable_unprepare(res->slave_clk); - clk_disable_unprepare(res->master_clk); - clk_disable_unprepare(res->cfg_clk); - clk_disable_unprepare(res->aux_clk); - + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } @@ -615,40 +602,15 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) return ret; } - ret = clk_prepare_enable(res->aux_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); - goto err_aux_clk; - } - - ret = clk_prepare_enable(res->cfg_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable cfg clock\n"); - goto err_cfg_clk; - } - - ret = clk_prepare_enable(res->master_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable master clock\n"); - goto err_master_clk; - } - - ret = clk_prepare_enable(res->slave_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable slave clock\n"); - goto err_slave_clk; + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + if (ret < 0) { + dev_err(dev, "cannot prepare/enable clocks\n"); + goto err_clks; } return 0; -err_slave_clk: - clk_disable_unprepare(res->master_clk); -err_master_clk: - clk_disable_unprepare(res->cfg_clk); -err_cfg_clk: - clk_disable_unprepare(res->aux_clk); - -err_aux_clk: +err_clks: regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); return ret; From patchwork Thu Oct 20 10:31:20 2022 Content-Type: text/plain; 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Thu, 20 Oct 2022 03:31:24 -0700 (PDT) Received: from eriador.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id l2-20020a2e3e02000000b0026be1de1500sm2829019lja.79.2022.10.20.03.31.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Oct 2022 03:31:23 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy?= =?utf-8?q?=C5=84ski?= , Bjorn Helgaas Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, Johan Hovold Subject: [PATCH 4/4] PCI: qcom: Use clk_bulk_ API for 2.3.3 clocks handling Date: Thu, 20 Oct 2022 13:31:20 +0300 Message-Id: <20221020103120.1541862-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221020103120.1541862-1-dmitry.baryshkov@linaro.org> References: <20221020103120.1541862-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Change hand-coded implementation of bulk clocks to use the existing clk_bulk_* API. Signed-off-by: Dmitry Baryshkov --- drivers/pci/controller/dwc/pcie-qcom.c | 90 ++++---------------------- 1 file changed, 12 insertions(+), 78 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index eee4d2179e90..e64e504e531e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -164,11 +164,7 @@ struct qcom_pcie_resources_2_4_0 { }; struct qcom_pcie_resources_2_3_3 { - struct clk *iface; - struct clk *axi_m_clk; - struct clk *axi_s_clk; - struct clk *ahb_clk; - struct clk *aux_clk; + struct clk_bulk_data clks[5]; struct reset_control *rst[7]; }; @@ -929,29 +925,19 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) struct dw_pcie *pci = pcie->pci; struct device *dev = pci->dev; int i; + int ret; const char *rst_names[] = { "axi_m", "axi_s", "pipe", "axi_m_sticky", "sticky", "ahb", "sleep", }; - res->iface = devm_clk_get(dev, "iface"); - if (IS_ERR(res->iface)) - return PTR_ERR(res->iface); - - res->axi_m_clk = devm_clk_get(dev, "axi_m"); - if (IS_ERR(res->axi_m_clk)) - return PTR_ERR(res->axi_m_clk); - - res->axi_s_clk = devm_clk_get(dev, "axi_s"); - if (IS_ERR(res->axi_s_clk)) - return PTR_ERR(res->axi_s_clk); - - res->ahb_clk = devm_clk_get(dev, "ahb"); - if (IS_ERR(res->ahb_clk)) - return PTR_ERR(res->ahb_clk); - - res->aux_clk = devm_clk_get(dev, "aux"); - if (IS_ERR(res->aux_clk)) - return PTR_ERR(res->aux_clk); + res->clks[0].id = "iface"; + res->clks[1].id = "axi_m"; + res->clks[2].id = "axi_s"; + res->clks[3].id = "ahb"; + res->clks[4].id = "aux"; + ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks); + if (ret < 0) + return ret; for (i = 0; i < ARRAY_SIZE(rst_names); i++) { res->rst[i] = devm_reset_control_get(dev, rst_names[i]); @@ -966,11 +952,7 @@ static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; - clk_disable_unprepare(res->iface); - clk_disable_unprepare(res->axi_m_clk); - clk_disable_unprepare(res->axi_s_clk); - clk_disable_unprepare(res->ahb_clk); - clk_disable_unprepare(res->aux_clk); + clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks); } static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) @@ -1005,55 +987,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) */ usleep_range(2000, 2500); - ret = clk_prepare_enable(res->iface); - if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_iface; - } - - ret = clk_prepare_enable(res->axi_m_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable core clock\n"); - goto err_clk_axi_m; - } - - ret = clk_prepare_enable(res->axi_s_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable axi slave clock\n"); - goto err_clk_axi_s; - } - - ret = clk_prepare_enable(res->ahb_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable ahb clock\n"); - goto err_clk_ahb; - } - - ret = clk_prepare_enable(res->aux_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); - goto err_clk_aux; - } - - return 0; - -err_clk_aux: - clk_disable_unprepare(res->ahb_clk); -err_clk_ahb: - clk_disable_unprepare(res->axi_s_clk); -err_clk_axi_s: - clk_disable_unprepare(res->axi_m_clk); -err_clk_axi_m: - clk_disable_unprepare(res->iface); -err_clk_iface: - /* - * Not checking for failure, will anyway return - * the original failure in 'ret'. - */ - for (i = 0; i < ARRAY_SIZE(res->rst); i++) - reset_control_assert(res->rst[i]); - - return ret; + return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); } static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)