From patchwork Tue Oct 18 15:57:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 616112 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DAAAC43217 for ; Tue, 18 Oct 2022 15:58:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229635AbiJRP6P (ORCPT ); Tue, 18 Oct 2022 11:58:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230199AbiJRP6O (ORCPT ); Tue, 18 Oct 2022 11:58:14 -0400 Received: from mail-qv1-xf33.google.com (mail-qv1-xf33.google.com [IPv6:2607:f8b0:4864:20::f33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1FDDEA5711 for ; Tue, 18 Oct 2022 08:58:13 -0700 (PDT) Received: by mail-qv1-xf33.google.com with SMTP id i9so9598907qvo.0 for ; Tue, 18 Oct 2022 08:58:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=nyrr1GKzUYIMpFWVlAheSVsl7aNNeygDeG3I9WF4lxY=; b=HEQBGXL7dZIu1ypps03BHEFpnE3PMF6f7sCEGxqrsj4hBZB3QlXL4XXho/NizfuHiq iXe14RFrIKecLdMOvjJ1Kp5zat267X23gGqMyhoNICV2vEugbXM+rzWMNyOTIEMA5pf7 v9E3av2l854Fh2/kmRMmjDBR3jH0hpflHvVT2MnztQuCtEVJaxZZieIzGIi5msk7KJ7U 99g6pVluhm/Q9Q7xOZxddAaggS7ZN+JL7XsvIIorr21HYo0jNAs39S4Fz8H7KX9g70Cf AE5jHXcH8F2eAmX2btUxqSNSs0Ib6YQ4pI7hQyLhl/4mUkgEheByeaWQTDKMXOdBRrKl PmFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=nyrr1GKzUYIMpFWVlAheSVsl7aNNeygDeG3I9WF4lxY=; b=f119R3BJsS1MAwXFI6VFrSRcTJO1r0UfiZkRVKpkES7zm37EgxvxO1rjgtE2iEjlDG Lp41Z9S/JwTMxa2OTnI6c5leBQ2Ozy7ZBm8TRcue+UY1IJ1zfLVIAbGsSAg4TzBuQV2g wMiDKrkAhIm+eL9yhf4cO6ErkXNeYiPN0L6/vt3HLScaIcnEmOUtfujXH0xvj6QLeN0a pzlotnXtqquTF8q1ucrlDliNgTqC+u29iKtWmX58boLyaAk6gTKbB6RxxV5HHj0O9DuK h9pLqEmH6ESn+oUWNadr8ccop1yuv8cX/Z442aCn6TTe01mO6zSG/8LDeokXx5yiM2dL YWCw== X-Gm-Message-State: ACrzQf24vZwaUUiAqli3X5lTBqsIT+kntT7gmcZxbKPs4XVl9r3wop+S +YPKVoS5y04faWaoR5xgX57XDw== X-Google-Smtp-Source: AMsMyM7kMnKXk90f9GxW+pS49t8OkZJXmVtkcvIe4Spj10MeHPBJy/kf/L+PLhlAQNMAFho8TVz4bQ== X-Received: by 2002:a05:6214:240a:b0:4b1:cb3e:d49c with SMTP id fv10-20020a056214240a00b004b1cb3ed49cmr2782692qvb.39.1666108692280; Tue, 18 Oct 2022 08:58:12 -0700 (PDT) Received: from krzk-bin.MSRM (pool-72-83-177-149.washdc.east.verizon.net. [72.83.177.149]) by smtp.gmail.com with ESMTPSA id de38-20020a05620a372600b006ce30a5f892sm2721448qkb.102.2022.10.18.08.58.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Oct 2022 08:58:11 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v3 1/3] arm64: dts: qcom: msm8996-sony-xperia-tone: drop incorrect wlan pin input Date: Tue, 18 Oct 2022 11:57:19 -0400 Message-Id: <20221018155721.47140-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Pin configuration has no "input-high" property, so drop it from node described as Wifi host wake up pin. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- Changes since v2: 1. None Changes since v1: 1. Add Rb tag. --- arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index ca7c8d2e1d3d..93568fb4bc86 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -912,7 +912,6 @@ wl_host_wake: wl-host-wake { function = "gpio"; drive-strength = <2>; bias-pull-down; - input-high; }; wl_reg_on: wl-reg-on { From patchwork Tue Oct 18 15:57:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 616111 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D544EC43219 for ; Tue, 18 Oct 2022 15:58:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231253AbiJRP60 (ORCPT ); Tue, 18 Oct 2022 11:58:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52768 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231202AbiJRP6Y (ORCPT ); Tue, 18 Oct 2022 11:58:24 -0400 Received: from mail-qt1-x836.google.com (mail-qt1-x836.google.com [IPv6:2607:f8b0:4864:20::836]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24326C14A2 for ; Tue, 18 Oct 2022 08:58:21 -0700 (PDT) Received: by mail-qt1-x836.google.com with SMTP id c23so9918999qtw.8 for ; Tue, 18 Oct 2022 08:58:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mXLUh6pa/VInn9mwcpcYb8Q/C2ecI2W0Bi6jSdtbr1w=; b=bK99z7s3ERwc55FjB+ukbok2LE63npCwOCd9nR9FdAcBg+IWZ0hQTTac+CbzGX4HVf LgufoH12pTSJlyXsqt2XjmHWxkpLlh0NgyF1XEnB7gJp1ge2YPAI9Dx9jx6YZ4VVKUjs J38XOah7BiE9YpRNyE2POGXpW8OEbIYn7xP3xcEAihQFhkSSjhT1dlPd11z/gEPE+vqK Ny0dJ9W13tZPcpJRyA9BKsNwwf2JYTFc7bHebaFG/qrR8YyCFfF4tdVlTwWxgEVf05g6 GleVOUL6B1xSo7JAQwYjnBTX6g9qLcCZAxTONcPUeu1rF9Ct2eJGxdYtHuMiXhydjJ5o N5Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mXLUh6pa/VInn9mwcpcYb8Q/C2ecI2W0Bi6jSdtbr1w=; b=o0+gcy1PJgrdnWj1LFl1waTnMbM8U52puikEmErvcAbu0op+iH2dRZMTClJn/TYO03 YeLAg8sKNq82dBK5Y/uzGJ3UD0m/8h+fvoIKSEJH6rlJgU6yvzA94H/1F28j7U63pfCK ZFOIpwulTzcG62J7Ft6t9qIMfeJUzXU6FoiihLmtbqPr9BDtI49tYOcLwd+fl4JMLcrM hMJ2wngkcPtyHhP7UayNvomVZrlnxhfbZK68QNUuaHgEuzAjfkPrzTt9hRQO7LPDWiXL rwrh7mE55+9lUlCzBnO5KKCnsy7MhKQxQq11eXi2ZljvdoRnKrSDbN9Q1zt+ue9wMth7 DVDw== X-Gm-Message-State: ACrzQf3rdGUe6oWnfXnrwwNjK60q3M/+Lb8vfbfawn1g40XbJvIk8PkK k6EQ9KL/TfPV3gnOc90tzRgwRA== X-Google-Smtp-Source: AMsMyM4NX1Ks6A4p4tDa8J3Nq8hfnBBvToQuBi+FpRKUZPTGpWrO/uMOi/CapYLlqS72aWlkpWfUhw== X-Received: by 2002:a05:622a:283:b0:39c:d772:7e02 with SMTP id z3-20020a05622a028300b0039cd7727e02mr2627266qtw.369.1666108700020; Tue, 18 Oct 2022 08:58:20 -0700 (PDT) Received: from krzk-bin.MSRM (pool-72-83-177-149.washdc.east.verizon.net. [72.83.177.149]) by smtp.gmail.com with ESMTPSA id de38-20020a05620a372600b006ce30a5f892sm2721448qkb.102.2022.10.18.08.58.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Oct 2022 08:58:19 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v3 2/3] arm64: dts: qcom: msm8996: align TLMM pin configuration with DT schema Date: Tue, 18 Oct 2022 11:57:20 -0400 Message-Id: <20221018155721.47140-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221018155721.47140-1-krzysztof.kozlowski@linaro.org> References: <20221018155721.47140-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- Changes since v2: 1. None Changes since v1: 1. Add Rb tag. --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 96 ++++------ arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts | 68 ++------ .../dts/qcom/msm8996-sony-xperia-tone.dtsi | 26 +-- .../boot/dts/qcom/msm8996-xiaomi-common.dtsi | 10 +- .../boot/dts/qcom/msm8996-xiaomi-gemini.dts | 8 +- .../boot/dts/qcom/msm8996-xiaomi-natrium.dts | 4 +- .../boot/dts/qcom/msm8996-xiaomi-scorpio.dts | 8 +- arch/arm64/boot/dts/qcom/msm8996.dtsi | 164 +++++++++--------- 8 files changed, 153 insertions(+), 231 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index 5cdc7ac1a9c0..a3d1ff1aba8f 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -422,82 +422,46 @@ &tlmm { "NC", /* GPIO_148 */ "NC"; /* GPIO_149 */ - sdc2_cd_on: sdc2_cd_on { - mux { - pins = "gpio38"; - function = "gpio"; - }; - - config { - pins = "gpio38"; - bias-pull-up; /* pull up */ - drive-strength = <16>; /* 16 MA */ - }; + sdc2_cd_on: sdc2-cd-on-state { + pins = "gpio38"; + function = "gpio"; + bias-pull-up; + drive-strength = <16>; }; - sdc2_cd_off: sdc2_cd_off { - mux { - pins = "gpio38"; - function = "gpio"; - }; - - config { - pins = "gpio38"; - bias-pull-up; /* pull up */ - drive-strength = <2>; /* 2 MA */ - }; + sdc2_cd_off: sdc2-cd-off-state { + pins = "gpio38"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; }; - hdmi_hpd_active: hdmi_hpd_active { - mux { - pins = "gpio34"; - function = "hdmi_hot"; - }; - - config { - pins = "gpio34"; - bias-pull-down; - drive-strength = <16>; - }; + hdmi_hpd_active: hdmi-hpd-active-state { + pins = "gpio34"; + function = "hdmi_hot"; + bias-pull-down; + drive-strength = <16>; }; - hdmi_hpd_suspend: hdmi_hpd_suspend { - mux { - pins = "gpio34"; - function = "hdmi_hot"; - }; - - config { - pins = "gpio34"; - bias-pull-down; - drive-strength = <2>; - }; + hdmi_hpd_suspend: hdmi-hpd-suspend-state { + pins = "gpio34"; + function = "hdmi_hot"; + bias-pull-down; + drive-strength = <2>; }; - hdmi_ddc_active: hdmi_ddc_active { - mux { - pins = "gpio32", "gpio33"; - function = "hdmi_ddc"; - }; - - config { - pins = "gpio32", "gpio33"; - drive-strength = <2>; - bias-pull-up; - }; + hdmi_ddc_active: hdmi-ddc-active-state { + pins = "gpio32", "gpio33"; + function = "hdmi_ddc"; + drive-strength = <2>; + bias-pull-up; }; - hdmi_ddc_suspend: hdmi_ddc_suspend { - mux { - pins = "gpio32", "gpio33"; - function = "hdmi_ddc"; - }; - - config { - pins = "gpio32", "gpio33"; - drive-strength = <2>; - bias-pull-down; - }; + hdmi_ddc_suspend: hdmi-ddc-suspend-state { + pins = "gpio32", "gpio33"; + function = "hdmi_ddc"; + drive-strength = <2>; + bias-pull-down; }; }; diff --git a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts index 92f264891d84..943dc362faad 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-ifc6640.dts @@ -104,60 +104,22 @@ &mdss { status = "okay"; }; -&tlmm { - sdc2_pins_default: sdc2-pins-default { - clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <16>; - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <10>; - }; - - data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <10>; - }; +&sdc2_state_on { + cd-pins { + pins = "gpio38"; + function = "gpio"; - cd { - pins = "gpio38"; - function = "gpio"; - - bias-pull-up; - drive-strength = <16>; - }; + bias-pull-up; + drive-strength = <16>; }; +}; - sdc2_pins_sleep: sdc2-pins-sleep { - clk { - pins = "sdc2_clk"; - bias-disable; - drive-strength = <2>; - }; - - cmd { - pins = "sdc2_cmd"; - bias-pull-up; - drive-strength = <2>; - }; - - data { - pins = "sdc2_data"; - bias-pull-up; - drive-strength = <2>; - }; - - cd { - pins = "gpio38"; - function = "gpio"; - bias-pull-up; - drive-strength = <2>; - }; +&sdc2_state_off { + cd-pins { + pins = "gpio38"; + function = "gpio"; + bias-pull-up; + drive-strength = <2>; }; }; @@ -372,10 +334,6 @@ &sdhc2 { vmmc-supply = <&vreg_l21a_2p95>; vqmmc-supply = <&vreg_l13a_2p95>; - - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&sdc2_pins_default>; - pinctrl-1 = <&sdc2_pins_sleep>; }; &ufshc { diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index 93568fb4bc86..c824aa17f3a7 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -847,28 +847,28 @@ &tlmm { pinctrl-0 = <&sw_service_gpio>; pinctrl-names = "default"; - disp_reset_n_gpio: disp-reset-n { + disp_reset_n_gpio: disp-reset-n-state { pins = "gpio8"; function = "gpio"; drive-strength = <2>; bias-disable; }; - mdp_vsync_p_gpio: mdp-vsync-p { + mdp_vsync_p_gpio: mdp-vsync-p-state { pins = "gpio10"; function = "mdp_vsync"; drive-strength = <2>; bias-disable; }; - sw_service_gpio: sw-service-gpio { + sw_service_gpio: sw-service-gpio-state { pins = "gpio16"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; - usb_detect: usb-detect { + usb_detect: usb-detect-state { pins = "gpio25"; function = "gpio"; drive-strength = <2>; @@ -876,7 +876,7 @@ usb_detect: usb-detect { output-high; }; - uim_detect_en: uim-detect-en { + uim_detect_en: uim-detect-en-state { pins = "gpio29"; function = "gpio"; drive-strength = <2>; @@ -884,14 +884,14 @@ uim_detect_en: uim-detect-en { output-high; }; - tray_det_pin: tray-det { + tray_det_pin: tray-det-state { pins = "gpio40"; function = "gpio"; drive-strength = <2>; bias-disable; }; - tp_vddio_en: tp-vddio-en { + tp_vddio_en: tp-vddio-en-state { pins = "gpio50"; function = "gpio"; drive-strength = <2>; @@ -899,7 +899,7 @@ tp_vddio_en: tp-vddio-en { output-high; }; - lcd_vddio_en: lcd-vddio-en { + lcd_vddio_en: lcd-vddio-en-state { pins = "gpio51"; function = "gpio"; drive-strength = <2>; @@ -907,14 +907,14 @@ lcd_vddio_en: lcd-vddio-en { output-low; }; - wl_host_wake: wl-host-wake { + wl_host_wake: wl-host-wake-state { pins = "gpio79"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - wl_reg_on: wl-reg-on { + wl_reg_on: wl-reg-on-state { pins = "gpio84"; function = "gpio"; drive-strength = <2>; @@ -922,20 +922,20 @@ wl_reg_on: wl-reg-on { output-low; }; - ts_reset_n: ts-rst-n { + ts_reset_n: ts-rst-n-state { pins = "gpio89"; function = "gpio"; drive-strength = <2>; }; - touch_int_n: touch-int-n { + touch_int_n: touch-int-n-state { pins = "gpio125"; function = "gpio"; drive-strength = <2>; bias-pull-up; }; - touch_int_sleep: touch-int-sleep { + touch_int_sleep: touch-int-sleep-state { pins = "gpio125"; function = "gpio"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 77819186086a..2ac2dfc22411 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -694,35 +694,35 @@ divclk4_pin_a: divclk4-state { }; &tlmm { - mdss_dsi_default: mdss_dsi_default { + mdss_dsi_default: mdss-dsi-default-state { pins = "gpio8"; function = "gpio"; drive-strength = <8>; bias-disable; }; - mdss_dsi_sleep: mdss_dsi_sleep { + mdss_dsi_sleep: mdss-dsi-sleep-state { pins = "gpio8"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - mdss_te_default: mdss_te_default { + mdss_te_default: mdss-te-default-state { pins = "gpio10"; function = "mdp_vsync"; drive-strength = <2>; bias-pull-down; }; - mdss_te_sleep: mdss_te_sleep { + mdss_te_sleep: mdss-te-sleep-state { pins = "gpio10"; function = "mdp_vsync"; drive-strength = <2>; bias-pull-down; }; - nfc_default: nfc_default { + nfc_default: nfc-default-state { pins = "gpio12", "gpio21"; function = "gpio"; drive-strength = <16>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index 4e5264f4116a..54894ccc9785 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -445,28 +445,28 @@ &tlmm { "RFFE1_DATA", /* GPIO_148 */ "RFFE1_CLK"; /* GPIO_149 */ - touchscreen_default: touchscreen_default { + touchscreen_default: touchscreen-default-state { pins = "gpio89", "gpio125"; function = "gpio"; drive-strength = <10>; bias-pull-up; }; - touchscreen_sleep: touchscreen_sleep { + touchscreen_sleep: touchscreen-sleep-state { pins = "gpio89", "gpio125"; function = "gpio"; drive-strength = <2>; bias-disable; }; - vibrator_default: vibrator_default { + vibrator_default: vibrator-default-state { pins = "gpio93"; function = "gpio"; drive-strength = <8>; bias-pull-up; }; - vibrator_sleep: vibrator_sleep { + vibrator_sleep: vibrator-sleep-state { pins = "gpio93"; function = "gpio"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts index ff4673ee9e81..44b137f3cfe7 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-natrium.dts @@ -398,14 +398,14 @@ &tlmm { "RFFE1_DATA", /* GPIO_148 */ "RFFE1_CLK"; /* GPIO_149 */ - touchscreen_default: touchscreen-default { + touchscreen_default: touchscreen-default-state { pins = "gpio89", "gpio125"; function = "gpio"; drive-strength = <10>; bias-pull-up; }; - touchscreen_sleep: touchscreen-sleep { + touchscreen_sleep: touchscreen-sleep-state { pins = "gpio89", "gpio125"; function = "gpio"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts index 79be5fb1295b..75200ba4c5b4 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts @@ -468,28 +468,28 @@ &tlmm { "RFFE1_DATA", /* GPIO_148 */ "RFFE1_CLK"; /* GPIO_149 */ - touchkey_default: touchkey_default { + touchkey_default: touchkey-default-state { pins = "gpio77"; function = "gpio"; drive-strength = <16>; bias-pull-up; }; - touchkey_sleep: touchkey_sleep { + touchkey_sleep: touchkey-sleep-state { pins = "gpio77"; function = "gpio"; drive-strength = <2>; bias-disable; }; - touchscreen_default: touchscreen_default { + touchscreen_default: touchscreen-default-state { pins = "gpio75", "gpio125"; function = "gpio"; drive-strength = <10>; bias-pull-up; }; - touchscreen_sleep: touchscreen_sleep { + touchscreen_sleep: touchscreen-sleep-state { pins = "gpio75", "gpio125"; function = "gpio"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index c0a2baffa49d..3d98cdfc317e 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1262,15 +1262,15 @@ tlmm: pinctrl@1010000 { interrupt-controller; #interrupt-cells = <2>; - blsp1_spi1_default: blsp1-spi1-default { - spi { + blsp1_spi1_default: blsp1-spi1-default-state { + spi-pins { pins = "gpio0", "gpio1", "gpio3"; function = "blsp_spi1"; drive-strength = <12>; bias-disable; }; - cs { + cs-pins { pins = "gpio2"; function = "gpio"; drive-strength = <16>; @@ -1279,42 +1279,42 @@ cs { }; }; - blsp1_spi1_sleep: blsp1-spi1-sleep { + blsp1_spi1_sleep: blsp1-spi1-sleep-state { pins = "gpio0", "gpio1", "gpio2", "gpio3"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - blsp2_uart2_2pins_default: blsp2-uart1-2pins { + blsp2_uart2_2pins_default: blsp2-uart1-2pins-state { pins = "gpio4", "gpio5"; function = "blsp_uart8"; drive-strength = <16>; bias-disable; }; - blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep { + blsp2_uart2_2pins_sleep: blsp2-uart1-2pins-sleep-state { pins = "gpio4", "gpio5"; function = "gpio"; drive-strength = <2>; bias-disable; }; - blsp2_i2c2_default: blsp2-i2c2 { + blsp2_i2c2_default: blsp2-i2c2-state { pins = "gpio6", "gpio7"; function = "blsp_i2c8"; drive-strength = <16>; bias-disable; }; - blsp2_i2c2_sleep: blsp2-i2c2-sleep { + blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { pins = "gpio6", "gpio7"; function = "gpio"; drive-strength = <2>; bias-disable; }; - cci0_default: cci0-default { + cci0_default: cci0-default-state { pins = "gpio17", "gpio18"; function = "cci_i2c"; drive-strength = <16>; @@ -1322,22 +1322,22 @@ cci0_default: cci0-default { }; camera0_state_on: - camera_rear_default: camera-rear-default { - camera0_mclk: mclk0 { + camera_rear_default: camera-rear-default-state { + camera0_mclk: mclk0-pins { pins = "gpio13"; function = "cam_mclk"; drive-strength = <16>; bias-disable; }; - camera0_rst: rst { + camera0_rst: rst-pins { pins = "gpio25"; function = "gpio"; drive-strength = <16>; bias-disable; }; - camera0_pwdn: pwdn { + camera0_pwdn: pwdn-pins { pins = "gpio26"; function = "gpio"; drive-strength = <16>; @@ -1345,7 +1345,7 @@ camera0_pwdn: pwdn { }; }; - cci1_default: cci1-default { + cci1_default: cci1-default-state { pins = "gpio19", "gpio20"; function = "cci_i2c"; drive-strength = <16>; @@ -1353,22 +1353,22 @@ cci1_default: cci1-default { }; camera1_state_on: - camera_board_default: camera-board-default { - mclk1 { + camera_board_default: camera-board-default-state { + mclk1-pins { pins = "gpio14"; function = "cam_mclk"; drive-strength = <16>; bias-disable; }; - pwdn { + pwdn-pins { pins = "gpio98"; function = "gpio"; drive-strength = <16>; bias-disable; }; - rst { + rst-pins { pins = "gpio104"; function = "gpio"; drive-strength = <16>; @@ -1377,22 +1377,22 @@ rst { }; camera2_state_on: - camera_front_default: camera-front-default { - camera2_mclk: mclk2 { + camera_front_default: camera-front-default-state { + camera2_mclk: mclk2-pins { pins = "gpio15"; function = "cam_mclk"; drive-strength = <16>; bias-disable; }; - camera2_rst: rst { + camera2_rst: rst-pins { pins = "gpio23"; function = "gpio"; drive-strength = <16>; bias-disable; }; - pwdn { + pwdn-pins { pins = "gpio133"; function = "gpio"; drive-strength = <16>; @@ -1400,22 +1400,22 @@ pwdn { }; }; - pcie0_state_on: pcie0-state-on { - perst { + pcie0_state_on: pcie0-state-on-state { + perst-pins { pins = "gpio35"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio36"; function = "pci_e0"; drive-strength = <2>; bias-pull-up; }; - wake { + wake-pins { pins = "gpio37"; function = "gpio"; drive-strength = <2>; @@ -1423,22 +1423,22 @@ wake { }; }; - pcie0_state_off: pcie0-state-off { - perst { + pcie0_state_off: pcie0-state-off-state { + perst-pins { pins = "gpio35"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio36"; function = "gpio"; drive-strength = <2>; bias-disable; }; - wake { + wake-pins { pins = "gpio37"; function = "gpio"; drive-strength = <2>; @@ -1446,63 +1446,63 @@ wake { }; }; - blsp1_uart2_default: blsp1-uart2-default { + blsp1_uart2_default: blsp1-uart2-default-state { pins = "gpio41", "gpio42", "gpio43", "gpio44"; function = "blsp_uart2"; drive-strength = <16>; bias-disable; }; - blsp1_uart2_sleep: blsp1-uart2-sleep { + blsp1_uart2_sleep: blsp1-uart2-sleep-state { pins = "gpio41", "gpio42", "gpio43", "gpio44"; function = "gpio"; drive-strength = <2>; bias-disable; }; - blsp1_i2c3_default: blsp1-i2c2-default { + blsp1_i2c3_default: blsp1-i2c2-default-state { pins = "gpio47", "gpio48"; function = "blsp_i2c3"; drive-strength = <16>; bias-disable; }; - blsp1_i2c3_sleep: blsp1-i2c2-sleep { + blsp1_i2c3_sleep: blsp1-i2c2-sleep-state { pins = "gpio47", "gpio48"; function = "gpio"; drive-strength = <2>; bias-disable; }; - blsp2_uart3_4pins_default: blsp2-uart2-4pins { + blsp2_uart3_4pins_default: blsp2-uart2-4pins-state { pins = "gpio49", "gpio50", "gpio51", "gpio52"; function = "blsp_uart9"; drive-strength = <16>; bias-disable; }; - blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep { + blsp2_uart3_4pins_sleep: blsp2-uart2-4pins-sleep-state { pins = "gpio49", "gpio50", "gpio51", "gpio52"; function = "blsp_uart9"; drive-strength = <2>; bias-disable; }; - blsp2_i2c3_default: blsp2-i2c3 { + blsp2_i2c3_default: blsp2-i2c3-state-state { pins = "gpio51", "gpio52"; function = "blsp_i2c9"; drive-strength = <16>; bias-disable; }; - blsp2_i2c3_sleep: blsp2-i2c3-sleep { + blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { pins = "gpio51", "gpio52"; function = "gpio"; drive-strength = <2>; bias-disable; }; - wcd_intr_default: wcd-intr-default{ + wcd_intr_default: wcd-intr-default-state { pins = "gpio54"; function = "gpio"; drive-strength = <2>; @@ -1510,21 +1510,21 @@ wcd_intr_default: wcd-intr-default{ input-enable; }; - blsp2_i2c1_default: blsp2-i2c1 { + blsp2_i2c1_default: blsp2-i2c1-state { pins = "gpio55", "gpio56"; function = "blsp_i2c7"; drive-strength = <16>; bias-disable; }; - blsp2_i2c1_sleep: blsp2-i2c0-sleep { + blsp2_i2c1_sleep: blsp2-i2c0-sleep-state { pins = "gpio55", "gpio56"; function = "gpio"; drive-strength = <2>; bias-disable; }; - blsp2_i2c5_default: blsp2-i2c5 { + blsp2_i2c5_default: blsp2-i2c5-state { pins = "gpio60", "gpio61"; function = "blsp_i2c11"; drive-strength = <2>; @@ -1533,7 +1533,7 @@ blsp2_i2c5_default: blsp2-i2c5 { /* Sleep state for BLSP2_I2C5 is missing.. */ - cdc_reset_active: cdc-reset-active { + cdc_reset_active: cdc-reset-active-state { pins = "gpio64"; function = "gpio"; drive-strength = <16>; @@ -1541,7 +1541,7 @@ cdc_reset_active: cdc-reset-active { output-high; }; - cdc_reset_sleep: cdc-reset-sleep { + cdc_reset_sleep: cdc-reset-sleep-state { pins = "gpio64"; function = "gpio"; drive-strength = <16>; @@ -1549,15 +1549,15 @@ cdc_reset_sleep: cdc-reset-sleep { output-low; }; - blsp2_spi6_default: blsp2-spi5-default { - spi { + blsp2_spi6_default: blsp2-spi5-default-state { + spi-pins { pins = "gpio85", "gpio86", "gpio88"; function = "blsp_spi12"; drive-strength = <12>; bias-disable; }; - cs { + cs-pins { pins = "gpio87"; function = "gpio"; drive-strength = <16>; @@ -1566,43 +1566,43 @@ cs { }; }; - blsp2_spi6_sleep: blsp2-spi5-sleep { + blsp2_spi6_sleep: blsp2-spi5-sleep-state { pins = "gpio85", "gpio86", "gpio87", "gpio88"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - blsp2_i2c6_default: blsp2-i2c6 { + blsp2_i2c6_default: blsp2-i2c6-state { pins = "gpio87", "gpio88"; function = "blsp_i2c12"; drive-strength = <16>; bias-disable; }; - blsp2_i2c6_sleep: blsp2-i2c6-sleep { + blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { pins = "gpio87", "gpio88"; function = "gpio"; drive-strength = <2>; bias-disable; }; - pcie1_state_on: pcie1-state-on { - perst { + pcie1_state_on: pcie1-on-state { + perst-pins { pins = "gpio130"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio131"; function = "pci_e1"; drive-strength = <2>; bias-pull-up; }; - wake { + wake-pins { pins = "gpio132"; function = "gpio"; drive-strength = <2>; @@ -1610,16 +1610,16 @@ wake { }; }; - pcie1_state_off: pcie1-state-off { + pcie1_state_off: pcie1-off-state { /* Perst is missing? */ - clkreq { + clkreq-pins { pins = "gpio131"; function = "gpio"; drive-strength = <2>; bias-disable; }; - wake { + wake-pins { pins = "gpio132"; function = "gpio"; drive-strength = <2>; @@ -1627,22 +1627,22 @@ wake { }; }; - pcie2_state_on: pcie2-state-on { - perst { + pcie2_state_on: pcie2-on-state { + perst-pins { pins = "gpio114"; function = "gpio"; drive-strength = <2>; bias-pull-down; }; - clkreq { + clkreq-pins { pins = "gpio115"; function = "pci_e2"; drive-strength = <2>; bias-pull-up; }; - wake { + wake-pins { pins = "gpio116"; function = "gpio"; drive-strength = <2>; @@ -1650,16 +1650,16 @@ wake { }; }; - pcie2_state_off: pcie2-state-off { + pcie2_state_off: pcie2-off-state { /* Perst is missing? */ - clkreq { + clkreq-pins { pins = "gpio115"; function = "gpio"; drive-strength = <2>; bias-disable; }; - wake { + wake-pins { pins = "gpio116"; function = "gpio"; drive-strength = <2>; @@ -1667,90 +1667,90 @@ wake { }; }; - sdc1_state_on: sdc1-state-on { - clk { + sdc1_state_on: sdc1-on-state { + clk-pins { pins = "sdc1_clk"; bias-disable; drive-strength = <16>; }; - cmd { + cmd-pins { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <10>; }; - data { + data-pins { pins = "sdc1_data"; bias-pull-up; drive-strength = <10>; }; - rclk { + rclk-pins { pins = "sdc1_rclk"; bias-pull-down; }; }; - sdc1_state_off: sdc1-state-off { - clk { + sdc1_state_off: sdc1-off-state { + clk-pins { pins = "sdc1_clk"; bias-disable; drive-strength = <2>; }; - cmd { + cmd-pins { pins = "sdc1_cmd"; bias-pull-up; drive-strength = <2>; }; - data { + data-pins { pins = "sdc1_data"; bias-pull-up; drive-strength = <2>; }; - rclk { + rclk-pins { pins = "sdc1_rclk"; bias-pull-down; }; }; - sdc2_state_on: sdc2-clk-on { - clk { + sdc2_state_on: sdc2-on-state { + clk-pins { pins = "sdc2_clk"; bias-disable; drive-strength = <16>; }; - cmd { + cmd-pins { pins = "sdc2_cmd"; bias-pull-up; drive-strength = <10>; }; - data { + data-pins { pins = "sdc2_data"; bias-pull-up; drive-strength = <10>; }; }; - sdc2_state_off: sdc2-clk-off { - clk { + sdc2_state_off: sdc2-off-state { + clk-pins { pins = "sdc2_clk"; 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[72.83.177.149]) by smtp.gmail.com with ESMTPSA id do20-20020a05620a2b1400b006ec9f5e3396sm2694658qkb.72.2022.10.18.08.55.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Oct 2022 08:55:12 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski , Rob Herring Subject: [PATCH v3 3/3] dt-bindings: pinctrl: qcom,msm8994: convert to dtschema Date: Tue, 18 Oct 2022 11:54:50 -0400 Message-Id: <20221018155450.39816-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221018155450.39816-1-krzysztof.kozlowski@linaro.org> References: <20221018155450.39816-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Convert Qualcomm MSM8994 pin controller bindings to DT schema. Keep the parsing of pin configuration subnodes consistent with other Qualcomm schemas (children named with '-state' suffix, their children with '-pins'). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Rob Herring --- Changes since v2: 1. Add Rb tag. 2. Drop entire drive-strength (not needed, brought by common TLMM schema). Changes since v1: 1. Drop default:2 for drive strength --- .../bindings/pinctrl/qcom,msm8994-pinctrl.txt | 186 ------------------ .../pinctrl/qcom,msm8994-pinctrl.yaml | 162 +++++++++++++++ 2 files changed, 162 insertions(+), 186 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt deleted file mode 100644 index da52df6273bc..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.txt +++ /dev/null @@ -1,186 +0,0 @@ -Qualcomm MSM8994 TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -MSM8994 platform. - -- compatible: - Usage: required - Value type: - Definition: Should contain one of: - "qcom,msm8992-pinctrl", - "qcom,msm8994-pinctrl". - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-ranges: - Usage: required - Definition: see ../gpio/gpio.txt - -- gpio-reserved-ranges: - Usage: optional - Definition: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. - - Valid pins are: - gpio0-gpio145 - Supports mux, bias and drive-strength - - sdc1_clk, sdc1_cmd, sdc1_data sdc1_rclk, sdc2_clk, - sdc2_cmd, sdc2_data - Supports bias and drive-strength - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Functions are only valid for gpio pins. - Valid values are: - - audio_ref_clk, blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, - blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_i2c9, blsp_i2c10, blsp_i2c11, - blsp_i2c12, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3, - blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3, - blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9, - blsp_spi10, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3, blsp_spi11, - blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3, blsp_uart4, blsp_uart5, - blsp_uart6, blsp_uart7, blsp_uart8, blsp_uart9, blsp_uart10, blsp_uart11, - blsp_uart12, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5, - blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, blsp_uim11, - blsp_uim12, blsp11_i2c_scl_b, blsp11_i2c_sda_b, blsp11_uart_rx_b, - blsp11_uart_tx_b, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3, - cci_async_in0, cci_async_in1, cci_async_in2, cci_i2c0, cci_i2c1, - cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, - gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a, - gcc_gp3_clk_b, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, - gp1_clk, gps_tx, gsm_tx, hdmi_cec, hdmi_ddc, hdmi_hpd, hdmi_rcv, - mdp_vsync, mss_lte, nav_pps, nav_tsync, qdss_cti_trig_in_a, - qdss_cti_trig_in_b, qdss_cti_trig_in_c, qdss_cti_trig_in_d, - qdss_cti_trig_out_a, qdss_cti_trig_out_b, qdss_cti_trig_out_c, - qdss_cti_trig_out_d, qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, - qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, qua_mi2s, pci_e0, - pci_e1, pri_mi2s, sdc4, sec_mi2s, slimbus, spkr_i2s, ter_mi2s, tsif1, - tsif2, uim_batt_alarm, uim1, uim2, uim3, uim4, gpio - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configured as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - Not valid for sdc pins. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - Not valid for sdc pins. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - msmgpio: pinctrl@fd510000 { - compatible = "qcom,msm8994-pinctrl"; - reg = <0xfd510000 0x4000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&msmgpio 0 0 146>; - interrupt-controller; - #interrupt-cells = <2>; - - blsp1_uart2_default: blsp1_uart2_default { - pinmux { - pins = "gpio4", "gpio5"; - function = "blsp_uart2"; - }; - pinconf { - pins = "gpio4", "gpio5"; - drive-strength = <16>; - bias-disable; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml new file mode 100644 index 000000000000..55d5439c6c24 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8994-pinctrl.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8994-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8994 TLMM pin controller + +maintainers: + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + Top Level Mode Multiplexer pin controller in Qualcomm MSM8994 SoC. + +properties: + compatible: + enum: + - qcom,msm8992-pinctrl + - qcom,msm8994-pinctrl + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + "#gpio-cells": true + gpio-ranges: true + wakeup-parent: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 75 + + gpio-line-names: + maxItems: 150 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-msm8994-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-msm8994-tlmm-state" + additionalProperties: false + +$defs: + qcom-msm8994-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk, + sdc2_cmd, sdc2_data, sdc3_clk, sdc3_cmd, sdc3_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, audio_ref_clk, blsp_i2c1, blsp_i2c2, blsp_i2c3, + blsp_i2c4, blsp_i2c5, blsp_i2c6, blsp_i2c7, blsp_i2c8, + blsp_i2c9, blsp_i2c10, blsp_i2c11, blsp_i2c12, blsp_spi1, + blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3, blsp_spi2, + blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3, + blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8, + blsp_spi9, blsp_spi10, blsp_spi10_cs1, blsp_spi10_cs2, + blsp_spi10_cs3, blsp_spi11, blsp_spi12, blsp_uart1, blsp_uart2, + blsp_uart3, blsp_uart4, blsp_uart5, blsp_uart6, blsp_uart7, + blsp_uart8, blsp_uart9, blsp_uart10, blsp_uart11, blsp_uart12, + blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5, + blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, + blsp_uim11, blsp_uim12, blsp11_i2c_scl_b, blsp11_i2c_sda_b, + blsp11_uart_rx_b, blsp11_uart_tx_b, cam_mclk0, cam_mclk1, + cam_mclk2, cam_mclk3, cci_async_in0, cci_async_in1, + cci_async_in2, cci_i2c0, cci_i2c1, cci_timer0, cci_timer1, + cci_timer2, cci_timer3, cci_timer4, gcc_gp1_clk_a, + gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a, + gcc_gp3_clk_b, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk, + gp1_clk, gps_tx, gsm_tx, hdmi_cec, hdmi_ddc, hdmi_hpd, + hdmi_rcv, mdp_vsync, mss_lte, nav_pps, nav_tsync, + qdss_cti_trig_in_a, qdss_cti_trig_in_b, qdss_cti_trig_in_c, + qdss_cti_trig_in_d, qdss_cti_trig_out_a, qdss_cti_trig_out_b, + qdss_cti_trig_out_c, qdss_cti_trig_out_d, qdss_traceclk_a, + qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, + qdss_tracedata_a, qdss_tracedata_b, qua_mi2s, pci_e0, pci_e1, + pri_mi2s, sdc4, sec_mi2s, slimbus, spkr_i2s, ter_mi2s, tsif1, + tsif2, uim_batt_alarm, uim1, uim2, uim3, uim4 ] + + bias-pull-down: true + bias-pull-up: true + bias-disable: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + additionalProperties: false + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + tlmm: pinctrl@fd510000 { + compatible = "qcom,msm8994-pinctrl"; + reg = <0xfd510000 0x4000>; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 146>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + blsp1-uart2-default-state { + function = "blsp_uart2"; + pins = "gpio4", "gpio5"; + drive-strength = <16>; + bias-disable; + }; + + blsp1-spi1-default-state { + default-pins { + pins = "gpio0", "gpio1", "gpio3"; + function = "blsp_spi1"; + drive-strength = <10>; + bias-pull-down; + }; + + cs-pins { + pins = "gpio8"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; + };