From patchwork Mon Oct 17 10:23:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 615900 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E672C43219 for ; Mon, 17 Oct 2022 10:23:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230008AbiJQKXQ (ORCPT ); Mon, 17 Oct 2022 06:23:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41968 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229900AbiJQKXO (ORCPT ); Mon, 17 Oct 2022 06:23:14 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB99A5FDEF for ; Mon, 17 Oct 2022 03:23:12 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id f11so17719406wrm.6 for ; Mon, 17 Oct 2022 03:23:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0BtCteD54q02kgUkMkj2OAC+PDkYwPzaE7W/pW2qQxs=; b=dAaFQ8MmIj1mfftRn85kI1Q3UM+UcI9CdXnNOaS2QeJCFzWf2UxzefLcCo+UhC3YWL WiAhVTEQC2unmT6AJp663ECO4dkEISWkrz33zUnpLotiJKeUkSOk7lsEmWU/QuF/yc66 Im6qqKpiDh2c58jZp76TnILCsv61o9ifH3xGVs3K78SGQDSN5ZGSRq0KY0R4HyR02xYC QFtPm2gmwr7hPvxr2TMPfwAJcIN1qHSpkGaA4zVuUgq4K0JoAz7uDlyCtYmA2HXgAZSj 5usxkYO2bGWWWj9sRjKFpkKWu2p6Mk1+rS8800SkzzJwcdWimT9pdX2MEW1iiEuYqaOT 9tTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0BtCteD54q02kgUkMkj2OAC+PDkYwPzaE7W/pW2qQxs=; b=ta0LyigwoK6IR03lpAVoKZJhNUCE7EJlm/ZcaiwS6BNaOKt56VO7EFVy6zhsfSMvkY KJKuTD8VVaZYwMSo1VbQU8o3aj7vLm6LPjAmyl0jQ8fEcbZxIC65koqJrlCMLI0iu+cf p788CFrK7tIW8x5U9s9cHcMYCzES+laxUsDlXaT9+bKcqv3RwuzLtkEHHv8w45/Xg4CK s3AsiX8IOHnqyjw0QJ2awMpXE7LSfqc41vSFUEBEBPDps684rTm5IqzrwSvohyhUn1Fo Rm7oCCRpCC4mVjgfJHovz0YF4iAWDYlLL7aYYBt75scLafzqVOVhUH2kWDTMVN5bLV2y awqA== X-Gm-Message-State: ACrzQf3QsuDEngDj1lwiJ2UJVZKbWP3ZhnGo3Yqs4PwjkTDcneqF5+or 5cQh9tfqKyFFn5YNMCm3r48kPA== X-Google-Smtp-Source: AMsMyM5wgwpm9McR2B2qeS/Q6AZZTiAotClK7y2ZgtebZYU5yvFANNlfloXRllnAVKNZFDL37ScBag== X-Received: by 2002:a5d:4150:0:b0:22f:f9f6:cca1 with SMTP id c16-20020a5d4150000000b0022ff9f6cca1mr5974819wrq.510.1666002191072; Mon, 17 Oct 2022 03:23:11 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id t9-20020a05600c198900b003b4fe03c881sm15590707wmq.48.2022.10.17.03.23.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Oct 2022 03:23:10 -0700 (PDT) From: Neil Armstrong Date: Mon, 17 Oct 2022 12:23:05 +0200 Subject: [PATCH v2 1/5] dt-bindings: pinctrl: convert qcom, mdm9615-pinctrl.txt to dt-schema MIME-Version: 1.0 Message-Id: <20221005-mdm9615-pinctrl-yaml-v2-1-639fe67a04be@linaro.org> References: <20221005-mdm9615-pinctrl-yaml-v2-0-639fe67a04be@linaro.org> In-Reply-To: <20221005-mdm9615-pinctrl-yaml-v2-0-639fe67a04be@linaro.org> To: Lee Jones , Krzysztof Kozlowski , Konrad Dybcio , Andy Gross , Mark Brown , Liam Girdwood , Linus Walleij , Rob Herring , Bjorn Andersson Cc: Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, Neil Armstrong , devicetree@vger.kernel.org X-Mailer: b4 0.10.1 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Convert the MDM9515 pinctrl bindings to dt-schema. Keep the parsing of pin configuration subnodes consistent with other Qualcomm schemas (children named with '-state' suffix, optional children with '-pins'). Signed-off-by: Neil Armstrong Reviewed-by: Rob Herring --- .../bindings/pinctrl/qcom,mdm9615-pinctrl.txt | 161 --------------------- .../bindings/pinctrl/qcom,mdm9615-pinctrl.yaml | 120 +++++++++++++++ 2 files changed, 120 insertions(+), 161 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt deleted file mode 100644 index d46973968873..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.txt +++ /dev/null @@ -1,161 +0,0 @@ -Qualcomm MDM9615 TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -MDM9615 platform. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,mdm9615-pinctrl" - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-ranges: - Usage: required - Definition: see ../gpio/gpio.txt - -- gpio-reserved-ranges: - Usage: optional - Definition: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. Valid pins are: - gpio0-gpio87 - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. - Valid values are: - gpio, gsbi2_i2c, gsbi3, gsbi4, gsbi5_i2c, gsbi5_uart, - sdc2, ebi2_lcdc, ps_hold, prim_audio, sec_audio, - cdc_mclk - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configured as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - msmgpio: pinctrl@800000 { - compatible = "qcom,mdm9615-pinctrl"; - reg = <0x800000 0x4000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&msmgpio 0 0 88>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = <0 16 0x4>; - - gsbi8_uart: gsbi8-uart { - mux { - pins = "gpio34", "gpio35"; - function = "gsbi8"; - }; - - tx { - pins = "gpio34"; - drive-strength = <4>; - bias-disable; - }; - - rx { - pins = "gpio35"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml new file mode 100644 index 000000000000..69a8549beef6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,mdm9615-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. MDM9615 TLMM block + +maintainers: + - Bjorn Andersson + +description: Top Level Mode Multiplexer pin controller in Qualcomm MDM9615 SoC. + +$ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,mdm9615-pinctrl + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + '#interrupt-cells': true + gpio-controller: true + '#gpio-cells': true + gpio-ranges: true + +required: + - compatible + - reg + +additionalProperties: false + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-mdm9615-pinctrl-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-mdm9615-pinctrl-state" + additionalProperties: false + +$defs: + qcom-mdm9615-pinctrl-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-7][0-9]|8[0-7])$" + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, gsbi2_i2c, gsbi3, gsbi4, gsbi5_i2c, gsbi5_uart, + sdc2, ebi2_lcdc, ps_hold, prim_audio, sec_audio, cdc_mclk, ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + output-high: true + output-low: true + input-enable: true + + required: + - pins + - function + + additionalProperties: false + +examples: + - | + #include + tlmm: pinctrl@1000000 { + compatible = "qcom,mdm9615-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + gpio-ranges = <&msmgpio 0 0 88>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + + gsbi3-state { + pins = "gpio8", "gpio9", "gpio10", "gpio11"; + function = "gsbi3"; + drive-strength = <8>; + bias-disable; + }; + + gsbi5-i2c-state { + sda-pins { + pins = "gpio16"; + function = "gsbi5_i2c"; + drive-strength = <8>; + bias-disable; + }; + + scl-pins { + pins = "gpio17"; + function = "gsbi5_i2c"; + drive-strength = <2>; + bias-disable; + }; + }; + }; From patchwork Mon Oct 17 10:23:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 615899 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A0B0C43219 for ; Mon, 17 Oct 2022 10:23:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230050AbiJQKXR (ORCPT ); Mon, 17 Oct 2022 06:23:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230022AbiJQKXQ (ORCPT ); Mon, 17 Oct 2022 06:23:16 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D1395FDD1 for ; Mon, 17 Oct 2022 03:23:14 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id n12so17698161wrp.10 for ; Mon, 17 Oct 2022 03:23:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=DpV/qCEWf/oxdA4ww51qfQjnCUWo3HbkpcM9BvV5fno=; b=os1RfSXZtHCkU6GI6uXXkcEXJfLtaPZhkfLfPfmPyIMNVxXNjQy5ta95vojoukfmsC G7KsJEO7XAv1guEoNs582HHYPf5Axn2VB/Nj1ktY5ocPtwwDs35xQfvPw6WoV2Jx1KgC /BKr1Q322PFVBS8X0NgOW3ck8bPt6L5GGiBhpoI2hAIt3vW1g93q+RB3J10ZvK0vALLE cDri5ua3+X1UaRh+Bwvuy/wMRnsfUU9UJAiy9ZUb25ATHLH1aqyYFXv3RFep96rbq6nt TLg9v6E5D00RsriKmySXPT/sR7KWEke9DDTpcBoE59b0eEq8ZRUfQEGsYhD/SX3PgURU Bo/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DpV/qCEWf/oxdA4ww51qfQjnCUWo3HbkpcM9BvV5fno=; b=n0PjcwDengz/G+/7hGQWnlPaqFYYSs+JbSaeEUUtaJdBJ0D0l5fXN+CBh1fpMZ/y5f t0I7YWl/FVdZx8FqW4abSQpMn1u7dGgzCQNAXo3wM+NlgC2SuFP2hhQiZY86/m4UA2ir XoV9uE/yrm51i0Rdr852jtOEnabaqpSWViLf3uXcNnO32J1faN1MWSrCfN5HIqRbxcWL ULRT9UwpMwuzUnPBLXp+QhXoTFPgMVTeicBPiqSOgNU1fKUbkKbOsuHYbdH9JZXbPlYV aMafkGVGQXLw1BgQKxkh0MhumWDUX2Dl3HIcALfauLko7EPmbZe0GTSvCotJDuEx/XMJ V27A== X-Gm-Message-State: ACrzQf1pIYphze5QvS/qLLrpElhi70eVtvfsijcPlNnax1gO2D6v0pyh otORIMoWUesgKssAXfg6wYgiNQ== X-Google-Smtp-Source: AMsMyM6b39tiyV1LOE66pb8hnBuR0GHG0bwPbwGUkCiaGC+vdy4rgkQZqGJMiEQF479pvYc1CmgSxw== X-Received: by 2002:a5d:584a:0:b0:231:636c:de28 with SMTP id i10-20020a5d584a000000b00231636cde28mr5875835wrf.175.1666002193007; Mon, 17 Oct 2022 03:23:13 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id t9-20020a05600c198900b003b4fe03c881sm15590707wmq.48.2022.10.17.03.23.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Oct 2022 03:23:12 -0700 (PDT) From: Neil Armstrong Date: Mon, 17 Oct 2022 12:23:07 +0200 Subject: [PATCH v2 3/5] arm: dts: qcom: mdm9615: wp8548-mangoh-green: fix sx150xq node names and probe-reset property MIME-Version: 1.0 Message-Id: <20221005-mdm9615-pinctrl-yaml-v2-3-639fe67a04be@linaro.org> References: <20221005-mdm9615-pinctrl-yaml-v2-0-639fe67a04be@linaro.org> In-Reply-To: <20221005-mdm9615-pinctrl-yaml-v2-0-639fe67a04be@linaro.org> To: Lee Jones , Krzysztof Kozlowski , Konrad Dybcio , Andy Gross , Mark Brown , Liam Girdwood , Linus Walleij , Rob Herring , Bjorn Andersson Cc: Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, Neil Armstrong , devicetree@vger.kernel.org X-Mailer: b4 0.10.1 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Fix the sx150xq node names to pinctrl and use the right probe-reset property. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts index 30a110984597..a8304769b509 100644 --- a/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts +++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts @@ -116,7 +116,7 @@ i2c@4 { #size-cells = <0>; reg = <4>; - gpioext0: gpio@3e { + gpioext0: pinctrl@3e { /* GPIO Expander 0 Mapping : * - 0: ARDUINO_RESET_Level shift * - 1: BattChrgr_PG_N @@ -142,7 +142,7 @@ gpioext0: gpio@3e { interrupt-parent = <&gpioext1>; interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - probe-reset; + semtech,probe-reset; gpio-controller; interrupt-controller; @@ -154,7 +154,7 @@ i2c@5 { #size-cells = <0>; reg = <5>; - gpioext1: gpio@3f { + gpioext1: pinctrl@3f { /* GPIO Expander 1 Mapping : * - 0: GPIOEXP_INT1 * - 1: Battery detect @@ -183,7 +183,7 @@ gpioext1: gpio@3f { interrupt-parent = <&msmgpio>; interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - probe-reset; + semtech,probe-reset; gpio-controller; interrupt-controller; @@ -195,7 +195,7 @@ i2c@6 { #size-cells = <0>; reg = <6>; - gpioext2: gpio@70 { + gpioext2: pinctrl@70 { /* GPIO Expander 2 Mapping : * - 0: USB_HUB_INTn * - 1: HUB_CONNECT @@ -221,7 +221,7 @@ gpioext2: gpio@70 { interrupt-parent = <&gpioext1>; interrupts = <14 IRQ_TYPE_EDGE_FALLING>; - probe-reset; + semtech,probe-reset; gpio-controller; interrupt-controller; From patchwork Mon Oct 17 10:23:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 615898 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAA78C4321E for ; Mon, 17 Oct 2022 10:23:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230111AbiJQKXU (ORCPT ); Mon, 17 Oct 2022 06:23:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230057AbiJQKXR (ORCPT ); Mon, 17 Oct 2022 06:23:17 -0400 Received: from mail-wr1-x42e.google.com (mail-wr1-x42e.google.com [IPv6:2a00:1450:4864:20::42e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C7FC5FDF3 for ; Mon, 17 Oct 2022 03:23:15 -0700 (PDT) Received: by mail-wr1-x42e.google.com with SMTP id bp11so17722659wrb.9 for ; Mon, 17 Oct 2022 03:23:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=T4vnnNnC74AadFGPIaQilMOOArwGooyURI20oo6pvdI=; b=E7UkAb984yGO2S+TPiMJI8VNnm2hyTRukt0iCsSbfG4/frAjKuMNKkaTWVYhqG22Eo pYd6DhLCyEVYISG8IRmNxxaOk0Zc7Fxdus5A4DZ1UuDas40yDtOLQ9wsTVGgn/BW4bIT aPUQuU6sO8iw1POLSvGTFPe4/8ETooxDRhhBnT4qxK03duAsazPQT5pTKkUcx4EyLdkR 3oY1B8OHUEIBiBYFgcxcAXAg4GvtQhN9htlrFDR9lSTYw/1qdexnMrCnAxqIRTpeM0mm LIh8sGTt8HUxDJnNWkO6u0GDIWTjNu148ul5nKLuKk/1jMhHKJZZlajwD1rbZ8h2NaFf mzrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T4vnnNnC74AadFGPIaQilMOOArwGooyURI20oo6pvdI=; b=llVC/uCjXb448nwe0CMXbxxzw4Wsz3QdlIf6hwcnRv6aoYgmyFFTEtk5GkZDYVWvbV gCIzyVk34xZEclr2+mtvqiEg3GN3ha4F2YDKDZrYU0D57l3DJxXX/ikKQnUNu8s+o7LW bG27S+joNPSPbbN5U6RHXw0WgdxCaiFglj1AIkP3ZAZDatSJnm0J/IqY5sIZUNUhn2ev 0x2MqseOXltrGuTLuWt1n4v031kbbzgYhsTBUoCvcDI7X41Cz/t/rjiQVAzWoXoDLxik Ifnyu8gAnucImqlkdJ9p9/8MJ9lgIEEwebhSpA5wPhTdkrtbVTJM/m/dpuDWyOaz5hz7 XD6Q== X-Gm-Message-State: ACrzQf18JfYADJW1NP6oB2Iu2fuoD1pLhCF1aaq9nJYpvJuXwMvcqSm6 KJDoFAkkpqzQNotNsFMfRHhfmA== X-Google-Smtp-Source: AMsMyM6HU5BuPA3M/bfb/GFmfDnbrmPt9e6BVpjgCq6VWHhs5X5IEOx2PBHwIP5KLLaFMco4dcVrhA== X-Received: by 2002:a05:6000:1d82:b0:22c:ae77:c8dc with SMTP id bk2-20020a0560001d8200b0022cae77c8dcmr6046310wrb.413.1666002193889; Mon, 17 Oct 2022 03:23:13 -0700 (PDT) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id t9-20020a05600c198900b003b4fe03c881sm15590707wmq.48.2022.10.17.03.23.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 Oct 2022 03:23:13 -0700 (PDT) From: Neil Armstrong Date: Mon, 17 Oct 2022 12:23:08 +0200 Subject: [PATCH v2 4/5] dt-bindings: regulators: convert non-smd RPM Regulators bindings to dt-schema MIME-Version: 1.0 Message-Id: <20221005-mdm9615-pinctrl-yaml-v2-4-639fe67a04be@linaro.org> References: <20221005-mdm9615-pinctrl-yaml-v2-0-639fe67a04be@linaro.org> In-Reply-To: <20221005-mdm9615-pinctrl-yaml-v2-0-639fe67a04be@linaro.org> To: Lee Jones , Krzysztof Kozlowski , Konrad Dybcio , Andy Gross , Mark Brown , Liam Girdwood , Linus Walleij , Rob Herring , Bjorn Andersson Cc: Krzysztof Kozlowski , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, Neil Armstrong , devicetree@vger.kernel.org X-Mailer: b4 0.10.1 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Convert the non-SMD Regulators bindings to dt-schema, the old text based bindings will be deleted later since the RPM bindings are not yet converted. Signed-off-by: Neil Armstrong --- .../bindings/regulator/qcom,ipc-rpm-regulator.yaml | 127 +++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/qcom,ipc-rpm-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,ipc-rpm-regulator.yaml new file mode 100644 index 000000000000..e18bb8b87c43 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/qcom,ipc-rpm-regulator.yaml @@ -0,0 +1,127 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/qcom,ipc-rpm-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QCOM IPC RPM REGULATOR + +description: + The Qualcomm RPM over IPC regulator is modelled as a subdevice of the RPM. + + Please refer to Documentation/devicetree/bindings/soc/qcom/qcom,ipc-rpm.yaml + for information regarding the RPM node. + + The regulator node houses sub-nodes for each regulator within the device. + Each sub-node is identified using the node's name, with valid values listed + for each of the pmics below. + + For pm8058 l0, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, + l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, s0, s1, s2, s3, s4, + lvs0, lvs1, ncp + + For pm8901 l0, l1, l2, l3, l4, l5, l6, s0, s1, s2, s3, s4, lvs0, lvs1, lvs2, lvs3, + mvs + + For pm8921 s1, s2, s3, s4, s7, s8, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, + l12, l14, l15, l16, l17, l18, l21, l22, l23, l24, l25, l26, l27, l28, + l29, lvs1, lvs2, lvs3, lvs4, lvs5, lvs6, lvs7, usb-switch, hdmi-switch, + ncp + + For pm8018 s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, + l12, l14, lvs1 + + For smb208 s1a, s1b, s2a, s2b + +maintainers: + - Bjorn Andersson + +properties: + compatible: + enum: + - qcom,rpm-pm8058-regulators + - qcom,rpm-pm8901-regulators + - qcom,rpm-pm8921-regulators + - qcom,rpm-pm8018-regulators + - qcom,rpm-smb208-regulators + +patternProperties: + ".*-supply$": + description: Input supply phandle(s) for this node + + "^((s|l|lvs)[0-9]*)|(s[1-2][a-b])|(ncp)|(mvs)|(usb-switch)|(hdmi-switch)$": + description: List of regulators and its properties + $ref: regulator.yaml# + properties: + bias-pull-down: + description: enable pull down of the regulator when inactive + type: boolean + + qcom,switch-mode-frequency: + description: Frequency (Hz) of the switch-mode power supply + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 19200000 + - 9600000 + - 6400000 + - 4800000 + - 3840000 + - 3200000 + - 2740000 + - 2400000 + - 2130000 + - 1920000 + - 1750000 + - 1600000 + - 1480000 + - 1370000 + - 1280000 + - 1200000 + + qcom,force-mode: + description: Indicates that the regulator should be forced to a particular mode + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # QCOM_RPM_FORCE_MODE_NONE do not force any mode + - 1 # QCOM_RPM_FORCE_MODE_LPM force into low power mode + - 2 # QCOM_RPM_FORCE_MODE_HPM force into high power mode + - 3 # QCOM_RPM_FORCE_MODE_AUTO allow regulator to automatically select its own mode + # based on realtime current draw, only for pm8921 smps and ftsmps + + qcom,power-mode-hysteretic: + description: select that the power supply should operate in hysteretic mode, + instead of the default pwm mode + type: boolean + +additionalProperties: false + +required: + - compatible + +examples: + - | + #include + regulators { + compatible = "qcom,rpm-pm8921-regulators"; + vdd_l1_l2_l12_l18-supply = <&pm8921_s4>; + + s1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + + bias-pull-down; + + qcom,switch-mode-frequency = <3200000>; + }; + + pm8921_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + qcom,switch-mode-frequency = <1600000>; + bias-pull-down; + + qcom,force-mode = ; + }; + }; +...