From patchwork Mon Oct 17 19:25:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 616222 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F3F3C43219 for ; Mon, 17 Oct 2022 19:26:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231211AbiJQT0x (ORCPT ); Mon, 17 Oct 2022 15:26:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231149AbiJQT01 (ORCPT ); Mon, 17 Oct 2022 15:26:27 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8639B7756B; Mon, 17 Oct 2022 12:26:05 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29HJPYxn007817; Mon, 17 Oct 2022 14:25:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666034734; bh=yIqqHgndFLShNCLNh4uSv4KXNiiYiiM5GTjwUcf0SAo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=L1n3ESu//NKM0yKhZ+TSayU30+LK8GSFjaBWROUQCyGEj1MhSZC7+am56mnmvQYXg 39re+ojNd7oawLAJ3tDveXEkn/MZu7UGDSqnt4DuFhHySEr/sdE2+vxJ6IndNCsX/j x6OTvGBMh94+/PWHuILIcPQp6vwWfP7jV+0Rx0BM= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29HJPYOm026073 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 17 Oct 2022 14:25:34 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Mon, 17 Oct 2022 14:25:33 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Mon, 17 Oct 2022 14:25:33 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29HJPWXI026106; Mon, 17 Oct 2022 14:25:33 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , , , CC: Andrew Davis Subject: [PATCH 01/10] arm64: dts: ti: k3-am64: Enable UART nodes at the board level Date: Mon, 17 Oct 2022 14:25:23 -0500 Message-ID: <20221017192532.23825-2-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221017192532.23825-1-afd@ti.com> References: <20221017192532.23825-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org UART nodes defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the UART nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 7 ++++++ arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 29 +----------------------- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 29 +----------------------- 4 files changed, 11 insertions(+), 56 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index d6aa23681bbe..a115c668d001 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -237,6 +237,7 @@ main_uart0: serial@2800000 { power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 146 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart1: serial@2810000 { @@ -248,6 +249,7 @@ main_uart1: serial@2810000 { power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 152 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart2: serial@2820000 { @@ -259,6 +261,7 @@ main_uart2: serial@2820000 { power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 153 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart3: serial@2830000 { @@ -270,6 +273,7 @@ main_uart3: serial@2830000 { power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 154 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart4: serial@2840000 { @@ -281,6 +285,7 @@ main_uart4: serial@2840000 { power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 155 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart5: serial@2850000 { @@ -292,6 +297,7 @@ main_uart5: serial@2850000 { power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 156 0>; clock-names = "fclk"; + status = "disabled"; }; main_uart6: serial@2860000 { @@ -303,6 +309,7 @@ main_uart6: serial@2860000 { power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 158 0>; clock-names = "fclk"; + status = "disabled"; }; main_i2c0: i2c@20000000 { diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi index 02d4285acbb8..1181ad017626 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -14,6 +14,7 @@ mcu_uart0: serial@4a00000 { power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 0>; clock-names = "fclk"; + status = "disabled"; }; mcu_uart1: serial@4a10000 { @@ -24,6 +25,7 @@ mcu_uart1: serial@4a10000 { power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 160 0>; clock-names = "fclk"; + status = "disabled"; }; mcu_i2c0: i2c@4900000 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 5cf913860f80..78f246077ca9 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -325,6 +325,7 @@ AM64X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (C17) MCAN1_TX */ }; &main_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; @@ -334,34 +335,6 @@ &main_uart1 { status = "reserved"; }; -&main_uart2 { - status = "disabled"; -}; - -&main_uart3 { - status = "disabled"; -}; - -&main_uart4 { - status = "disabled"; -}; - -&main_uart5 { - status = "disabled"; -}; - -&main_uart6 { - status = "disabled"; -}; - -&mcu_uart0 { - status = "disabled"; -}; - -&mcu_uart1 { - status = "disabled"; -}; - &main_i2c1 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 738d0cf6c40a..8423295150fc 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -338,15 +338,8 @@ AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ }; }; -&mcu_uart0 { - status = "disabled"; -}; - -&mcu_uart1 { - status = "disabled"; -}; - &main_uart0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; @@ -356,26 +349,6 @@ &main_uart1 { status = "reserved"; }; -&main_uart2 { - status = "disabled"; -}; - -&main_uart3 { - status = "disabled"; -}; - -&main_uart4 { - status = "disabled"; -}; - -&main_uart5 { - status = "disabled"; -}; - -&main_uart6 { - status = "disabled"; -}; - &mcu_i2c0 { status = "disabled"; }; From patchwork Mon Oct 17 19:25:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 615853 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8900EC4332F for ; Mon, 17 Oct 2022 19:26:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230123AbiJQT0b (ORCPT ); Mon, 17 Oct 2022 15:26:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45400 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231215AbiJQT0O (ORCPT ); Mon, 17 Oct 2022 15:26:14 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B47118B15; Mon, 17 Oct 2022 12:26:09 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29HJPYHK120479; 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Mon, 17 Oct 2022 14:25:34 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29HJPWXJ026106; Mon, 17 Oct 2022 14:25:33 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , , , CC: Andrew Davis Subject: [PATCH 02/10] arm64: dts: ti: k3-am64: Enable I2C nodes at the board level Date: Mon, 17 Oct 2022 14:25:24 -0500 Message-ID: <20221017192532.23825-3-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221017192532.23825-1-afd@ti.com> References: <20221017192532.23825-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org I2C nodes defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the I2C nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 4 ++++ arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 9 +-------- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 13 +------------ 4 files changed, 8 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index a115c668d001..fdcacf78f4a6 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -321,6 +321,7 @@ main_i2c0: i2c@20000000 { power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 102 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c1: i2c@20010000 { @@ -332,6 +333,7 @@ main_i2c1: i2c@20010000 { power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 103 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c2: i2c@20020000 { @@ -343,6 +345,7 @@ main_i2c2: i2c@20020000 { power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 104 2>; clock-names = "fck"; + status = "disabled"; }; main_i2c3: i2c@20030000 { @@ -354,6 +357,7 @@ main_i2c3: i2c@20030000 { power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 105 2>; clock-names = "fck"; + status = "disabled"; }; main_spi0: spi@20100000 { diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi index 1181ad017626..5ce8ceb3779d 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -37,6 +37,7 @@ mcu_i2c0: i2c@4900000 { power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 106 2>; clock-names = "fck"; + status = "disabled"; }; mcu_i2c1: i2c@4910000 { @@ -48,6 +49,7 @@ mcu_i2c1: i2c@4910000 { power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 107 2>; clock-names = "fck"; + status = "disabled"; }; mcu_spi0: spi@4b00000 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 78f246077ca9..3903e907244e 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -336,6 +336,7 @@ &main_uart1 { }; &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; @@ -378,14 +379,6 @@ &mcu_gpio0 { status = "reserved"; }; -&mcu_i2c0 { - status = "disabled"; -}; - -&mcu_i2c1 { - status = "disabled"; -}; - &mcu_spi0 { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 8423295150fc..56763d839e05 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -349,15 +349,8 @@ &main_uart1 { status = "reserved"; }; -&mcu_i2c0 { - status = "disabled"; -}; - -&mcu_i2c1 { - status = "disabled"; -}; - &main_i2c1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; @@ -382,10 +375,6 @@ exp2: gpio@60 { }; }; -&main_i2c3 { - status = "disabled"; -}; - &mcu_spi0 { status = "disabled"; }; From patchwork Mon Oct 17 19:25:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 616225 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E12BC4332F for ; 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Mon, 17 Oct 2022 14:25:34 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Mon, 17 Oct 2022 14:25:34 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Mon, 17 Oct 2022 14:25:34 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29HJPWXK026106; Mon, 17 Oct 2022 14:25:34 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , , , CC: Andrew Davis Subject: [PATCH 03/10] arm64: dts: ti: k3-am64: Enable SPI nodes at the board level Date: Mon, 17 Oct 2022 14:25:25 -0500 Message-ID: <20221017192532.23825-4-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221017192532.23825-1-afd@ti.com> References: <20221017192532.23825-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org SPI nodes defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the SPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 5 +++++ arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 9 +-------- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 8 -------- 4 files changed, 8 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index fdcacf78f4a6..375078ca4fdd 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -370,6 +370,7 @@ main_spi0: spi@20100000 { clocks = <&k3_clks 141 0>; dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; dma-names = "tx0", "rx0"; + status = "disabled"; }; main_spi1: spi@20110000 { @@ -380,6 +381,7 @@ main_spi1: spi@20110000 { #size-cells = <0>; power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 142 0>; + status = "disabled"; }; main_spi2: spi@20120000 { @@ -390,6 +392,7 @@ main_spi2: spi@20120000 { #size-cells = <0>; power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 143 0>; + status = "disabled"; }; main_spi3: spi@20130000 { @@ -400,6 +403,7 @@ main_spi3: spi@20130000 { #size-cells = <0>; power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 144 0>; + status = "disabled"; }; main_spi4: spi@20140000 { @@ -410,6 +414,7 @@ main_spi4: spi@20140000 { #size-cells = <0>; power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 145 0>; + status = "disabled"; }; main_gpio_intr: interrupt-controller@a00000 { diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi index 5ce8ceb3779d..38ddf0b3b8a0 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -60,6 +60,7 @@ mcu_spi0: spi@4b00000 { #size-cells = <0>; power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 147 0>; + status = "disabled"; }; mcu_spi1: spi@4b10000 { @@ -70,6 +71,7 @@ mcu_spi1: spi@4b10000 { #size-cells = <0>; power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 148 0>; + status = "disabled"; }; mcu_gpio_intr: interrupt-controller@4210000 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 3903e907244e..12d971c3bc3a 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -379,15 +379,8 @@ &mcu_gpio0 { status = "reserved"; }; -&mcu_spi0 { - status = "disabled"; -}; - -&mcu_spi1 { - status = "disabled"; -}; - &main_spi0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_spi0_pins_default>; ti,pindir-d0-out-d1-in; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 56763d839e05..1a116593a771 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -375,14 +375,6 @@ exp2: gpio@60 { }; }; -&mcu_spi0 { - status = "disabled"; -}; - -&mcu_spi1 { - status = "disabled"; -}; - /* mcu_gpio0 is reserved for mcu firmware usage */ &mcu_gpio0 { status = "reserved"; From patchwork Mon Oct 17 19:25:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 616226 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EBBCEC4332F for ; Mon, 17 Oct 2022 19:26:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230329AbiJQT0Z (ORCPT ); Mon, 17 Oct 2022 15:26:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56518 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230406AbiJQT0Q (ORCPT ); Mon, 17 Oct 2022 15:26:16 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 437F47437B; Mon, 17 Oct 2022 12:26:03 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29HJPZE0121476; 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Mon, 17 Oct 2022 14:25:35 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29HJPWXL026106; Mon, 17 Oct 2022 14:25:34 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , , , CC: Andrew Davis Subject: [PATCH 04/10] arm64: dts: ti: k3-am64: Enable EPWM nodes at the board level Date: Mon, 17 Oct 2022 14:25:26 -0500 Message-ID: <20221017192532.23825-5-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221017192532.23825-1-afd@ti.com> References: <20221017192532.23825-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org EPWM nodes defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the EPWM nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 9 +++++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 36 ------------------- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 44 ------------------------ 3 files changed, 9 insertions(+), 80 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 375078ca4fdd..672575f44529 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -898,6 +898,7 @@ epwm0: pwm@23000000 { power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm1: pwm@23010000 { @@ -907,6 +908,7 @@ epwm1: pwm@23010000 { power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm2: pwm@23020000 { @@ -916,6 +918,7 @@ epwm2: pwm@23020000 { power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm3: pwm@23030000 { @@ -925,6 +928,7 @@ epwm3: pwm@23030000 { power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm4: pwm@23040000 { @@ -934,6 +938,7 @@ epwm4: pwm@23040000 { power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm5: pwm@23050000 { @@ -943,6 +948,7 @@ epwm5: pwm@23050000 { power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm6: pwm@23060000 { @@ -952,6 +958,7 @@ epwm6: pwm@23060000 { power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm7: pwm@23070000 { @@ -961,6 +968,7 @@ epwm7: pwm@23070000 { power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; epwm8: pwm@23080000 { @@ -970,6 +978,7 @@ epwm8: pwm@23080000 { power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; clock-names = "tbclk", "fck"; + status = "disabled"; }; ecap0: pwm@23100000 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 12d971c3bc3a..cef3afa10c39 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -580,42 +580,6 @@ &ecap2 { status = "disabled"; }; -&epwm0 { - status = "disabled"; -}; - -&epwm1 { - status = "disabled"; -}; - -&epwm2 { - status = "disabled"; -}; - -&epwm3 { - status = "disabled"; -}; - -&epwm4 { - status = "disabled"; -}; - -&epwm5 { - status = "disabled"; -}; - -&epwm6 { - status = "disabled"; -}; - -&epwm7 { - status = "disabled"; -}; - -&epwm8 { - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 1a116593a771..51f4ae165c13 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -579,50 +579,6 @@ &ecap2 { status = "disabled"; }; -&epwm0 { - status = "disabled"; -}; - -&epwm1 { - status = "disabled"; -}; - -&epwm2 { - status = "disabled"; -}; - -&epwm3 { - status = "disabled"; -}; - -&epwm4 { - /* - * EPWM4_A, EPWM4_B is available on Pin 32 and 33 on J4 (RPi hat) - * But RPi Hat will be used for other use cases, so marking epwm4 as disabled. - */ - status = "disabled"; -}; - -&epwm5 { - /* - * EPWM5_A, EPWM5_B is available on Pin 29 and 31 on J4 (RPi hat) - * But RPi Hat will be used for other use cases, so marking epwm5 as disabled. - */ - status = "disabled"; -}; - -&epwm6 { - status = "disabled"; -}; - -&epwm7 { - status = "disabled"; -}; - -&epwm8 { - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; From patchwork Mon Oct 17 19:25:27 2022 Content-Type: text/plain; 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Mon, 17 Oct 2022 14:25:35 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29HJPWXM026106; Mon, 17 Oct 2022 14:25:35 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , , , CC: Andrew Davis Subject: [PATCH 05/10] arm64: dts: ti: k3-am64: Enable ECAP nodes at the board level Date: Mon, 17 Oct 2022 14:25:27 -0500 Message-ID: <20221017192532.23825-6-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221017192532.23825-1-afd@ti.com> References: <20221017192532.23825-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org ECAP nodes defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. (These and the EPWM nodes could be used to trigger internal actions but they are not used like that currently) As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the ECAP nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 9 +-------- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 9 +-------- 3 files changed, 5 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 672575f44529..ef1833f65bdc 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -988,6 +988,7 @@ ecap0: pwm@23100000 { power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 51 0>; clock-names = "fck"; + status = "disabled"; }; ecap1: pwm@23110000 { @@ -997,6 +998,7 @@ ecap1: pwm@23110000 { power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 52 0>; clock-names = "fck"; + status = "disabled"; }; ecap2: pwm@23120000 { @@ -1006,6 +1008,7 @@ ecap2: pwm@23120000 { power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 53 0>; clock-names = "fck"; + status = "disabled"; }; main_rti0: watchdog@e000000 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index cef3afa10c39..43d50ecfb211 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -567,19 +567,12 @@ &pcie0_ep { }; &ecap0 { + status = "okay"; /* PWM is available on Pin 1 of header J12 */ pinctrl-names = "default"; pinctrl-0 = <&main_ecap0_pins_default>; }; -&ecap1 { - status = "disabled"; -}; - -&ecap2 { - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 51f4ae165c13..8b9987ccdc1b 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -566,19 +566,12 @@ &pcie0_ep { }; &ecap0 { + status = "okay"; /* PWM is available on Pin 1 of header J3 */ pinctrl-names = "default"; pinctrl-0 = <&main_ecap0_pins_default>; }; -&ecap1 { - status = "disabled"; -}; - -&ecap2 { - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; From patchwork Mon Oct 17 19:25:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 616224 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8A0DC4167B for ; Mon, 17 Oct 2022 19:26:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230172AbiJQT03 (ORCPT ); Mon, 17 Oct 2022 15:26:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231239AbiJQT0T (ORCPT ); Mon, 17 Oct 2022 15:26:19 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 36C637677A; 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Mon, 17 Oct 2022 14:25:36 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29HJPWXN026106; Mon, 17 Oct 2022 14:25:35 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , , , CC: Andrew Davis Subject: [PATCH 06/10] arm64: dts: ti: k3-am64: Enable PCIe nodes at the board level Date: Mon, 17 Oct 2022 14:25:28 -0500 Message-ID: <20221017192532.23825-7-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221017192532.23825-1-afd@ti.com> References: <20221017192532.23825-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org PCIe nodes defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless they are extended with a SerDes PHY. And usually only one of the two modes can be used at a time as they share a SerDes link. As the PHY and mode is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the PCIe nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 2 +- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 8 -------- 3 files changed, 3 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index ef1833f65bdc..b193f88a7a0f 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -871,6 +871,7 @@ pcie0_rc: pcie@f102000 { ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; + status = "disabled"; }; pcie0_ep: pcie-ep@f102000 { @@ -889,6 +890,7 @@ pcie0_ep: pcie-ep@f102000 { clocks = <&k3_clks 114 0>; clock-names = "fck"; max-functions = /bits/ 8 <1>; + status = "disabled"; }; epwm0: pwm@23000000 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 43d50ecfb211..2dec25d90240 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -553,6 +553,7 @@ serdes0_pcie_link: phy@0 { }; &pcie0_rc { + status = "okay"; reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; @@ -563,7 +564,6 @@ &pcie0_ep { phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; num-lanes = <1>; - status = "disabled"; }; &ecap0 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 8b9987ccdc1b..58c71608d925 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -557,14 +557,6 @@ &main_r5fss1_core1 { <&main_r5fss1_core1_memory_region>; }; -&pcie0_rc { - status = "disabled"; -}; - -&pcie0_ep { - status = "disabled"; -}; - &ecap0 { status = "okay"; /* PWM is available on Pin 1 of header J3 */ From patchwork Mon Oct 17 19:25:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 615852 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7437EC4332F for ; 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Mon, 17 Oct 2022 14:25:37 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Mon, 17 Oct 2022 14:25:36 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Mon, 17 Oct 2022 14:25:36 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29HJPWXO026106; Mon, 17 Oct 2022 14:25:36 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , , , CC: Andrew Davis Subject: [PATCH 07/10] arm64: dts: ti: k3-am64: MDIO pinmux should belong to the MDIO node Date: Mon, 17 Oct 2022 14:25:29 -0500 Message-ID: <20221017192532.23825-8-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221017192532.23825-1-afd@ti.com> References: <20221017192532.23825-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Although usually integrated as a child of an Ethernet controller, MDIO IP has an independent pinout. This pinout should be controlled by the MDIO node (so if it was to be disabled for instance, the pinmux state would reflect that). Move the MDIO pins pinmux to the MIDO nodes. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 6 ++++-- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 2dec25d90240..2319ba4f5ae3 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -425,8 +425,7 @@ &usb0 { &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&mdio1_pins_default - &rgmii1_pins_default + pinctrl-0 = <&rgmii1_pins_default &rgmii2_pins_default>; }; @@ -441,6 +440,9 @@ &cpsw_port2 { }; &cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio1_pins_default>; + cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 58c71608d925..c1d634647027 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -439,8 +439,7 @@ &usb0 { &cpsw3g { pinctrl-names = "default"; - pinctrl-0 = <&mdio1_pins_default - &rgmii1_pins_default + pinctrl-0 = <&rgmii1_pins_default &rgmii2_pins_default>; }; @@ -455,6 +454,9 @@ &cpsw_port2 { }; &cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio1_pins_default>; + cpsw3g_phy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = ; From patchwork Mon Oct 17 19:25:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 615856 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3988C4332F for ; Mon, 17 Oct 2022 19:26:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231253AbiJQT0X (ORCPT ); Mon, 17 Oct 2022 15:26:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231200AbiJQT0J (ORCPT ); Mon, 17 Oct 2022 15:26:09 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42EE71A825; Mon, 17 Oct 2022 12:26:03 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29HJPbJv120494; Mon, 17 Oct 2022 14:25:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666034737; bh=KtFEujHPwKAgrsBapVOwK35q3T/eNr1mHH14Ul63X7I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=rBu/kx22v89TbVE8xZoP5aC7ZywZCTZP2Dwk40R5eXDKpAvAly4QYzHVR6eG8sgx7 IgE+jFDbztn+xYfl8mW/KttXdv64Tf3gDEUooXQcOZg5QavwLbNwyI3df3bBAhVudM B303k/yLJxgA0lZTBKCLNuyig3tm7xMjB22ueHUs= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29HJPbE0083466 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 17 Oct 2022 14:25:37 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Mon, 17 Oct 2022 14:25:37 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Mon, 17 Oct 2022 14:25:37 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29HJPWXP026106; Mon, 17 Oct 2022 14:25:36 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , , , CC: Andrew Davis Subject: [PATCH 08/10] arm64: dts: ti: k3-am64: Enable MDIO nodes at the board level Date: Mon, 17 Oct 2022 14:25:30 -0500 Message-ID: <20221017192532.23825-9-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221017192532.23825-1-afd@ti.com> References: <20221017192532.23825-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MDIO nodes defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless they are extended with a pinmux. As the attached PHY is only known about at the board integration level, these nodes should only be enabled when provided with this information. Disable the MDIO nodes (in both CPSW and ICSSG) in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 9 +-------- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 9 +-------- 3 files changed, 5 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index b193f88a7a0f..7ea07f7fe5a2 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -552,6 +552,7 @@ cpsw3g_mdio: mdio@f00 { clocks = <&k3_clks 13 0>; clock-names = "fck"; bus_freq = <1000000>; + status = "disabled"; }; cpts@3d000 { @@ -1168,6 +1169,7 @@ icssg0_mdio: mdio@32400 { #address-cells = <1>; #size-cells = <0>; bus_freq = <1000000>; + status = "disabled"; }; }; @@ -1308,6 +1310,7 @@ icssg1_mdio: mdio@32400 { clocks = <&k3_clks 82 0>; clock-names = "fck"; bus_freq = <1000000>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 2319ba4f5ae3..9a3bf852810c 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -440,6 +440,7 @@ &cpsw_port2 { }; &cpsw3g_mdio { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mdio1_pins_default>; @@ -575,14 +576,6 @@ &ecap0 { pinctrl-0 = <&main_ecap0_pins_default>; }; -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - &main_mcan0 { pinctrl-names = "default"; pinctrl-0 = <&main_mcan0_pins_default>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index c1d634647027..451e1483f3e4 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -454,6 +454,7 @@ &cpsw_port2 { }; &cpsw3g_mdio { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mdio1_pins_default>; @@ -566,14 +567,6 @@ &ecap0 { pinctrl-0 = <&main_ecap0_pins_default>; }; -&icssg0_mdio { - status = "disabled"; -}; - -&icssg1_mdio { - status = "disabled"; -}; - &main_mcan0 { status = "disabled"; }; From patchwork Mon Oct 17 19:25:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 615851 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4381C433FE for ; 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Mon, 17 Oct 2022 14:25:38 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Mon, 17 Oct 2022 14:25:37 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Mon, 17 Oct 2022 14:25:37 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29HJPWXQ026106; Mon, 17 Oct 2022 14:25:37 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , , , CC: Andrew Davis Subject: [PATCH 09/10] arm64: dts: ti: k3-am64: Enable MCAN nodes at the board level Date: Mon, 17 Oct 2022 14:25:31 -0500 Message-ID: <20221017192532.23825-10-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221017192532.23825-1-afd@ti.com> References: <20221017192532.23825-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org MCAN nodes defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the MCAN nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 2 ++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 8 -------- 3 files changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index 7ea07f7fe5a2..d6218038055a 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1326,6 +1326,7 @@ main_mcan0: can@20701000 { ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; main_mcan1: can@20711000 { @@ -1340,6 +1341,7 @@ main_mcan1: can@20711000 { ; interrupt-names = "int0", "int1"; bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + status = "disabled"; }; crypto: crypto@40900000 { diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 9a3bf852810c..666f5d3a2d95 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -577,12 +577,14 @@ &ecap0 { }; &main_mcan0 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan0_pins_default>; phys = <&transceiver1>; }; &main_mcan1 { + status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan1_pins_default>; phys = <&transceiver2>; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 451e1483f3e4..3e6df16fcb59 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -567,14 +567,6 @@ &ecap0 { pinctrl-0 = <&main_ecap0_pins_default>; }; -&main_mcan0 { - status = "disabled"; -}; - -&main_mcan1 { - status = "disabled"; -}; - &gpmc0 { status = "disabled"; }; From patchwork Mon Oct 17 19:25:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 615855 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D914AC43219 for ; Mon, 17 Oct 2022 19:26:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231200AbiJQT00 (ORCPT ); Mon, 17 Oct 2022 15:26:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35120 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230483AbiJQT0S (ORCPT ); Mon, 17 Oct 2022 15:26:18 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1388218B30; Mon, 17 Oct 2022 12:26:04 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29HJPctN017214; Mon, 17 Oct 2022 14:25:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666034738; bh=gJnlZ3gu7fn/Vfuey53wcldGkX1GM1+DM6mfFO9jJeo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=cOtXbLOtibVGV6o6Sdkh/v00yuNc1JqSKwAaWwP1LCBDMqmyBa/L4PdCJRuqZVG4s hKklBcRyNNT/yzAR0kud8iu8DGkj9UwkW3m92kNJwCUxscMsXlxrwYqMCuKYY8POi9 1mtXPxO3BVGo1528M5ek75ZmWbaBxg2mumeLkliA= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29HJPcpf026089 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 17 Oct 2022 14:25:38 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Mon, 17 Oct 2022 14:25:38 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Mon, 17 Oct 2022 14:25:38 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29HJPWXR026106; Mon, 17 Oct 2022 14:25:37 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , , , CC: Andrew Davis Subject: [PATCH 10/10] arm64: dts: ti: k3-am64: Enable GPMC and ELM nodes at the board level Date: Mon, 17 Oct 2022 14:25:32 -0500 Message-ID: <20221017192532.23825-11-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221017192532.23825-1-afd@ti.com> References: <20221017192532.23825-1-afd@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The GPMC node defined in the top-level AM64x SoC dtsi files are incomplete and will not be functional unless it is extended with pinmux information. As the pinmux is only known at the board integration level, this node should only be enabled when provided with this information. Disable the GPMC node in the dtsi file. Since the ELM is made to work with the GPMC, disable it too. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 8 -------- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 8 -------- 3 files changed, 2 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi index d6218038055a..c96df4b9b3d7 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi @@ -1381,6 +1381,7 @@ gpmc0: memory-controller@3b000000 { #interrupt-cells = <2>; gpio-controller; #gpio-cells = <2>; + status = "disabled"; }; elm0: ecc@25010000 { @@ -1390,5 +1391,6 @@ elm0: ecc@25010000 { power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 54 0>; clock-names = "fck"; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index 666f5d3a2d95..39feea78a084 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -589,11 +589,3 @@ &main_mcan1 { pinctrl-0 = <&main_mcan1_pins_default>; phys = <&transceiver2>; }; - -&gpmc0 { - status = "disabled"; -}; - -&elm0 { - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 3e6df16fcb59..2e2d40da360a 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -566,11 +566,3 @@ &ecap0 { pinctrl-names = "default"; pinctrl-0 = <&main_ecap0_pins_default>; }; - -&gpmc0 { - status = "disabled"; -}; - -&elm0 { - status = "disabled"; -};