From patchwork Thu Oct 13 21:46:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 614758 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp498202pvb; Thu, 13 Oct 2022 14:51:08 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5byVQUl7DqzbIW5238cSFeCpr2uyoCy4kzQ7Yi7B1JAKttNL736c+dMzY3PCrsZXkQhSOQ X-Received: by 2002:a05:6214:230c:b0:4b1:795c:4e89 with SMTP id gc12-20020a056214230c00b004b1795c4e89mr1867978qvb.18.1665697868796; Thu, 13 Oct 2022 14:51:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665697868; cv=none; d=google.com; s=arc-20160816; b=Acka9dFHtknjNFomVIEJwdmMFL2E15M4gMIztoHG4cg5YbaJyWuJsM8sK6BNzaDoJY MFuH3Mo5sreJLddH5CJ+jkbBcCF3vE4D6LvIrZPXjKl3Gy99IpJ30s27GV7rfoA47kid wZKt9HgxwgwqbWo5Dm04qh/i7nHNnCDPx+YeRgBf4IgAbUFgVAv8ozUyG9Ols776Qlg6 Xv0VMigmK/DpFyehzOhypF1ZQpQc8qMIin0b2Qb5IzuhJnS/d4/HWY8GjTxsNTR9diyJ 1Y+yhb0Nd//5K7A7vkEBGBcaJtzNXr1TVJo3a8v+itcA6GnOv1MenTQJeGZl8tRaUB58 CN2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=kEyemxO9xMYMhd66NPRMZhd75CaPXlPzvYN7a53fY5Y=; b=bC+WYGqaEraT/foNQXPqyOPUGnHnNvGz/RRJ4OQ67LJTc/Ki8yndKeJSxSfBS+d6ib oFdaZfm0GUo8RC8+li9D/j1zu1O4Ugve+TbnVnbVkpOCHaS8UZI36iOQ/Ur5YwenkbhL 27QuFuuH9eXIZU1rAq5P5kEHqv8Rikk7Xe9WDAnbbymKL0egvE4cNZ1KKG81HM5id/8/ t8D6WnpxNQTf4UnY4X5YRQppYpjxOCoqVxfLL2jM+8hNI/GVWdRvKtqqPZybtGK4Z6K2 4OrsanI0+8hyOuBiHuuEKgRfMnm2vANLP5GcsJ+yhNjSQwmo3RrKImHoCzfnp479Agwb ULfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=MomER4ic; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g20-20020a05620a40d400b006ee1af5f55esi557078qko.325.2022.10.13.14.51.08 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Oct 2022 14:51:08 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=MomER4ic; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1]:42748 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oj66e-0002T4-AF for patch@linaro.org; Thu, 13 Oct 2022 17:51:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44878) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oj62i-0002SV-Ke for qemu-devel@nongnu.org; Thu, 13 Oct 2022 17:47:07 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]:52975) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oj62g-0005BD-62 for qemu-devel@nongnu.org; Thu, 13 Oct 2022 17:47:03 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1665697621; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kEyemxO9xMYMhd66NPRMZhd75CaPXlPzvYN7a53fY5Y=; b=MomER4icUgIJZbLQUsMxD+iFF6QUnT46cFMVlFYuimKRhjedMMQGjvorGaHTV/ishSygpc /3Zh9jHo8xKN963YTeW9Y8dyQH6VetcIfJkmOTaO6c9/Fnl7ilKn9gveWav9YFsU+GvkEc FjpmTNsAYvG7Ql86LciLdEWgvTwN3lk= Received: from mail-ed1-f72.google.com (mail-ed1-f72.google.com [209.85.208.72]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-43-HEVpW308PyyQxMuG94rgJA-1; Thu, 13 Oct 2022 17:47:00 -0400 X-MC-Unique: HEVpW308PyyQxMuG94rgJA-1 Received: by mail-ed1-f72.google.com with SMTP id h13-20020a056402280d00b0045cb282161cso2331433ede.8 for ; Thu, 13 Oct 2022 14:47:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kEyemxO9xMYMhd66NPRMZhd75CaPXlPzvYN7a53fY5Y=; b=YPjWEmO2hT8CW7g19YfcqwSPb/R43GOW98ULVtfuLppY0yA3T0nr7Gfx09hwxjua4G bYEHh2C71rXwhlzBDThUBOtuwOZHHEBMc2xwSLSfRzCbO+9UveHVPvQSdDIDM8tbzmjt EYJe1ifwJ8XSoRfF/EERZijhhFb2mCXUt9T6NAN4gX+GXY5oijPFxs+uF+RFRKO1pj6h Iyf+cWKrbBpBROeRIqMAjC/WASvmkUm0egoSVa/LgYrlpq0kUnztGEX4zrVF3H0/kmWE QtT/VhPCQ1M/fWKgF8gtU/MEm+u79X9KBGt2kF7UyrGaMw+5SHKkraKU6hBJA2bgTlAY E96Q== X-Gm-Message-State: ACrzQf3o53pEAJ28+5NBfXvgS/Ice6Gk2wgwqwSra2XH7Caa4SZhdxcO odopmjMrS41SJ+oS0GupfGcP9GEB7CRLNE/Txr0cZuSE80QlEDKkb1yUqGfoMvgGEZaAFu/8zYs QO5C5WGTl1tjuX5YNvoSFp5S53IZRH/n7yhwH7RMho4/ZQdjKccd2nZqqMMrMulILl00= X-Received: by 2002:a05:6402:27cd:b0:45c:db6f:7e77 with SMTP id c13-20020a05640227cd00b0045cdb6f7e77mr1575920ede.149.1665697618830; Thu, 13 Oct 2022 14:46:58 -0700 (PDT) X-Received: by 2002:a05:6402:27cd:b0:45c:db6f:7e77 with SMTP id c13-20020a05640227cd00b0045cdb6f7e77mr1575906ede.149.1665697618540; Thu, 13 Oct 2022 14:46:58 -0700 (PDT) Received: from avogadro.local ([2001:b07:6468:f312:1c09:f536:3de6:228c]) by smtp.gmail.com with ESMTPSA id k17-20020aa7c391000000b00456cbd8c65bsm556218edq.6.2022.10.13.14.46.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Oct 2022 14:46:57 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: paul@nowt.org, richard.henderson@linaro.org Subject: [PATCH 01/35] target/i386: Define XMMReg and access macros, align ZMM registers Date: Thu, 13 Oct 2022 23:46:17 +0200 Message-Id: <20221013214651.672114-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221013214651.672114-1-pbonzini@redhat.com> References: <20221013214651.672114-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson This will be used for emission and endian adjustments of gvec operations. Signed-off-by: Richard Henderson Message-Id: <20220822223722.1697758-2-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini --- target/i386/cpu.h | 56 ++++++++++++++++++++++++++++++++++++----------- 1 file changed, 43 insertions(+), 13 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9327353fff..63bb500d07 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1233,18 +1233,34 @@ typedef struct SegmentCache { uint32_t flags; } SegmentCache; -#define MMREG_UNION(n, bits) \ - union n { \ - uint8_t _b_##n[(bits)/8]; \ - uint16_t _w_##n[(bits)/16]; \ - uint32_t _l_##n[(bits)/32]; \ - uint64_t _q_##n[(bits)/64]; \ - float32 _s_##n[(bits)/32]; \ - float64 _d_##n[(bits)/64]; \ - } +typedef union MMXReg { + uint8_t _b_MMXReg[64 / 8]; + uint16_t _w_MMXReg[64 / 16]; + uint32_t _l_MMXReg[64 / 32]; + uint64_t _q_MMXReg[64 / 64]; + float32 _s_MMXReg[64 / 32]; + float64 _d_MMXReg[64 / 64]; +} MMXReg; -typedef MMREG_UNION(ZMMReg, 512) ZMMReg; -typedef MMREG_UNION(MMXReg, 64) MMXReg; +typedef union XMMReg { + uint64_t _q_XMMReg[128 / 64]; +} XMMReg; + +typedef union YMMReg { + uint64_t _q_YMMReg[256 / 64]; + XMMReg _x_YMMReg[256 / 128]; +} YMMReg; + +typedef union ZMMReg { + uint8_t _b_ZMMReg[512 / 8]; + uint16_t _w_ZMMReg[512 / 16]; + uint32_t _l_ZMMReg[512 / 32]; + uint64_t _q_ZMMReg[512 / 64]; + float32 _s_ZMMReg[512 / 32]; + float64 _d_ZMMReg[512 / 64]; + XMMReg _x_ZMMReg[512 / 128]; + YMMReg _y_ZMMReg[512 / 256]; +} ZMMReg; typedef struct BNDReg { uint64_t lb; @@ -1267,6 +1283,13 @@ typedef struct BNDCSReg { #define ZMM_S(n) _s_ZMMReg[15 - (n)] #define ZMM_Q(n) _q_ZMMReg[7 - (n)] #define ZMM_D(n) _d_ZMMReg[7 - (n)] +#define ZMM_X(n) _x_ZMMReg[3 - (n)] +#define ZMM_Y(n) _y_ZMMReg[1 - (n)] + +#define XMM_Q(n) _q_XMMReg[1 - (n)] + +#define YMM_Q(n) _q_YMMReg[3 - (n)] +#define YMM_X(n) _x_YMMReg[1 - (n)] #define MMX_B(n) _b_MMXReg[7 - (n)] #define MMX_W(n) _w_MMXReg[3 - (n)] @@ -1279,6 +1302,13 @@ typedef struct BNDCSReg { #define ZMM_S(n) _s_ZMMReg[n] #define ZMM_Q(n) _q_ZMMReg[n] #define ZMM_D(n) _d_ZMMReg[n] +#define ZMM_X(n) _x_ZMMReg[n] +#define ZMM_Y(n) _y_ZMMReg[n] + +#define XMM_Q(n) _q_XMMReg[n] + +#define YMM_Q(n) _q_YMMReg[n] +#define YMM_X(n) _x_YMMReg[n] #define MMX_B(n) _b_MMXReg[n] #define MMX_W(n) _w_MMXReg[n] @@ -1556,8 +1586,8 @@ typedef struct CPUArchState { float_status mmx_status; /* for 3DNow! float ops */ float_status sse_status; uint32_t mxcsr; - ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; - ZMMReg xmm_t0; + ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32] QEMU_ALIGNED(16); + ZMMReg xmm_t0 QEMU_ALIGNED(16); MMXReg mmx_t0; uint64_t opmask_regs[NB_OPMASK_REGS]; From patchwork Thu Oct 13 21:46:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paolo Bonzini X-Patchwork-Id: 614759 Delivered-To: patch@linaro.org Received: by 2002:a17:522:c983:b0:460:3032:e3c4 with SMTP id kr3csp506903pvb; Thu, 13 Oct 2022 15:11:41 -0700 (PDT) X-Google-Smtp-Source: AMsMyM52P0cl0zcgte3Juvj0ZlBz2ZMOCtOVw7Ix+DtzOML8P6Fq5udKirnFZpZVGjnPuMDMJtE2 X-Received: by 2002:a05:622a:1051:b0:35c:eb36:d61 with SMTP id f17-20020a05622a105100b0035ceb360d61mr1901571qte.582.1665699101344; Thu, 13 Oct 2022 15:11:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1665699101; cv=none; d=google.com; s=arc-20160816; b=xX0cQSp2ZtX5lPbmUHCOb62hFFJ2vXonZNPRZ2HZ//u0UrRFiUYOOpfvIzWpbwCuuF 6kuivy02PBaAbW5CqKeRqWH1Nwp+4VBuKZAc87BHunfS5eNeyuQeTXihMDvQyJweTBnu tNy7peiVs7y6UuAd6cYuoV49A68I/+R1sxULzpqeFNclhiQwEj4BbnI7mofNNMKGGhsW JkP+ol65rfLiLtvVC1nNgpjUA8aUe1mMniKuTORhKC5rPCiBoc32Cvtj/uIe1nsTH2/W 4jfzCrZbXaAm6CqLteFA1rorp22kBdcbEPUtOSms9j8yWmfK0WpyQ2UtXMXtSCG03CYJ ofTQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=k229EqfcdmSEeYRUd9pze+gwJ+qeSPgXw5lbUelqaYo=; b=VZnSKK/OxBbQliIDoV1PiiY55lztAgUWTLvcOcXgzz/t+ei65fJnJfAGThKfZAsfnc 1UzfzDF2V9+du+ik5fQPe1DhO9WyQxGRMyQSxRfDQBoEwf8Fi7m5hrgMkq+8gjjrYjiq WTcJQ8t4Q3j32BY57bdOnZL3Q+h4kCugPZCgkv4ht/FZSOXx4F7yx/hpW7llTzS+CsD6 LQCS5IPvlAu4RrursPirnFT+qoY6stkIhFYRB5UE3cyQ14Y6lD6htfZCMU/2uA7Dh5L0 CcIxPcZyJlaj5cD/GtSNtb0v87Mko3glqwmpp7rL1r9v5wECfkt/eeLFZRC1hOmRoaZv RTKg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=V7ZT7qlP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p2-20020a378d02000000b006ce93e46f95si482334qkd.40.2022.10.13.15.11.41 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 13 Oct 2022 15:11:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=V7ZT7qlP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=redhat.com Received: from localhost ([::1]:33194 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oj6QW-00040S-Qp for patch@linaro.org; Thu, 13 Oct 2022 18:11:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35900) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oj63s-0002qz-Q4 for qemu-devel@nongnu.org; Thu, 13 Oct 2022 17:48:19 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]:41896) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oj63n-0005JY-SS for qemu-devel@nongnu.org; Thu, 13 Oct 2022 17:48:13 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1665697690; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=k229EqfcdmSEeYRUd9pze+gwJ+qeSPgXw5lbUelqaYo=; b=V7ZT7qlPw4aUcVlW3obltqCjgJgqPiCobjkquxwAulkrHunLuQDji9qiMA0N3/2Z2BzF8B KjGL2vsUcpLxqbD/vtRkuRz8CbOvrLsbr4+YcAnrkRsYKmkNdxJGJqGOCkeXt7p8dTWEsI 8XUwYkbb9N0ksiEwsfoFKIO3C1m0hsg= Received: from mail-ed1-f70.google.com (mail-ed1-f70.google.com [209.85.208.70]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-93-6znWEnTbNZCvASxsKwL9Uw-1; Thu, 13 Oct 2022 17:48:09 -0400 X-MC-Unique: 6znWEnTbNZCvASxsKwL9Uw-1 Received: by mail-ed1-f70.google.com with SMTP id f18-20020a056402355200b0045c13ee57d9so2365506edd.20 for ; Thu, 13 Oct 2022 14:48:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=k229EqfcdmSEeYRUd9pze+gwJ+qeSPgXw5lbUelqaYo=; b=uxEsDnalezqj7npArnu7287/TZHBivyk6qX0jSnvnCqc1CzcOGpNKXgnTcEmnBHnTx XXrzKeTHtvsLJan4u/sEiNBBxB0E2CLjX8wyAi+APL/vMw5le5gfk8W00D6YQZ4kbC/r 9KRHMnWYEeyDSdccISVW+sFOUnZFGnhAPFBY4w28NJp/IywgQaXGzId+JoTLhGce2ZLj 6gQgCUZlCQwIzpOt00pJgu2mrXvixEJgNWvUVLGi6yhEWzBrHgCA6EDgXpokem6L7f7z ObYYoAgT7NnJo8V5mfiVT6teGM+D+qJI9fTeZ6Y3cYiLPkRUs/QLhPQfnq5v3iUnPSnL V9Dg== X-Gm-Message-State: ACrzQf1krzXuTsBW3SGSFTRKcD2qUXBmZekh2IWANs0OCfFCPpUNtpBm 3Vc2f07gSoBLEyxDfbXaXnQoHsNpTVaFpRhuMr1omisx+CWvQl7/vkYAhj5VsYVKJAOeaoHNUfC /bTbwW6SbqxeAsK3ajbtMzsKCunDh2raFLbfXpWfP+ToIZCOJBJG3W21XvT54COczEGU= X-Received: by 2002:a17:907:70a:b0:741:78ab:dce5 with SMTP id xb10-20020a170907070a00b0074178abdce5mr1309233ejb.527.1665697687305; Thu, 13 Oct 2022 14:48:07 -0700 (PDT) X-Received: by 2002:a17:907:70a:b0:741:78ab:dce5 with SMTP id xb10-20020a170907070a00b0074178abdce5mr1309222ejb.527.1665697687015; Thu, 13 Oct 2022 14:48:07 -0700 (PDT) Received: from avogadro.local ([2001:b07:6468:f312:1c09:f536:3de6:228c]) by smtp.gmail.com with ESMTPSA id g16-20020a170906539000b0073d5948855asm496457ejo.1.2022.10.13.14.48.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Oct 2022 14:48:06 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: paul@nowt.org, richard.henderson@linaro.org Subject: [PATCH 25/35] target/i386: Use tcg gvec ops for pmovmskb Date: Thu, 13 Oct 2022 23:46:41 +0200 Message-Id: <20221013214651.672114-26-pbonzini@redhat.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221013214651.672114-1-pbonzini@redhat.com> References: <20221013214651.672114-1-pbonzini@redhat.com> MIME-Version: 1.0 Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson As pmovmskb is used by strlen et al, this is the third highest overhead sse operation at %0.8. Signed-off-by: Richard Henderson [Reorganize to generate code for any vector size. - Paolo] Signed-off-by: Paolo Bonzini --- target/i386/tcg/emit.c.inc | 88 +++++++++++++++++++++++++++++++++++--- 1 file changed, 83 insertions(+), 5 deletions(-) diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc index 062c92e45a..ad93094ca8 100644 --- a/target/i386/tcg/emit.c.inc +++ b/target/i386/tcg/emit.c.inc @@ -1191,14 +1191,92 @@ static void gen_PINSR(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) gen_pinsr(s, env, decode, decode->op[2].ot); } +static void gen_pmovmskb_i64(TCGv_i64 d, TCGv_i64 s) +{ + TCGv_i64 t = tcg_temp_new_i64(); + + tcg_gen_andi_i64(d, s, 0x8080808080808080ull); + + /* + * After each shift+or pair: + * 0: a.......b.......c.......d.......e.......f.......g.......h....... + * 7: ab......bc......cd......de......ef......fg......gh......h....... + * 14: abcd....bcde....cdef....defg....efgh....fgh.....gh......h....... + * 28: abcdefghbcdefgh.cdefgh..defgh...efgh....fgh.....gh......h....... + * The result is left in the high bits of the word. + */ + tcg_gen_shli_i64(t, d, 7); + tcg_gen_or_i64(d, d, t); + tcg_gen_shli_i64(t, d, 14); + tcg_gen_or_i64(d, d, t); + tcg_gen_shli_i64(t, d, 28); + tcg_gen_or_i64(d, d, t); +} + +static void gen_pmovmskb_vec(unsigned vece, TCGv_vec d, TCGv_vec s) +{ + TCGv_vec t = tcg_temp_new_vec_matching(d); + TCGv_vec m = tcg_constant_vec_matching(d, MO_8, 0x80); + + /* See above */ + tcg_gen_and_vec(vece, d, s, m); + tcg_gen_shli_vec(vece, t, d, 7); + tcg_gen_or_vec(vece, d, d, t); + tcg_gen_shli_vec(vece, t, d, 14); + tcg_gen_or_vec(vece, d, d, t); + tcg_gen_shli_vec(vece, t, d, 28); + tcg_gen_or_vec(vece, d, d, t); +} + +#ifdef TARGET_X86_64 +#define TCG_TARGET_HAS_extract2_tl TCG_TARGET_HAS_extract2_i64 +#else +#define TCG_TARGET_HAS_extract2_tl TCG_TARGET_HAS_extract2_i32 +#endif + static void gen_PMOVMSKB(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode) { - if (s->prefix & PREFIX_DATA) { - gen_helper_pmovmskb_xmm(s->tmp2_i32, cpu_env, OP_PTR2); - } else { - gen_helper_pmovmskb_mmx(s->tmp2_i32, cpu_env, OP_PTR2); + static const TCGOpcode vecop_list[] = { INDEX_op_shli_vec, 0 }; + static const GVecGen2 g = { + .fni8 = gen_pmovmskb_i64, + .fniv = gen_pmovmskb_vec, + .opt_opc = vecop_list, + .vece = MO_64, + .prefer_i64 = TCG_TARGET_REG_BITS == 64 + }; + MemOp ot = decode->op[2].ot; + int vec_len = vector_len(s, decode); + TCGv t = tcg_temp_new(); + + tcg_gen_gvec_2(offsetof(CPUX86State, xmm_t0) + xmm_offset(ot), decode->op[2].offset, + vec_len, vec_len, &g); + tcg_gen_ld8u_tl(s->T0, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1))); + while (vec_len > 8) { + vec_len -= 8; + if (TCG_TARGET_HAS_extract2_tl) { + /* + * Load the next byte of the result into the high byte of T. + * TCG does a similar expansion of deposit to shl+extract2; by + * loading the whole word, the shift left is avoided. + */ +#ifdef TARGET_X86_64 + tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_Q((vec_len - 1) / 8))); +#else + tcg_gen_ld_tl(t, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_L((vec_len - 1) / 4))); +#endif + + tcg_gen_extract2_tl(s->T0, t, s->T0, TARGET_LONG_BITS - 8); + } else { + /* + * The _previous_ value is deposited into bits 8 and higher of t. Because + * those bits are known to be zero after ld8u, this becomes a shift+or + * if deposit is not available. + */ + tcg_gen_ld8u_tl(t, cpu_env, offsetof(CPUX86State, xmm_t0.ZMM_B(vec_len - 1))); + tcg_gen_deposit_tl(s->T0, t, s->T0, 8, TARGET_LONG_BITS - 8); + } } - tcg_gen_extu_i32_tl(s->T0, s->tmp2_i32); + tcg_temp_free(t); } static void gen_PSHUFW(DisasContext *s, CPUX86State *env, X86DecodedInsn *decode)