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[209.51.188.17]) by mx.google.com with ESMTPS id n6si10108010ywh.299.2019.02.27.18.29.39 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 27 Feb 2019 18:29:40 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=xCTNdYeW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:55900 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzBS7-0006XY-JR for patch@linaro.org; Wed, 27 Feb 2019 21:29:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:43948) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gzBN9-0003OJ-Ha for qemu-devel@nongnu.org; Wed, 27 Feb 2019 21:24:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gzBMz-00053N-4W for qemu-devel@nongnu.org; Wed, 27 Feb 2019 21:24:21 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:40170) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1gzBMy-000522-Sp for qemu-devel@nongnu.org; Wed, 27 Feb 2019 21:24:21 -0500 Received: by mail-pf1-x444.google.com with SMTP id h1so8937762pfo.7 for ; Wed, 27 Feb 2019 18:24:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xvID2qgXqZj1yGEiZojx46MlPX9UnBo71CxlwZmoZ40=; b=xCTNdYeWRjgqo7ok6xeWY3ZVoD9buli3q+Ooz/Cwtx9k6CN//5r1sAOlS2eIU/QZz/ T31zAw7ms9Rr77j9oqqp/wqAk9KAXK8Q9pH3aOwRG8InA83aDoDCKuv0ZQDQSSrA3bKV CwEC5bvk6HOD3wcKklL6Q4LR6ziv5GViDizGlmEe/rZpVug4W+piK0Lj6NM+A1jzP7hu rPVomHrKPUL0GNpoCtQ2892s5WQ2sOGhF4IyAgNsdKW2Pm2Psgj6/QHnwLuzINZzlFW1 t+Y3ILRo6VsRjwGohiBoMVltJAnnpTk3v2jwfFgf1M0y8EbI7Q6Cqd45f+THDBAqn1ZP TISQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xvID2qgXqZj1yGEiZojx46MlPX9UnBo71CxlwZmoZ40=; b=jfbRxpnhkhkyAWHvRpo5x6ywh+c9BydAs2RCdcJak1AxnbkzbYinIpuvfjiwCB7uXj Puam8bR1aK0qPoDnnLYEvKFd88XMi4GwDKf6PIrIHr5CnLK4kRtYnA8Z5HT06H2uItuw Ma856dB4ee1IFRIsQ5IchneZ8BsQPJJyexE0RnK9M4AdNtcmnGQ71FXDVLd6szMJ2aKT 14JfRLfT9cQVI6v1vyI0PBiWWcB35LomgUb4Ind4k4s7Ec2movnMzMvnxGRHVS1Xoywp 1KUEsZj9Zc4u0ggxlD6OHFb7xQ9mHMMspNcIbtIm3NFq+tG3fANTuwpnW5mQE06VHoZ6 IxbA== X-Gm-Message-State: AHQUAuZF6MNJfFzcIpbT5e0xuOZk77i6zTpkdx7DRv6CEteJAYVwcUCU vs9BG2suZ7T6NijxDTCXjRVU58Xx6q0= X-Received: by 2002:a63:455f:: with SMTP id u31mr6053273pgk.241.1551320659482; Wed, 27 Feb 2019 18:24:19 -0800 (PST) Received: from cloudburst.dc.rr.com ([2605:e000:100e:478c:cfa2:eb27:db4f:e85]) by smtp.gmail.com with ESMTPSA id l28sm11928346pfi.186.2019.02.27.18.24.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 27 Feb 2019 18:24:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 27 Feb 2019 18:24:13 -0800 Message-Id: <20190228022415.27878-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190228022415.27878-1-richard.henderson@linaro.org> References: <20190228022415.27878-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v2 1/3] target/arm: Split out arm_sctlr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Minimize the number of places that will need updating when the virtual host extensions are added. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 26 ++++++++++++++++---------- target/arm/helper.c | 8 ++------ 2 files changed, 18 insertions(+), 16 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1eea1a408b..9a4c56826a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3029,11 +3029,20 @@ static inline bool arm_sctlr_b(CPUARMState *env) (env->cp15.sctlr_el[1] & SCTLR_B) != 0; } +static inline uint64_t arm_sctlr(CPUARMState *env, int el) +{ + if (el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + return env->cp15.sctlr_el[1]; + } else { + return env->cp15.sctlr_el[el]; + } +} + + /* Return true if the processor is in big-endian mode. */ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) { - int cur_el; - /* In 32bit endianness is determined by looking at CPSR's E bit */ if (!is_a64(env)) { return @@ -3052,15 +3061,12 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) arm_sctlr_b(env) || #endif ((env->uncached_cpsr & CPSR_E) ? 1 : 0); + } else { + int cur_el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, cur_el); + + return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0; } - - cur_el = arm_current_el(env); - - if (cur_el == 0) { - return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; - } - - return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; } #include "exec/cpu-all.h" diff --git a/target/arm/helper.c b/target/arm/helper.c index fbaa801cea..8a71a80dfd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12877,12 +12877,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); } - if (current_el == 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - sctlr = env->cp15.sctlr_el[1]; - } else { - sctlr = env->cp15.sctlr_el[current_el]; - } + sctlr = arm_sctlr(env, current_el); + if (cpu_isar_feature(aa64_pauth, cpu)) { /* * In order to save space in flags, we record only whether From patchwork Thu Feb 28 02:24:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159304 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp111307jad; Wed, 27 Feb 2019 18:26:58 -0800 (PST) X-Google-Smtp-Source: AHgI3IYRME1sUOGdl+2Rk+lKaXdOiHBbEPjAE0cDItw9UQVasplUfypdebUcU5rrMtvf0spj5d6M X-Received: by 2002:a81:3d07:: with SMTP id k7mr3755346ywa.262.1551320818273; Wed, 27 Feb 2019 18:26:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551320818; cv=none; d=google.com; s=arc-20160816; b=SMmvkslS04TPXdqPcYtTKizzv1ccN++i22wg+KHf2FPpG1gDJtPDjdUOoRuRUJyy2/ sFVqJKtuULfm+85APCs78Ve8XOvZ6QNBEORWcyczjNC+vQl79554T/0au0zoqTY+78rH ejPSxyO0+CjR0eR1U7yai8E1h2uPKs5Nri/nj/EdhjEqgM+cabVBcich9bYtUxSDhMqT M1BLNtWALiXLW5AQ3AhNkLMwNafaYN4xqNp/CS5BOyxuQaDCgQBNGhy4brNOtYRZGb97 y9i6aFIuOoZNHVNVsAL4eG+z73tcJOfq3/ZS+hH+JHCz2YBFERVRWZVCQtGjO7wKVdZi 7YAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=LChsYdkE7QTme6BJYdMYtByCP2AoIgVkch18ulXBP7c=; b=ySpqYccjjW136Z2ZD3WydfqFuQSSXSOMDTXrjWZXQowvsRRK6HLg8Y8iu6hDiF+NlR G2W9G2/8N9fgzSOUoq+NnrPWxS45+1ZmUn6W52G/Ig225pTQuww4pGknAT+IB/QqEvjZ zVl/13+wRkK8G/ROC/YT+OsYr1ioZMDbSwGnLubkRypypsZQWw/b7ERxvMThB4O4+7Hh Oxx0FtOycnZbcD0TBJQIErf9EuuGm2n+PNTWTfrWEf16JYshLl/9ulCqx9RqeBKB1ksZ 0yQn6PjAyp7CBnuZdYmdm8Gk6vp3NhyBflHJ/2XkV2kSFebSFtLdEzIInNy9JZi0nN9z 5NmQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="e7/wSX0f"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::644 Subject: [Qemu-devel] [PATCH v2 2/3] target/arm: Implement ARMv8.0-SB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++++++++++ linux-user/elfload.c | 1 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 2 ++ target/arm/translate-a64.c | 14 ++++++++++++++ target/arm/translate.c | 22 ++++++++++++++++++++++ 6 files changed, 50 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9a4c56826a..1a6ca35ea7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3289,6 +3289,11 @@ static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; } +static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* @@ -3387,6 +3392,11 @@ static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; } +static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 3a50d587ff..b7484f6d82 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -602,6 +602,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA); GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE); GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG); + GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); #undef GET_FEATURE_ID diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8ea6569088..7940d49c1d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2003,6 +2003,7 @@ static void arm_max_initfn(Object *obj) t = cpu->isar.id_isar6; t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); t = FIELD_DP32(t, ID_ISAR6, DP, 1); + t = FIELD_DP32(t, ID_ISAR6, SB, 1); cpu->isar.id_isar6 = t; t = cpu->id_mmfr4; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 69e4134f79..168aa9e0f1 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -317,6 +317,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ISAR1, API, 0); t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); + t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); cpu->isar.id_aa64isar1 = t; t = cpu->isar.id_aa64pfr0; @@ -347,6 +348,7 @@ static void aarch64_max_initfn(Object *obj) u = cpu->isar.id_isar6; u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); u = FIELD_DP32(u, ID_ISAR6, DP, 1); + u = FIELD_DP32(u, ID_ISAR6, SB, 1); cpu->isar.id_isar6 = u; /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c56e878787..7c00d084ce 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1637,7 +1637,21 @@ static void handle_sync(DisasContext *s, uint32_t insn, reset_btype(s); gen_goto_tb(s, 0, s->pc); return; + + case 7: /* SB */ + if (crm != 0 || !dc_isar_feature(aa64_sb, s)) { + goto do_unallocated; + } + /* + * TODO: There is no speculation barrier opcode for TCG; + * MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->pc); + return; + default: + do_unallocated: unallocated_encoding(s); return; } diff --git a/target/arm/translate.c b/target/arm/translate.c index c1175798ac..b86086ada9 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9208,6 +9208,17 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) */ gen_goto_tb(s, 0, s->pc & ~1); return; + case 7: /* sb */ + if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) { + goto illegal_op; + } + /* + * TODO: There is no speculation barrier opcode + * for TCG; MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->pc & ~1); + return; default: goto illegal_op; } @@ -11826,6 +11837,17 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) */ gen_goto_tb(s, 0, s->pc & ~1); break; + case 7: /* sb */ + if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) { + goto illegal_op; + } + /* + * TODO: There is no speculation barrier opcode + * for TCG; MB and end the TB instead. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); + gen_goto_tb(s, 0, s->pc & ~1); + break; default: goto illegal_op; } From patchwork Thu Feb 28 02:24:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 159303 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp111266jad; Wed, 27 Feb 2019 18:26:53 -0800 (PST) X-Google-Smtp-Source: AHgI3IZKOOgCc/1yEQHiXnoQrlM6sd22HN0684GNk4itz+upKQfU9DXI3jz3cm4dNX5A9otqXXZ1 X-Received: by 2002:a81:3988:: with SMTP id g130mr3942601ywa.470.1551320813505; Wed, 27 Feb 2019 18:26:53 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551320813; cv=none; d=google.com; s=arc-20160816; b=Sax2yK6r/LbFiytb+GDdkpNjPcHkviTOOtlOeSwrn+NQDhUrLyFjSD0DlTJq2LEMRv ICEbY3G97G50yV0m/oXL0xKXdgeZHhYpUmi0MKOX3879+c368kO9YRBR2sTJh3yTSg7F yRA4tHhnLkwY4ck5aNJgnnKepwY2sNoSpgXZ/WpxD37HiIF/OMNF7gAr58ddpi73ZOxQ yWjZXl4VcjdHCyBp7KzTJ9AH/NhQ/U+jm1Y9JmhEf6Kx7pRYIJMYrW0MNU5ftQkfFWQW a5Nha3ucH2fgjpyoyGiN98NCbqqkNMU78eJkg12elnnuQpEkJtDf0yq/uKxaqDDyaukV pXvA== ARC-Message-Signature: i=1; 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X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v2 3/3] target/arm: Implement ARMv8.0-PredRes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is named "Execution and Data prediction restriction instructions" within the ARMv8.5 manual, and given the name "PredRes" by binutils. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 13 ++++++++++- target/arm/cpu.c | 1 + target/arm/cpu64.c | 2 ++ target/arm/helper.c | 55 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 70 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1a6ca35ea7..e1acc711cf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1060,7 +1060,8 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ #define SCTLR_F (1U << 10) /* up to v6 */ -#define SCTLR_SW (1U << 10) /* v7, RES0 in v8 */ +#define SCTLR_SW (1U << 10) /* v7 */ +#define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ #define SCTLR_I (1U << 12) @@ -3294,6 +3295,11 @@ static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; } +static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* @@ -3397,6 +3403,11 @@ static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; } +static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7940d49c1d..b78e1d610e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2004,6 +2004,7 @@ static void arm_max_initfn(Object *obj) t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); t = FIELD_DP32(t, ID_ISAR6, DP, 1); t = FIELD_DP32(t, ID_ISAR6, SB, 1); + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 = t; t = cpu->id_mmfr4; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 168aa9e0f1..92c75cbfa6 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -318,6 +318,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); + t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); cpu->isar.id_aa64isar1 = t; t = cpu->isar.id_aa64pfr0; @@ -349,6 +350,7 @@ static void aarch64_max_initfn(Object *obj) u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); u = FIELD_DP32(u, ID_ISAR6, DP, 1); u = FIELD_DP32(u, ID_ISAR6, SB, 1); + u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 = u; /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 8a71a80dfd..554f111ea8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5742,6 +5742,50 @@ static const ARMCPRegInfo pauth_reginfo[] = { }; #endif +static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el = arm_current_el(env); + + if (el == 0) { + uint64_t sctlr = arm_sctlr(env, el); + if (!(sctlr & SCTLR_EnRCTX)) { + return CP_ACCESS_TRAP; + } + } else if (el == 1) { + uint64_t hcr = arm_hcr_el2_eff(env); + if (hcr & HCR_NV) { + return CP_ACCESS_TRAP_EL2; + } + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo predinv_reginfo[] = { + { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4, + .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, + { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, + { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64, + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7, + .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, + /* + * Note the AArch32 opcodes have a different OPC1. + */ + { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32, + .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4, + .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, + { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32, + .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5, + .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, + { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32, + .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7, + .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -6641,6 +6685,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, pauth_reginfo); } #endif + + /* + * While all v8.0 cpus support aarch64, QEMU does have configurations + * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max, + * which will set ID_ISAR6. + */ + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) + ? cpu_isar_feature(aa64_predinv, cpu) + : cpu_isar_feature(aa32_predinv, cpu)) { + define_arm_cp_regs(cpu, predinv_reginfo); + } } void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)