From patchwork Mon Oct 10 12:52:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 614982 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 84D00C433F5 for ; Mon, 10 Oct 2022 12:52:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230083AbiJJMwJ (ORCPT ); Mon, 10 Oct 2022 08:52:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229986AbiJJMwI (ORCPT ); Mon, 10 Oct 2022 08:52:08 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0EB4C52DC0; Mon, 10 Oct 2022 05:52:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665406327; x=1696942327; h=from:to:subject:date:message-id:mime-version: content-transfer-encoding; bh=JHiNEn1VO1XjaqbGRbNtJMKQOanLaGLJSkjjUAgEfvs=; b=jfk/0B2BdOKmb2vCJamDAG+La+k8g438xd4ozEFXIge5jSUNH/WXikGQ Ys4nC1JxN6IUivCZHnHNLt1Ahd5LFHghoiitnvAXxqOO1K+bV9qkZq3xD fzlc4xQ3K0LNMaXgz5O5X+laEd9yj0spT3Moxc6plGYDehuSYAcThdXd+ gpajC0fUMHZQf3EHfT1oWFSS9smmlnldu8HafPVcnSRTrrCCu71tVvuGJ Sd6H2EfywBXjmIkY1cTSjB+663nc0+i1g96M0LDlleLFVvC6dMGm/1QP9 /uK0p6STU4p34A+YBHiFMUuptM2y6q1ShZb7C+/nZwCv9m7dpWNLfwZtK g==; X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="366181070" X-IronPort-AV: E=Sophos;i="5.95,173,1661842800"; d="scan'208";a="366181070" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2022 05:52:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="628266211" X-IronPort-AV: E=Sophos;i="5.95,173,1661842800"; d="scan'208";a="628266211" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga007.fm.intel.com with ESMTP; 10 Oct 2022 05:52:04 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id EA3512B0; Mon, 10 Oct 2022 15:52:24 +0300 (EEST) From: Andy Shevchenko To: Linus Walleij , Andy Shevchenko , Patrick Rudolph , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/2] pinctrl: cy8c95x0: Extract cy8c95x0_set_mode() helper Date: Mon, 10 Oct 2022 15:52:20 +0300 Message-Id: <20221010125221.28275-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The code in newly introduced cy8c95x0_set_mode() helper may be used later on by another function. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 68509a2301b8..33eba7ad87f4 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -1124,9 +1124,7 @@ static int cy8c95x0_get_function_groups(struct pinctrl_dev *pctldev, unsigned in return 0; } -static int cy8c95x0_pinmux_cfg(struct cy8c95x0_pinctrl *chip, - unsigned int val, - unsigned long off) +static int cy8c95x0_set_mode(struct cy8c95x0_pinctrl *chip, unsigned int off, bool mode) { u8 port = cypress_get_port(chip, off); u8 bit = cypress_get_pin_mask(chip, off); @@ -1137,7 +1135,20 @@ static int cy8c95x0_pinmux_cfg(struct cy8c95x0_pinctrl *chip, if (ret < 0) return ret; - ret = regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, val ? bit : 0); + return regmap_write_bits(chip->regmap, CY8C95X0_PWMSEL, bit, mode ? bit : 0); +} + +static int cy8c95x0_pinmux_mode(struct cy8c95x0_pinctrl *chip, + unsigned int selector, unsigned int group) +{ + u8 port = cypress_get_port(chip, group); + u8 bit = cypress_get_pin_mask(chip, group); + int ret; + + if (selector == 0) + return cy8c95x0_set_mode(chip, group, false); + + ret = cy8c95x0_set_mode(chip, group, true); if (ret < 0) return ret; @@ -1156,7 +1167,7 @@ static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, int ret; mutex_lock(&chip->i2c_lock); - ret = cy8c95x0_pinmux_cfg(chip, selector, group); + ret = cy8c95x0_pinmux_mode(chip, selector, group); mutex_unlock(&chip->i2c_lock); return ret; From patchwork Mon Oct 10 12:52:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 613983 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64AD4C433FE for ; Mon, 10 Oct 2022 12:52:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230168AbiJJMwJ (ORCPT ); Mon, 10 Oct 2022 08:52:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229527AbiJJMwJ (ORCPT ); Mon, 10 Oct 2022 08:52:09 -0400 Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D7D252E53; Mon, 10 Oct 2022 05:52:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1665406328; x=1696942328; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=3zHevgQOY48FMYBp2kdOdzu7Asoft6NnnDPXhDghaMo=; b=AU/RM2n0xP80UGd0O53/q+rPzSk8hBWU4iLnLhzDMXACwnfUyyKz+Zcz mvOuW6WERssPEJeXwnEzqunNGMSQLml8ddl9xainzKKmc9kZl9UfjnS8W beZ8VgLXiq7tjDKjSPxHFWMkVtfC5HMMAt/tvrQ4EMRq3uvbmylV3HAOh MS6Sxgk4oCjeYGSQvkhc6QG14+ZrLGWJORz0L9HlEHbV5HPGyLFCjK4BD vk5nShlVEB0OZDU3n3Zf/XQxymzJnMtN/6mzg7RfOoy+0N9kG4fo/ttIL HHLa1rXtzlucTaUNBYgnoTWK6qhY/e/MDbJHyXrPjSPydciQ4ASNAV9zp g==; X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="366181071" X-IronPort-AV: E=Sophos;i="5.95,173,1661842800"; d="scan'208";a="366181071" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Oct 2022 05:52:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10496"; a="628266212" X-IronPort-AV: E=Sophos;i="5.95,173,1661842800"; d="scan'208";a="628266212" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga007.fm.intel.com with ESMTP; 10 Oct 2022 05:52:05 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 97D1430B; Mon, 10 Oct 2022 15:52:25 +0300 (EEST) From: Andy Shevchenko To: Linus Walleij , Andy Shevchenko , Patrick Rudolph , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 2/2] pinctrl: cy8c95x0: Implement ->gpio_request_enable() and ->gpio_set_direction() Date: Mon, 10 Oct 2022 15:52:21 +0300 Message-Id: <20221010125221.28275-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221010125221.28275-1-andriy.shevchenko@linux.intel.com> References: <20221010125221.28275-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Without ->gpio_request_enable() and ->gpio_set_direction() callbacks it's not possible to mux GPIO via standard GPIO interfaces (like `gpioget` or `gpioset` tools in user space). Implement those functions to fill the above mentioned gap. Signed-off-by: Andy Shevchenko --- drivers/pinctrl/pinctrl-cy8c95x0.c | 112 +++++++++++++++++------------ 1 file changed, 68 insertions(+), 44 deletions(-) diff --git a/drivers/pinctrl/pinctrl-cy8c95x0.c b/drivers/pinctrl/pinctrl-cy8c95x0.c index 33eba7ad87f4..b44b36be54b3 100644 --- a/drivers/pinctrl/pinctrl-cy8c95x0.c +++ b/drivers/pinctrl/pinctrl-cy8c95x0.c @@ -21,9 +21,10 @@ #include #include -#include +#include #include #include +#include #include /* Fast access registers */ @@ -551,36 +552,7 @@ static int cy8c95x0_read_regs_mask(struct cy8c95x0_pinctrl *chip, int reg, static int cy8c95x0_gpio_direction_input(struct gpio_chip *gc, unsigned int off) { - struct cy8c95x0_pinctrl *chip = gpiochip_get_data(gc); - u8 port = cypress_get_port(chip, off); - u8 bit = cypress_get_pin_mask(chip, off); - int ret; - - mutex_lock(&chip->i2c_lock); - ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); - if (ret) - goto out; - - ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, bit); - if (ret) - goto out; - - if (test_bit(off, chip->push_pull)) { - /* - * Disable driving the pin by forcing it to HighZ. Only setting the - * direction register isn't sufficient in Push-Pull mode. - */ - ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit); - if (ret) - goto out; - - __clear_bit(off, chip->push_pull); - } - -out: - mutex_unlock(&chip->i2c_lock); - - return ret; + return pinctrl_gpio_direction_input(gc->base + off); } static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc, @@ -597,19 +569,7 @@ static int cy8c95x0_gpio_direction_output(struct gpio_chip *gc, if (ret) return ret; - mutex_lock(&chip->i2c_lock); - /* Select port... */ - ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); - if (ret) - goto out; - - /* ...then direction */ - ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, 0); - -out: - mutex_unlock(&chip->i2c_lock); - - return ret; + return pinctrl_gpio_direction_output(gc->base + off); } static int cy8c95x0_gpio_get_value(struct gpio_chip *gc, unsigned int off) @@ -850,6 +810,8 @@ static int cy8c95x0_setup_gpiochip(struct cy8c95x0_pinctrl *chip) { struct gpio_chip *gc = &chip->gpio_chip; + gc->request = gpiochip_generic_request; + gc->free = gpiochip_generic_free; gc->direction_input = cy8c95x0_gpio_direction_input; gc->direction_output = cy8c95x0_gpio_direction_output; gc->get = cy8c95x0_gpio_get_value; @@ -1173,11 +1135,73 @@ static int cy8c95x0_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, return ret; } +static int cy8c95x0_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin) +{ + struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); + int ret; + + mutex_lock(&chip->i2c_lock); + ret = cy8c95x0_set_mode(chip, pin, false); + mutex_unlock(&chip->i2c_lock); + + return ret; +} + +static int cy8c95x0_pinmux_direction(struct cy8c95x0_pinctrl *chip, + unsigned int pin, bool input) +{ + u8 port = cypress_get_port(chip, pin); + u8 bit = cypress_get_pin_mask(chip, pin); + int ret; + + /* Select port... */ + ret = regmap_write(chip->regmap, CY8C95X0_PORTSEL, port); + if (ret) + return ret; + + /* ...then direction */ + ret = regmap_write_bits(chip->regmap, CY8C95X0_DIRECTION, bit, input ? bit : 0); + if (ret) + return ret; + + /* + * Disable driving the pin by forcing it to HighZ. Only setting + * the direction register isn't sufficient in Push-Pull mode. + */ + if (input && test_bit(pin, chip->push_pull)) { + ret = regmap_write_bits(chip->regmap, CY8C95X0_DRV_HIZ, bit, bit); + if (ret) + return ret; + + __clear_bit(pin, chip->push_pull); + } + + return 0; +} + +static int cy8c95x0_gpio_set_direction(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int pin, bool input) +{ + struct cy8c95x0_pinctrl *chip = pinctrl_dev_get_drvdata(pctldev); + int ret; + + mutex_lock(&chip->i2c_lock); + ret = cy8c95x0_pinmux_direction(chip, pin, input); + mutex_unlock(&chip->i2c_lock); + + return ret; +} + static const struct pinmux_ops cy8c95x0_pmxops = { .get_functions_count = cy8c95x0_get_functions_count, .get_function_name = cy8c95x0_get_function_name, .get_function_groups = cy8c95x0_get_function_groups, .set_mux = cy8c95x0_set_mux, + .gpio_request_enable = cy8c95x0_gpio_request_enable, + .gpio_set_direction = cy8c95x0_gpio_set_direction, .strict = true, };