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Mon, 10 Oct 2022 13:23:24 +0000 From: =?utf-8?q?Levente_R=C3=A9v=C3=A9sz?= To: Linus Walleij , Bartosz Golaszewski Cc: linux-gpio@vger.kernel.org, =?utf-8?q?Levente_R=C3=A9v=C3=A9sz?= Subject: [PATCH 1/2] gpio: pca953x: Generalize interrupt mask register handling Date: Mon, 10 Oct 2022 15:20:06 +0200 Message-Id: <20221010132007.924810-2-levente.revesz@eilabs.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221010132007.924810-1-levente.revesz@eilabs.com> References: <20221010132007.924810-1-levente.revesz@eilabs.com> X-ClientProxiedBy: VI1PR06CA0146.eurprd06.prod.outlook.com (2603:10a6:803:a0::39) To VI1P194MB0655.EURP194.PROD.OUTLOOK.COM (2603:10a6:800:147::21) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: VI1P194MB0655:EE_|VI1P194MB0656:EE_ X-MS-Office365-Filtering-Correlation-Id: 2e4dfaed-95b8-4597-8b46-08daaac29b9e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: mwSpxjfkLbZWf1IUfk8A5finhQbtCC3yFHF+359b2rCY1/JVlNta28PY9bUY2Tt/P9obXmaB5Yk6ol9LNLB5KkLRebbXN69SW+PSKlv0KEKABTumkH313d8VkgTLIF935CkqWz726xDLCQY2F6/1H4VwfbBwC7mEkUru3/xEZwZDzP3URDEPr0o3OyLwOQcJ3Kb1xwzZ7wxB9PCMz9RLaXCjgwTnXkrxxJx9pE4NGtZG4OejX8Wp/EUklKuvaTgB3Dgg55GuVrexm6cK/qwDXk80ntE+zoJ+noy/vARGF2U7Bf69AHoM31+QN0rvW24+i4ZVPX2u3wMo/ca5XSVKDJYwY4pNmiE5WxSiEGshdiLSJdR8NcCeZj1ip46OD7Z9VLPYVP0zB8nsoGWdN7IPcMp65ea5RTFh5jQEBKjd3T6BozJU+T7/oSp0rWpPMe/RuH3ocWwRwSJLABqbZHtOywDV9h6Qz4JW/EO/TqRfiNN1DDhy9VfNv44/gOQ7tMS5Hu9W+E0Cp0VOgAv4zQQYvWAjKnyevevtuc1aYLsn9IZs+jb0H7PfQICdgr68p7cclOkkbVwc79/lY9ogd1npMPC4YwGu/qj4FjBa+c4xtNiQgUYpkoCex/9sUUmmZey9uFCdfyO/zpAZAC6YLArRQSKQQ9KzNN+5ZUA7//HgIzRx2r9ybDG60BI1ubja4DUp4pMU3ssyXWs4z4w6K3XMMwIROt72T6YA+ZLnbgVVRrvZz4EFQ0jbNYRcIUwiUtUK83yKtdAkRhWu1G5snvwbdg== X-Forefront-Antispam-Report: CIP:255.255.255.255; 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Currenty the only interrupt mask register the driver handles is PCAL953x_INT_MASK present in the pcal chips. The functions handling this register can easily be made generic enough to handle the interrupt mask register of other chips that do not use the pcal register set, and have their interrupt mask register at a different address. Add bit flag PCA_HAS_INT_MASK, which is set for each chip with an interrupt mask register (including pcal chips). Define a convenience bitmask PCA_MASKED_INT similar to PCA_LATCH_INT. Add an int_mask member to struct pca953x_reg_config. This way interrupt mask handling code can work with registers at different addresses. Add separate pca953x_reg_config for pcal953x chips. This differs from the pca953x_regs in the new int_mask field. In pca953x_readable_register and pca953x_writeable_register only check for PCA_PCAL if the chip is not PCA957X_TYPE. No chip is both pca957x and pcal. This makes logic for adding a different interrupt mask register cleaner. Signed-off-by: Levente Révész --- drivers/gpio/gpio-pca953x.c | 64 +++++++++++++++++++++++++------------ 1 file changed, 43 insertions(+), 21 deletions(-) diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index 61e874c0cde4..71bfc38c3930 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -63,7 +63,9 @@ #define PCA_INT BIT(8) #define PCA_PCAL BIT(9) -#define PCA_LATCH_INT (PCA_PCAL | PCA_INT) +#define PCA_HAS_INT_MASK BIT(10) +#define PCA_MASKED_INT (PCA_HAS_INT_MASK | PCA_INT) +#define PCA_LATCH_INT (PCA_PCAL | PCA_MASKED_INT) #define PCA953X_TYPE BIT(12) #define PCA957X_TYPE BIT(13) #define PCAL653X_TYPE BIT(14) @@ -177,6 +179,7 @@ struct pca953x_reg_config { int output; int input; int invert; + int int_mask; }; static const struct pca953x_reg_config pca953x_regs = { @@ -186,6 +189,14 @@ static const struct pca953x_reg_config pca953x_regs = { .invert = PCA953X_INVERT, }; +static const struct pca953x_reg_config pcal953x_regs = { + .direction = PCA953X_DIRECTION, + .output = PCA953X_OUTPUT, + .input = PCA953X_INPUT, + .invert = PCA953X_INVERT, + .int_mask = PCAL953X_INT_MASK, +}; + static const struct pca953x_reg_config pca957x_regs = { .direction = PCA957X_CFG, .output = PCA957X_OUT, @@ -356,12 +367,13 @@ static bool pca953x_readable_register(struct device *dev, unsigned int reg) } else { bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; - } - if (chip->driver_data & PCA_PCAL) { - bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | - PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | - PCAL9xxx_BANK_IRQ_STAT; + if (chip->driver_data & PCA_PCAL) + bank |= PCAL9xxx_BANK_IN_LATCH | + PCAL9xxx_BANK_PULL_EN | + PCAL9xxx_BANK_PULL_SEL | + PCAL9xxx_BANK_IRQ_MASK | + PCAL9xxx_BANK_IRQ_STAT; } return chip->check_reg(chip, reg, bank); @@ -378,11 +390,13 @@ static bool pca953x_writeable_register(struct device *dev, unsigned int reg) } else { bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; - } - if (chip->driver_data & PCA_PCAL) - bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | - PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; + if (chip->driver_data & PCA_PCAL) + bank |= PCAL9xxx_BANK_IN_LATCH | + PCAL9xxx_BANK_PULL_EN | + PCAL9xxx_BANK_PULL_SEL | + PCAL9xxx_BANK_IRQ_MASK; + } return chip->check_reg(chip, reg, bank); } @@ -764,14 +778,16 @@ static void pca953x_irq_bus_sync_unlock(struct irq_data *d) DECLARE_BITMAP(reg_direction, MAX_LINE); int level; - if (chip->driver_data & PCA_PCAL) { - /* Enable latch on interrupt-enabled inputs */ - pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); - + if (chip->driver_data & PCA_HAS_INT_MASK) { bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio); /* Unmask enabled interrupts */ - pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask); + pca953x_write_regs(chip, chip->regs->int_mask, irq_mask); + } + + if (chip->driver_data & PCA_PCAL) { + /* Enable latch on interrupt-enabled inputs */ + pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); } /* Switch direction to input if needed */ @@ -1171,7 +1187,11 @@ static int pca953x_probe(struct i2c_client *client, chip->regs = &pca957x_regs; ret = device_pca957x_init(chip, invert); } else { - chip->regs = &pca953x_regs; + if (chip->driver_data & PCA_PCAL) + chip->regs = &pcal953x_regs; + else + chip->regs = &pca953x_regs; + ret = device_pca95xx_init(chip, invert); } if (ret) @@ -1245,21 +1265,23 @@ static int pca953x_regcache_sync(struct device *dev) } #ifdef CONFIG_GPIO_PCA953X_IRQ - if (chip->driver_data & PCA_PCAL) { - regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0); + if (chip->driver_data & PCA_HAS_INT_MASK) { + regaddr = pca953x_recalc_addr(chip, chip->regs->int_mask, 0); ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); if (ret) { - dev_err(dev, "Failed to sync INT latch registers: %d\n", + dev_err(dev, "Failed to sync INT mask registers: %d\n", ret); return ret; } + } - regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0); + if (chip->driver_data & PCA_PCAL) { + regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0); ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); if (ret) { - dev_err(dev, "Failed to sync INT mask registers: %d\n", + dev_err(dev, "Failed to sync INT latch registers: %d\n", ret); return ret; } From patchwork Mon Oct 10 13:20:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?UsOpdsOpc3osIExldmVudGU=?= X-Patchwork-Id: 613981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E21FFC433FE for ; Mon, 10 Oct 2022 13:23:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229520AbiJJNXe (ORCPT ); Mon, 10 Oct 2022 09:23:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229475AbiJJNXd (ORCPT ); Mon, 10 Oct 2022 09:23:33 -0400 Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-eopbgr70052.outbound.protection.outlook.com [40.107.7.52]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1696963FCC for ; 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Add PCA_953X_INT_MASK register. Use it as the interrupt register of (non-pcal) pca953x chips. Set pca9505 and pca9506 to use this register. Signed-off-by: Levente Révész --- drivers/gpio/gpio-pca953x.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index 71bfc38c3930..bb8355540a46 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -28,6 +28,7 @@ #define PCA953X_OUTPUT 0x01 #define PCA953X_INVERT 0x02 #define PCA953X_DIRECTION 0x03 +#define PCA953X_INT_MASK 0x04 #define REG_ADDR_MASK GENMASK(5, 0) #define REG_ADDR_EXT BIT(6) @@ -76,8 +77,8 @@ static const struct i2c_device_id pca953x_id[] = { { "pca6408", 8 | PCA953X_TYPE | PCA_INT, }, { "pca6416", 16 | PCA953X_TYPE | PCA_INT, }, - { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, - { "pca9506", 40 | PCA953X_TYPE | PCA_INT, }, + { "pca9505", 40 | PCA953X_TYPE | PCA_MASKED_INT, }, + { "pca9506", 40 | PCA953X_TYPE | PCA_MASKED_INT, }, { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, { "pca9536", 4 | PCA953X_TYPE, }, @@ -187,6 +188,7 @@ static const struct pca953x_reg_config pca953x_regs = { .output = PCA953X_OUTPUT, .input = PCA953X_INPUT, .invert = PCA953X_INVERT, + .int_mask = PCA953X_INT_MASK, }; static const struct pca953x_reg_config pcal953x_regs = { @@ -240,6 +242,7 @@ static int pca953x_bank_shift(struct pca953x_chip *chip) #define PCA953x_BANK_OUTPUT BIT(1) #define PCA953x_BANK_POLARITY BIT(2) #define PCA953x_BANK_CONFIG BIT(3) +#define PCA953x_BANK_INT_MASK BIT(4) #define PCA957x_BANK_INPUT BIT(0) #define PCA957x_BANK_POLARITY BIT(1) @@ -261,6 +264,8 @@ static int pca953x_bank_shift(struct pca953x_chip *chip) * Output port 0x00 + 1 * bank_size RW * Polarity Inversion port 0x00 + 2 * bank_size RW * Configuration port 0x00 + 3 * bank_size RW + * - Some chips have the standard layout with additional interrupt mask: + * Interrupt Mask port 0x00 + 4 * bank_size RW * - PCA957x with mixed up registers * Input port 0x00 + 0 * bank_size R * Polarity Inversion port 0x00 + 1 * bank_size RW @@ -374,6 +379,8 @@ static bool pca953x_readable_register(struct device *dev, unsigned int reg) PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | PCAL9xxx_BANK_IRQ_STAT; + else if (chip->driver_data & PCA_HAS_INT_MASK) + bank |= PCA953x_BANK_INT_MASK; } return chip->check_reg(chip, reg, bank); @@ -396,6 +403,8 @@ static bool pca953x_writeable_register(struct device *dev, unsigned int reg) PCAL9xxx_BANK_PULL_EN | PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; + else if (chip->driver_data & PCA_HAS_INT_MASK) + bank |= PCA953x_BANK_INT_MASK; } return chip->check_reg(chip, reg, bank); @@ -1342,8 +1351,8 @@ static int pca953x_resume(struct device *dev) static const struct of_device_id pca953x_dt_ids[] = { { .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), }, { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, - { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, - { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), }, + { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_MASKED_INT), }, + { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_MASKED_INT), }, { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), },